KR20050066955A - Predistortion linealizer for power amplifier - Google Patents

Abstract

The predistortion linearizer of the present invention is a predistortion linearizer for suppressing gain and phase distortion of a power amplifier disposed between an input terminal and an output terminal, and is disposed between the input terminal and the power amplifier and includes a base-emitter junction diode. And a resistor disposed in series between the transistor and the power amplifier.

Description

Predistortion linealizer for power amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high efficiency and linear micro power amplifiers used in mobile and satellite communications, and more particularly to predistortion linearizers for compensating gain and phase distortion of power amplifiers.

In general, to increase the efficiency of power amplifiers used in mobile and satellite communications, power amplifiers should be operated near the saturation region. However, when the power amplifier is operated near the saturation region, a problem arises in that amplitude and phase distortion increase as the input power increases. When amplitude and phase distortions occur, interference between adjacent channels occurs, degrading the performance of the system. Various methods have been proposed to compensate for amplitude and phase distortion, one of which is to place a predistortion linealizer in front of the power amplifier.

1 is a circuit diagram illustrating a general power amplifier. 2 illustrates gain and phase characteristics of an input power of a power amplifier having a predistortion linearizer.

Referring first to FIG. 1, a transistor Q11 as a power amplifier is disposed between an input terminal P11 and an output terminal P12. The base of transistor Q11 is connected to input terminal P11 and the collector is connected to output terminal P12. A bias circuit composed of resistors R11 and R12 is disposed between the input terminal P11 and the base of the transistor Q11.

As the input power increases, the rectified current of the base-emitter diode of transistor Q11 increases. However, due to the resistors R11 and R12 constituting the bias circuit, the voltage across the base-emitter diode of the transistor Q11 decreases. As a result, the gain of the output signal has a negative distortion change amount that decreases as the input power increases. On the other hand, when the input power increases, the base-collector junction capacitance of the transistor Q11 changes, and as a result, the phase of the output signal has a positive amount of distortion change that increases with the increase of the input power.

Next, referring to FIG. 2, the predistortion linearizer 210 and the power amplifier 220 are sequentially disposed between the input terminal P21 and the output terminal P22. As shown in graph (b), the power amplifier 220 generates an output signal in which the gain decreases and the phase increases as the input power increases. In contrast, the predistortion linearizer 210 generates an output signal in which the gain increases and the phase decreases as the input power increases, as shown in the graph (a). The gain increase and phase reduction of the predistortion linearizer 210 compensate for the gain decrease and the phase increase of the power amplifier 220, and finally, as shown in graph (c), even if the input power increases, the gain and phase The output signal without distortion is generated.

3 is a circuit diagram illustrating a conventional example of the predistortion linearizer of FIG. 2.

Referring to FIG. 3, a capacitor Cp31 and a diode D31 connected in parallel to each other are disposed between the input terminal P31 and the output terminal P32. The anode of the diode D31 faces the input terminal P31 and the cathode faces the output terminal P32. Capacitors C31 and C32 for blocking DC current are respectively disposed between the diode D31 and the input terminal P31 and between the diode D31 and the output terminal P32, respectively. In the drawing, inductors L31 and L32 are for DC current feed, and reference numeral “Vcc31” denotes a bias applying terminal.

In the predistortion linearizer having such a structure, when the input power is increased, the amplitude increases and the phase decreases due to the nonlinearity of the equivalent resistance of the diode D31, and the gain reduction and phase of the power amplifier are caused by such characteristics. You can compensate for the increase. However, the predistortion linearizer requires a separate bias circuit for driving the diode D31, and as a result, additional current consumption occurs.

4 is a circuit diagram illustrating another conventional example of the predistortion linearizer of FIG. 2.

Referring to FIG. 4, the predistortion linearizer includes a diode D41 connected in parallel between an input terminal P41 and an output terminal P42, a bias feed resistor R41, and capacitors C41 and C42 for blocking a DC current. do. In such a predistortion linearizer, when the input power increases, the voltage Vd applied to the diode D41 decreases due to the voltage drop caused by the rectified current flowing through the diode D41. As the voltage Vd decreases, the equivalent resistance of the diode D41 increases, so that the amplitude increases and the phase shows a reduced output characteristic. However, the predistortion linearizer also requires a separate bias circuit for driving the diode D41, and as a result, additional current consumption occurs.

FIG. 5 is a circuit diagram illustrating another conventional example of the predistortion linearizer of FIG. 2.

Referring to FIG. 5, the base and the collector of the transistor Q51 used as the amplifier are connected to the input terminal P51 and the output terminal P52, respectively. The base of transistor Q51 is connected to the collector of transistor Q52. The base of the transistor Q52 is connected to the bias applied voltage terminal Vbb51 through a resistor R52. The base-collector diode of transistor Q52 and resistor R52 form a base biasing circuit of transistor Q51 while at the same time forming a predistortion linearizer. The resistor R51 connected between the base-emitter of the transistor Q52 has no effect on the linearizer, and the transistor Q52 is for forming a forward bias, and the current between the base and the emitter of the transistor Q42 Does not flow. The capacitor C52 is to provide a low impedance to the ultra-high frequency (RF) signal applied from the input terminal P51.

In such a predistortion linearizer, as the input power increases, the rectified current flowing through the base-collector diode of the transistor Q52 increases and the dc voltage across the diode decreases. As the base-collector voltage of transistor Q52 decreases, the base-emitter voltage of transistor Q51 increases slightly. The increase in the base-emitter voltage of the transistor Q51 may improve the gain attenuation and phase distortion characteristics of the transistor Q51 as the input power increases.

Unlike the predistortion linearizers of FIGS. 3 and 4, such a predistortion linearizer has an advantage that a separate bias circuit for driving the base-collector diode of the transistor Q52 is not required, but it is saturated to obtain high efficiency characteristics. In the design of a power amplifier having an operating point near an area, for example, a class AB power amplifier, there is a disadvantage in that it is impossible to control an increase in driving current according to input power.

FIG. 6 is a circuit diagram illustrating another conventional example of the predistortion linearizer of FIG. 2.

Referring to FIG. 6, the base and the collector of the transistor Q61 used as the amplifier are connected to the input terminal P61 and the output terminal P62, respectively. The base of transistor Q61 is connected to the emitter of transistor Q62. The base-emitter diode of transistor Q62 and the shunt capacitor C61 constitute a predistortion linearizer. The collector of transistor Q62 is connected to bias voltage application terminal Vref61. Transistors Q63 and Q64 acting as diodes are arranged to provide a constant constant voltage at the base of transistor Q62.

The operation of the predistortion linearizer is similar to the predistortion linearizer of FIG. 5 in that a capacitor C61 connected in parallel with the transistor Q62 is used. That is, the impedance of the resistor R and the two series diodes Q63 and Q64 is greater than the impedance of the capacitor C61 at the RF frequency, so that all the microwave signals at the base of the transistor Q62 are capacitors ( Flow through C61 keeps the voltage at the base of transistor Q62 constant. When the input power increases, the base bias drop of the transistor Q61 is compensated by the voltage drop of the base-emitter diode of the transistor Q62.

However, even in such a predistortion linearizer, the design of a power amplifier having an operating point near a saturation region, for example, a class AB power amplifier, has a disadvantage in that it does not control an increase in driving current according to input power in order to obtain high efficiency characteristics.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a predistortion linearizer of a power amplifier capable of controlling an increase in driving current according to input power without requiring a bias circuit of a diode constituting the predistortion linearizer. .

In order to achieve the above technical problem, the predistortion linearizer according to the present invention, in the predistortion linearizer for suppressing the gain and phase distortion of the power amplifier disposed between the input stage and the output stage, is disposed between the input stage and the power amplifier A transistor comprising a base-emitter junction diode; And a resistor disposed in series between the transistor and the power amplifier.

The power amplifier is preferably a bipolar junction transistor including a heterojunction.

In this case, it is preferable that the bipolar junction transistor is an npn type bipolar junction transistor having a base connected to the input terminal and the resistor and a collector connected to the output terminal.

The transistor constituting the predistortion linearizer is preferably an npn type bipolar junction transistor including a heterojunction.

In this case, the emitter of the npn type bipolar junction transistor constituting the predistortion linearizer is preferably connected in series with the resistor.

And a bias resistor and a diode connected in parallel to the npn type bipolar junction transistor and the resistor constituting the predistortion linearizer.

In this case, two or more diodes are connected in series, and each of the diodes is preferably an npn type bipolar junction transistor including a heterojunction to which a base and a collector are connected.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

7 is a circuit diagram illustrating a predistortion linearizer according to the present invention.

Referring to FIG. 7, the base and the collector of the transistor Q71 used as the power amplifier are connected to the input terminal P71 and the output terminal P72, respectively. A capacitor C71 is disposed between the base of the transistor Q71 and the input terminal P71. The capacitor C72 is also disposed between the collector of the transistor Q71 and the output terminal P72. These capacitors C71 and C72 are for blocking direct current. The voltage Vcc is applied to the collector of the transistor Q71 through the inductor L71. The transistor Q72 and the resistor R72 constituting the predistortion linearizer 700 are connected to the base of the transistor Q71. The base of transistor Q71 is connected to the emitter of transistor Q72 via resistor R72. In the present embodiment, the transistors Q71 and Q72 are all npn type bipolar junction transistors BJT including heterojunctions.

The reference voltage Vref is applied to the collector of the transistor Q72. In parallel with the transistor Q72 and the resistor R72, the resistor R71 and the transistors Q73 and Q74 are connected in series. The transistors Q73 and Q74 form a bias circuit, and both are npn type bipolar junction transistors, and the collector and the base are connected to operate as a diode. The resistor R71 and the transistors Q73 and Q74 also receive a reference voltage Vref.

The operation of the predistortion linearizer 700 having such a configuration is as follows.

The voltage V71 at the base of transistor Q72 is held constant by transistors Q73 and Q74. When the input power increases in this state, the base-emitter voltage of the transistor Q72 increases. When the base-emitter voltage of the transistor Q72 increases, the decrease in the base-emitter voltage of the transistor Q71 as the power amplifier is suppressed. This increases the linearity of the power amplifier by increasing the gain attenuation point at which the gain due to the reduction of the base-emitter voltage of transistor Q71 begins to distort. In this case, the resistor R72 performs a function of controlling the rectified current that increases together with the increase of the input power. That is, by having a resistance value of an appropriate size, it is possible to control the amount of change in the current increases when the operating point changes with the increase in the rectified current, thereby improving the efficiency of the power amplifier.

8 is a graph showing the power added efficiency characteristics with respect to the input power of the power amplifier having a predistortion linearizer according to the present invention.

Referring to FIG. 8, as the input power increases, the power added efficiency (PAE) also increases. The degree of increase at this time depends on the resistance value of the resistor R72. Specifically, the line denoted by reference numeral 810 denotes a case where the resistance value of the resistor R72 is 40 kW, and the line denoted by reference numeral 820 denotes a case where the resistance value of the resistor R72 is 90 kPa. The line indicated by "830" is the case where the resistance value of the resistor R72 is 140 kPa, the line denoted by the reference numeral "840" is the case where the resistance value of the resistor R72 is 190 kPa, and the reference numeral "850". The line indicated by is a case where the resistance value of the resistor R72 is 200 kΩ. As shown in the graph, it can be seen that the power added efficiency is higher as the resistance value of the resistor R72 is increased. For example, when the resistance value of the resistor R72 is 200 kPa (see 850), the resistance value of the resistor R72 is increased by approximately 34.8% compared to the case where the resistance value of the resistor R72 is 40 kPa (see 810).

9 is a graph illustrating collector current characteristics of input power of a power amplifier having a predistortion linearizer according to the present invention.

Referring to FIG. 9, as the input power increases, the collector current of the transistor Q71 also increases. The degree of increase at this time depends on the resistance value of the resistor R72. Specifically, the line indicated by reference numeral "910" is a case where the resistance value of the resistor R72 is 40 kW, and the line indicated by reference numeral "920" is a case where the resistance value of the resistor R72 is 90 kPa, The line denoted by "930" is the case where the resistance value of the resistor R72 is 140 kPa, the line denoted by the reference numeral "940" is the case where the resistance value of the resistor R72 is 190 kPa, and the reference numeral "950". The line indicated by is a case where the resistance value of the resistor R72 is 200 kΩ. As shown in the graph, it can be seen that as the resistance value of the resistor R72 increases, the collector current of the transistor Q71 decreases as the input power increases.

As a result, as shown in FIG. 8 and FIG. 9, the power added efficiency can be increased while keeping the output power constant. This increases the current increase due to the increase of the rectified current as the input power increases to the resistor R71. This is because it can be controlled by.

As described above, according to the predistortion linearizer of the power amplifier according to the present invention, in order to configure the predistortion linearizer, the emitter of a transistor having a base-emitter diode and the base of the transistor as a power amplifier are connected between them. By inserting a series resistor into the circuit, gain attenuation of the power amplifier and phase distortion can be reduced, thereby increasing the linearity of the device. In particular, the series resistor can increase the power added efficiency while keeping the output power constant. To provide.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

1 is a circuit diagram illustrating a general power amplifier.

2 is a diagram illustrating gain and phase characteristics of an input power of a power amplifier having a predistortion linearizer.

FIG. 3 is a circuit diagram illustrating a conventional example having the characteristics of the predistortion linearizer of FIG. 2.

4 is a circuit diagram illustrating another conventional example having the characteristics of the predistortion linearizer of FIG. 2.

FIG. 5 is a circuit diagram illustrating another conventional example having the characteristics of the predistortion linearizer of FIG. 2.

FIG. 6 is a circuit diagram illustrating another conventional example having the characteristics of the predistortion linearizer of FIG. 2.

7 is a circuit diagram illustrating a predistortion linearizer according to the present invention.

8 is a graph showing the power added efficiency characteristics with respect to the input power of the power amplifier having a predistortion linearizer according to the present invention.

9 is a graph illustrating collector current characteristics of input power of a power amplifier having a predistortion linearizer according to the present invention.

Claims (7)

In the predistortion linearizer for suppressing the gain and phase distortion of the power amplifier disposed between the input stage and the output stage, A transistor disposed between the input terminal and the power amplifier and including a base-emitter junction diode; And And a resistor disposed in series between the transistor and the power amplifier. The method of claim 1, The power amplifier is a pre-distortion linearizer, characterized in that the bipolar junction transistor. The method of claim 2, And said bipolar junction transistor is an npn type bipolar junction transistor having a base connected to said input terminal and said resistor and a collector connected to said output terminal. The method of claim 1, And the transistor is an npn type bipolar junction transistor. The method of claim 4, wherein And an emitter of the npn type bipolar junction transistor is connected in series with the resistor. The method of claim 4, wherein And a bias resistor and a diode connected in parallel to the npn type bipolar junction transistor and a resistor. The method of claim 6, The two or more diodes are connected in series, each predistortion linearizer characterized in that the npn type bipolar junction transistor connected to the base and the collector.