CN111555725A - Amplifier linearization device - Google Patents
Amplifier linearization device Download PDFInfo
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- CN111555725A CN111555725A CN201911308366.4A CN201911308366A CN111555725A CN 111555725 A CN111555725 A CN 111555725A CN 201911308366 A CN201911308366 A CN 201911308366A CN 111555725 A CN111555725 A CN 111555725A
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- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
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Abstract
The invention provides an amplifier linearizing apparatus, which includes an amplifier and a linearizer. The linearizer includes a first transistor including a first terminal coupled to an input of the amplifier, a second terminal coupled to a direct current power supply, and a control terminal configured to control a current flowing between the first terminal and the second terminal and to receive a direct current bias voltage different from a voltage of the first terminal. The present invention enables a lineariser and an amplifier to be combined with improved overall linearity by using the lineariser to compensate the amplifier.
Description
Technical Field
The present invention relates to an amplifier, and more particularly, to improving linearity of an amplifier by using a linearizer (linearizer).
Background
Power amplifiers are known electronic devices for increasing the power of Alternating Current (AC) signals. Generally, an amplifier multiplies a voltage amplitude of an AC signal input to the amplifier by a gain factor using power from a Direct Current (DC) power supply, and provides the multiplied signal as an output.
It is desirable for the amplifier to operate linearly over as wide a range of voltage amplitudes as possible. In the input voltage range in which the amplifier operates linearly, the ac signal output by the amplifier is proportional to the input ac signal by a gain factor that is constant over the input voltage range. In the range of input voltages where the gain factor is not constant, the amplifier operates non-linearly, which is undesirable.
Disclosure of Invention
Accordingly, an object of the present invention is to provide a technique for improving linearity of an amplifier, in which nonlinearity of the amplifier is compensated by using a linearizer (linearizer), to solve the above-mentioned problems.
According to an embodiment of the present invention, there is provided an amplifier linearizing apparatus including an amplifier and a linearizer. The linearizer includes a first transistor including a first terminal coupled to an input of the amplifier, a second terminal coupled to a direct current power supply, and a control terminal configured to control a current flowing between the first terminal and the second terminal and to receive a direct current bias voltage different from a voltage of the first terminal.
According to another embodiment of the present invention, there is provided an amplifier linearizing apparatus including an amplifier and a linearizer. The amplifier includes an input, an output, and a first set of transistors coupled between the input and the output, the first set of transistors including one or more transistors. The linearizer includes a second set of transistors, including one or more transistors, coupled between the direct current power supply and the input of the amplifier. Wherein the first set of transistors and the second set of transistors have the same topology.
The present invention enables a lineariser and an amplifier to be combined with improved overall linearity by using the lineariser to compensate the amplifier.
These and other objects of the present invention will become apparent to those skilled in the art upon a reading of the following detailed description of the preferred embodiments illustrated in the various drawings and drawings.
Drawings
Figure 1A is a block diagram illustrating an example system including an amplifier compensated by a linearizer, in accordance with some embodiments.
FIG. 1B shows a series of graphs corresponding to the system shown in FIG. 1A.
Figure 2A is a circuit diagram of an example system that includes a single-ended amplifier compensated by a linearizer, according to some embodiments.
Fig. 2B is a circuit diagram of an example system that includes a single-ended amplifier compensated by a cascode linearizer, in accordance with some embodiments.
Figure 2C is a circuit diagram of an example system including a differential amplifier compensated with a linearizer, in accordance with some embodiments.
Fig. 3A is a circuit diagram of an example system that includes a cascode differential amplifier compensated with a cascode linearizer, in accordance with some embodiments.
Fig. 3B is a circuit diagram of an example system that includes a cascode single-ended amplifier compensated by a cascode linear amplifier, in accordance with some embodiments.
Figure 4A is a circuit diagram of an example system that includes a single-ended amplifier compensated by a linearizer coupled output, according to some embodiments.
Fig. 4B is a circuit diagram of an example system that includes a cascode differential amplifier compensated by an output-coupled cascode linear amplifier, according to some embodiments.
Fig. 5A is a circuit diagram of an example system that includes a single-ended amplifier compensated with a PMOS linearizer, in accordance with some embodiments.
Figure 5B is a circuit diagram of an example system that includes a single-ended amplifier compensated by a PMOS and NMOS linearizers according to some embodiments.
Detailed Description
The implementation of amplifiers, such as power amplifiers used in radio-frequency (RF) transmission systems, involves a trade-off between the efficiency and linearity of the amplifier. Amplifiers with better linearity typically have poor operating efficiency and typically dissipate more than half of the total operating power as heat rather than being converted into the AC signal at the output of the amplifier. For example, class a power amplifiers can operate linearly over a wide range of input voltages, but operate with less than 50% and often even less than 10% efficiency, as compared to class C (class C) power amplifiers. Amplifiers with better operating efficiency typically have poor linearity and a relatively small voltage range over which the gain factor is constant. For example, class C power amplifiers may operate with efficiencies as high as 70% or more, but operate linearly over a significantly reduced input voltage range compared to class a amplifiers. The choice of amplifier therefore involves a trade-off between efficiency and linearity.
The present invention proposes a technique for improving linearity in a system having a non-linear amplifier by compensating the amplifier using a linearizer (linearizer). The linearizer may be coupled to the input of the amplifier and configured to provide a non-constant impedance transfer function (impedance transfer function) to an AC signal received at the input of the amplifier. The non-constant impedance transfer function of the linearizer can compensate for the non-linear response of the amplifier over a range of input voltages. For example, if the gain factor of the amplifier increases over a certain voltage range due to the non-linearity of the amplifier, the impedance transfer function of the linearizer can be compensated by decreasing over the voltage range, so that the overall linearity of the linearizer together with the amplifier is improved over the entire voltage range. Thus, the linearizer and the amplifier in combination may be implemented with improved overall linearity compared to the amplifier alone.
Fig. 1A is a block diagram illustrating an example system 100, the system 100 including an amplifier 130 compensated by a linearizer 110, in accordance with some embodiments. Linearizer 110 is coupled in parallel with amplifier 130. The inputs 102a and 102b of the system 100 are coupled to each of the linearizer 110 and the amplifier 130, and the outputs 104a and 104b of the system 100 are coupled to the amplifier 130. In some embodiments, outputs 104a and 104b may be coupled to linearizer 110, as shown by the dashed lines in fig. 1A.
The amplifier 130 may be used to multiply the signals received at the inputs 102a and 102b by a gain factor and provide the result to the outputs 104a and 104 b. The amplifier 130 may include one or more transistors, and the gain factor of the amplifier 130 may be set based on the configuration of the transistors, such as the placement and connection of the transistors and the voltage bias conditions.
Linearizer 110 may be used to provide a non-linear shunt impedance (shunt impedance) to AC signals received at inputs 102a and 102b of system 100. For example, linearizer 110 may be coupled between input terminals 102a and 102b and a DC power supply. AC signals received at input terminals 102a and 102b may be conducted through linearizer 110 to a DC power supply such that linearizer 110 provides a shunt impedance for system 100. The linearizer 110 may include one or more transistors, and the non-linear shunt impedance of the linearizer 110 may be set based on the configuration of the transistors (e.g., placement and connection of the transistors, and voltage bias conditions).
In system 100, linearizer 110 in combination with amplifier 130 can provide an overall transfer function with improved linearity as compared to the gain factor of amplifier 130. When combined, the overall transfer function of the system 100 between the input terminals 102a and 102b and the output terminals 104a and 104b is significantly more constant over the AC signal voltage range than the gain factor of the amplifier 130. For example, amplifier 130 may have a non-linear gain factor over a particular voltage range of the signals received at inputs 102a and 102 b. To compensate for the non-linear gain factor of amplifier 130, linearizer 110 may be configured to provide a non-linear impedance such that the overall transfer function between input terminals 102a and 102b and output terminals 104a and 104b has improved linearity over the gain factor of amplifier 130 over this particular voltage range. The gain factor of amplifier 130, the nonlinear impedance of linearizer 110, and the overall transfer function of system 100 will be described herein with reference to fig. 1B.
Although not shown in fig. 1A, it should be understood that linearizer 110 and amplifier 130 are both connected to a DC power supply. For example, linearizer 110 may couple AC signals received at input terminals 102a and 102b to a DC power source, and amplifier 130 may convert power received from the DC power source into signal power to amplify the AC signals at output terminals 104a and 104 b.
FIG. 1B shows a series of graphs 150, 170, and 190 that correspond to various transfer functions of components in the system 100 shown in FIG. 1A. Graph 150 shows impedance transfer function 154 for linearizer 110, as well as constant impedance transfer function 152. Graph 170 shows gain factor 174 for amplifier 130, as well as constant gain factor 172. Graph 190 shows an overall transfer function 194 of system 100 from inputs 102a and 102 to outputs 104a and 104b, as well as a constant transfer function 192. For example, the overall transfer function 194 is the product of the impedance transfer function 154 and the gain factor 174. The impedance transfer function 154, the gain factor 174, and the overall transfer function 194 are at the input voltage VINV of1To V2And (5) drawing within the range.
As shown in graph 150, impedance transfer function 154 of linearizer 110 is at V1To V2From the constant impedance transfer function 152. For example, linearizer 110 may include one or more transistors biased at V1And V2Resulting in a desired non-linear channel impedance (channel impedance). Thus, the impedance transfer function 154 is relative to the slave V1To V2Input voltage V ofINIs non-linear.
As shown in graph 170, the gain factor 174 of amplifier 130 is at voltage V1And V2From a constant gain factor 172. For example, amplifier 130 may be at a voltage V1And V2Class C power amplifiers with poor linearity in between. Thus, the gain factor 174 is relative to the slave V1To V2Input voltage V ofINIs non-linear.
As shown in graph 190, the overall transfer function 194 of system 100 (including amplifier 130 and shunt-coupled linearizer 110) is at a voltage V1And V2Substantially equal to the constant transfer function 192. The product of the impedance transfer function 154 and the gain factor 174 may be generated at a voltage V1And V2An overall transfer function with improved linearity therebetween. For example, the transistors of linearizer 110 may be biased to produce a non-linear channel impedance of the transistors, which may cancel out at voltage V1And V2To the gain factor 174 of the amplifier 130. Since the overall transfer function 194 is the product of the impedance transfer function 154 and the gain factor 174, the overall transfer function 194 is at a voltage V as compared to the gain factor 1741And V2With improved linearity therebetween.
The present invention proposes a linearizer implemented by one or more transistors coupled to an amplifier. For example, the transistors may be coupled to an input of an amplifier, the channels (channels) of the transistors being configured to provide a non-linear impedance to a signal received at the input. Fig. 2A-2C show circuit diagrams of exemplary systems 200a, 200b, and 200C, each having a linearizer implemented with one or more transistors coupled to an amplifier. Each of the systems 200a, 200B, and 200c may be configured to operate in the manner described in connection with the system 100 of fig. 1A-1B.
Fig. 2A is a circuit diagram illustrating a system 200a, the system 200a including a single-ended amplifier 230a compensated by a linearizer 210a coupled between an input 202 and an output 204. System 200a is shown as a single ended system. Thus, the signal received at the input 202 and provided at the output 204 may be a single-ended signal.
The amplifier 230a includes a transistor 232 that may be configured to amplify a signal received at the control terminal and provide an amplifier result at a channel terminal (channel terminal) coupled to the output 204. In the example embodiment of fig. 2A, the transistor 232 is a common-source configured FET, and the control terminal of the transistor 232 is a gate connected to the input 202. The drain of transistor 232 is connected to output 204 and also to a matching network 242 (e.g., a linear passive matching network). The matching network 242 may include passive components such as inductors and/or baluns (baluns). Matching network 242 is coupled to current mirror 240, and current mirror 240 provides current to bias transistor 232. In some embodiments, the drain of transistor 232 may be connected to the source of a cascode transistor (cascode transistor), which may be coupled to current mirror 240. A source of transistor 232 is coupled to a common voltage terminal, such as ground. However, the source of transistor 232 may be coupled to other components. For example, in some embodiments, the source of transistor 232 is coupled to current mirror 240.
In the illustrated common-source configuration, the transistor 232 is configured to receive the AC signal at its gate, amplify the AC signal based on a gain factor, and provide a gained AC signal at its drain. For example, the gain factor may be set based on the DC bias voltage at the gate, drain, and source of transistor 232 and based on the current provided by current mirror 240. The gain factor may be non-linear over the range of AC signal voltages at the gate. At the drain coupled to the output 204, the transistor 232 may provide a gained AC signal.
It should be understood that some embodiments do not include current mirror 240. For example, in some embodiments, the matching network 242 may be coupled to the DC power source 206. In some embodiments, transistor 232 may receive an input or provide an output to one or more transistors of additional amplification stages of amplifier 230 a. It should be understood that the transistor 232 may have different amplifier configurations, such as common-gate or common-drain. In addition, the transistor 232 may be a different type of transistor, such as a BJT, HEMT, IGBT, HBT, or the like, and similarly may have a configuration, such as a common-base, a common-emitter, or a common-collector, adapted to the corresponding transistor type.
The invention also proposes a linearizer implemented with selectable impedance. For example, one or more transistors of the linearizer may receive a selectable control terminal bias voltage (e.g., a gate bias voltage for a FET or a base bias voltage for a BJT), which enables selection of the impedance of the linearizer. For example, controlling the terminal bias voltage may set the channel impedance of the transistor, which helps linearize the impedance of the linearizer. In fig. 2A, DC bias voltage 214 sets the nonlinear channel impedance of transistor 212. Thus, some desired non-linear channel impedance for the AC signal coupled between the input 202 and the DC power source 206 through the transistor 212 may be achieved by setting the DC bias voltage 214 accordingly. For example, the DC bias voltage 214 may set a particular non-linear channel impedance for a received AC signal operating between a first AC voltage level and a second AC voltage level. In some embodiments, the DC bias voltage 214 may be a selectable bias voltage for producing a desired non-linear channel impedance of the transistor 212.
Implementing the linearizer with a selectable impedance may reduce the overall size of the linearizer, thereby reducing manufacturing costs and increasing the operating efficiency of the linearizer. In a linearizer without an optional impedance, the impedance of the linearizer may be set by the channel size of the devices within the linearizer. For example, the linearizer may include a diode-connected transistor, the impedance of which is set by the channel size (e.g., channel width) of the transistor. In order to compensate for the non-linear response of the amplifier, the transistors of such linearizers need to have channel widths that are about the same size as the transistors of the amplifier to match the current density of the amplifier. However, the channel width of the transistors in the amplifier may be large, and thus when implemented in an integrated circuit, an increase in manufacturing costs will result when implementing a linearizer that compensates for the amplifier. In addition, a large transistor channel width will result in a large transistor internal capacitance, requiring more power to turn on the transistor. Thus, the linearizer may have a higher cost and require more power to operate.
A linearizer implemented with a selectable impedance, such as that described herein with reference to fig. 2A, may be configured to provide a desired impedance with a smaller channel width than a linearizer without the selectable impedance. The impedance of the linearizer can be set based not only on the channel width of the transistor of the linearizer, but also according to the optional control terminal bias voltage of the transistor. For example, the control terminal bias voltage may be set relative to the control terminal bias voltage of one or more transistors of the amplifier to adjust for non-linearities in the amplifier. The channel width of the transistors of the linearizer may be reduced when the control terminal bias voltage can compensate for the effect of the channel width reduction on the impedance of the linearizer. Thus, the linearizer can be implemented with a smaller channel width than a linearizer without an optional impedance, while maintaining the ability to match the current density in the amplifier, thereby reducing manufacturing costs and improving operating efficiency. In some embodiments, the channel width of the transistors of the linearizer may be between 5% and 10% of the channel width of the transistors of the amplifier.
The present invention proposes a linearizer implemented as a transistor (e.g., common gate for a FET or common base for a BJT) including a common-control terminal (common-control terminal) configuration. For example, in fig. 2A, the transistor 212 is a common-gate FET having a source coupled to the input 202 and a drain coupled to the DC power source 206A. The gate of transistor 212 is coupled to a DC bias voltage that is different from the DC supply voltage and different from the voltage at input 202.
The present invention proposes a linearizer implemented as a transistor with a cascode (cascode) common control terminal configuration. For example, the first and second FETs may be arranged in a common-gate configuration between the input of the amplifier and the DC power supply. Fig. 2B is a circuit diagram illustrating a system 200B that includes a single-ended amplifier 230B compensated by a cascode linearizer 210B coupled between input 202 and DC power supply 206. As shown in fig. 2B, linearizer 210B includes transistors 212a and 212B having a cascode topology. It should be understood that system 200b may be configured to operate in the manner described in connection with system 200 a. For example, amplifier 230b may be configured to operate as described for amplifier 230 a.
The present invention proposes a linearizer configured for use with a differential system. Fig. 2C is a circuit diagram illustrating a system 200C that includes a differential amplifier 230C coupled between the input terminals 202a and 202b and the output terminals 204a and 204b compensated by a linearizer 210C. In contrast to systems 200a and 200b, the signals received at inputs 202a and 202b of system 200c may be differential signals, where a high value component of the differential signal is received at input 202a and a low value component of the differential signal is received at input 202 b. As shown in fig. 2C, linearizer 210C may be configured to provide a non-linear impedance to the differential signal received at input terminals 202a and 202 b.
The amplifier 230c may be configured to operate in the manner of the amplifiers 230a and 230B described in connection with fig. 2A-2B. However, in contrast to fig. 2A and 2B, amplifier 230c is configured to amplify the differential signals received at input terminals 202A and 202B. For example, amplifier 230c includes transistors 232a and 232b, where transistor 232a is configured to amplify the high value component of the differential signal received at input 202a and transistor 232b is configured to amplify the low value component of the differential signal received at input 202 b. As shown in fig. 2C, the control terminals of the transistors 232a and 232b are coupled to the input terminals 202a and 202b, and the channels of the transistors 232a and 232b are coupled to the output terminals 204a and 204 b. The gain factors of the transistors 232A and 232b may be set by a DC bias at the control terminal and across the channels of the transistors 232A and 232b, as described for the transistor 232 in conjunction with fig. 2A. The transistors 232a and 232b are also configured to provide respective amplified components of the differential signal at the output terminals 204a and 204b, respectively. The DC bias conditions of the transistors 232a and 232b may be substantially the same such that the transistors 232a and 232b have substantially the same gain factor to avoid adding distortion to the components of the signals provided at the output terminals 204a and 204 b.
The linearizer proposed by the present invention can be implemented with the same topology as the amplifier it will compensate for. Figures 3A-3B illustrate an exemplary system including an amplifier and a linearizer, where the amplifier and linearizer have the same topology, according to some embodiments.
Fig. 3A is a circuit diagram illustrating a system 300a, the system 300a including a cascode differential amplifier 330a compensated with a cascode linearizer 310a coupled between input terminals 302a and 302b and output terminals 304a and 304 b. Linearizer 310a and amplifier 330a both have a cascode configuration and therefore have the same topology. In the illustrated embodiment, linearizer 310a and amplifier 330a each have a cascode topology. It should be understood that system 300a may be configured to operate in the manner described in connection with fig. 2C. For example, system 300a may be configured to receive a differential signal at inputs 302a and 302 b.
Fig. 3B is a circuit diagram illustrating a single-ended system 300B, the single-ended system 300B including a cascode single-ended amplifier 330B compensated by a cascode linear amplifier 310B coupled between the input 302 and the output 304. Linearizer 310b and amplifier 330b both have a cascode configuration and therefore have the same topology. System 300B may be configured to operate as described in conjunction with fig. 2B.
The present invention proposes a linearizer coupled to the input and output of an amplifier to be compensated. Fig. 4A-4B are circuit diagrams illustrating an exemplary system including an amplifier and an output-coupled linearizer according to some embodiments.
Fig. 4A is a circuit diagram illustrating a system 400a, the system 400a including a single-ended amplifier 430a coupled between an input 402 and an output 404 compensated by an output-coupled linearizer 410 a. System 400a may be configured to operate in the manner described for system 200a in conjunction with fig. 2A. For example, linearizer 410a may be configured to provide a non-linear impedance in parallel with amplifier 430a to the signal received at input 402. Additionally, a signal received at input 402 may be coupled to output 404 through linearizer 410 a.
Since the signals conducted through linearizer 410a may not be frequency shifted, these signals may be superimposed at the output of amplifier 430 a. Thus, system 400a may hold (preserve) substantially all of the signal received at input 402 and provide an amplifier signal at output 404. It should be understood that in some embodiments linearizer 410a may be configured to match the phase shift of amplifier 430a such that the signal received at input 402 passes through linearizer 410a to output 404 is in phase with the signal passing through amplifier 430a to output 404. In some embodiments, linearizer 410a may be configured to provide a phase offset of 180 degrees such that a signal received at input 402 passes through linearizer 410a to output 404 is inverted (out of phase) with the signal passing through amplifier 430a to output 404. According to various embodiments, linearizer 410a may be configured to provide any desired phase offset to the signal received at input 402. In addition, it should be understood that although linearizer 410a and amplifier 430a are shown as having the same non-cascode topology, linearizer 410a and amplifier 430a may have different topologies according to various embodiments.
Fig. 4B is a circuit diagram illustrating an example system 400B that includes a cascode differential amplifier 430B compensated by an output-coupled cascode linear amplifier 410B, according to some embodiments. System 400b may be configured to operate as described in conjunction with fig. 4A. For example, linearizer 410b, coupled between input terminals 402a and 402b and output terminals 404a and 404b, may be configured to provide a non-linear impedance in parallel with amplifier 430 b. However, in contrast to fig. 4A, system 400b is configured to receive a differential signal at inputs 402a and 402b, and linearizer 410b and amplifier 430b have a cascode topology. It should be understood that linearizer 410b and amplifier 430b may be configured to operate as described for linearizer 310a and amplifier 330a in conjunction with fig. 3A.
Fig. 5A is a circuit diagram illustrating an exemplary system 500a, system 500a including a single-ended amplifier 530a compensated with a PMOS linearizer 510a according to some embodiments. System 500a may be configured to operate in the manner described in conjunction with fig. 2A. For example, linearizer 510a may be configured to provide a non-linear impedance in parallel with amplifier 530 a. However, in contrast to linearizer 210a of fig. 2A, linearizer 510a includes a PMOS transistor 512 having a control terminal biased by a DC bias voltage 514. In some embodiments, the DC bias voltage 514 may be a negative supply voltage from the DC supply 506. It should be understood that linearizer 510a may be configured to operate as described for linearizer 210a in conjunction with figure 2A. In this example, the voltage at the control terminal of PMOS transistor 512 should be at least a threshold voltage less than the voltage at its source coupled to input 202, and should be at least a threshold voltage higher than the voltage of DC power source 506 to which its drain is coupled.
Fig. 5B is a circuit diagram illustrating an exemplary system 500B that includes a single-ended amplifier 530B compensated by a PMOS and NMOS linearizer 510B, according to some embodiments. System 500b may be configured to operate in the manner described in conjunction with fig. 2A. For example, linearizer 510b may be configured to provide a non-linear impedance in parallel with amplifier 530 b. However, in contrast to linearizer 210a of fig. 2A, linearizer 510b includes an NMOS transistor 512A and a PMOS transistor 512 b. NMOS transistor 512A is biased by DC bias voltage 514a, and DC bias voltage 514a may be configured in the manner described for DC bias voltage 214 in conjunction with fig. 2A. PMOS transistor 512b is biased by DC bias voltage 514b, which DC bias voltage 514b may be configured in the manner described for DC bias voltage 514 in conjunction with fig. 5A.
Various aspects of the devices and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.
It should be appreciated that the above-described transistors may be implemented in any of a variety of ways. For example, the one or more transistors may be implemented as bipolar junction transistors or field-effect transistors (FETs), such as metal-oxide semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), heterostructure field-effect transistors (HFETs), Heterojunction Bipolar Transistors (HBTs), and High Electron Mobility Transistors (HEMTs). Where one or more of the transistors described herein are implemented as BJTs, the gate, source and drain terminals described above for such transistors may be base, emitter and collector terminals, respectively.
Additionally, it should be understood that the amplifiers described herein may include multiple cascaded stages of common-source, common-control-terminal, and/or cascode-configured transistors. In some embodiments, amplifier 130 may comprise a class C power amplifier. In some embodiments, the amplifiers described herein may include power amplifiers belonging to any of classes a, B, AB, C, D, E, F, G, and H. In some embodiments, amplifier 130 may comprise a low noise amplifier.
Additionally, it should be understood that the illustrated embodiment omitting current mirror 240 may also be adapted to include current mirror 240.
Use of ordinal terms such as "first," "second," "third," etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which steps of a method are performed, but are used merely as labels to distinguish one claim element having a same name from another element having a same name.
Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," "containing," or "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
The use of "coupled" or "connected" means that circuit elements or signals may be connected directly to one another or through intervening components.
The terms "about," "substantially," and "about" may represent within ± 20% of the target value in some embodiments, within ± 10% of the target value in some embodiments, within ± 5% of the target value in some embodiments, and within ± 2% of the target value in some embodiments. The terms "substantially", "about" and "approximately" may include the target value.
Claims (17)
1. An amplifier linearizing apparatus comprising:
an amplifier; and
a linearizer comprising a first transistor comprising:
a first terminal coupled to an input of the amplifier;
a second terminal configured to be coupled to a direct current power source; and
a control terminal configured to control a current flowing between the first terminal and the second terminal, and configured to receive a direct current bias voltage different from a voltage of the first terminal.
2. The apparatus of claim 1, wherein the dc bias voltage is selected from a plurality of dc bias voltages.
3. The apparatus of claim 1, wherein the amplifier comprises a first transistor having a common channel terminal configuration.
4. The apparatus of claim 3, wherein the amplifier further comprises a second transistor having a common control terminal configuration.
5. The apparatus of claim 4, wherein the first transistor of the amplifier and the second transistor of the amplifier are Field Effect Transistors (FETs) having common source and common gate configurations, respectively.
6. The apparatus of claim 1, wherein the linearizer further comprises a second transistor, the first transistor coupled to the input of the amplifier through the second transistor, the second transistor comprising:
a first terminal coupled to an input of the amplifier;
a second terminal coupled to the first terminal of the first transistor; and
a control terminal configured to control a current flowing between the first terminal of the second transistor and the second terminal of the second transistor, and configured to receive another direct current bias voltage different from a voltage of the first terminal of the second transistor.
7. The apparatus of claim 1, wherein the second terminal of the first transistor is coupled to an output of the amplifier.
8. The apparatus of claim 1, wherein the voltage at the control terminal is:
greater than a voltage at the first terminal by at least a threshold voltage of the first transistor and less than a voltage at the second terminal by at least the threshold voltage; or
Is at least the threshold voltage less than the voltage at the first terminal and is at least the threshold voltage greater than the voltage at the second terminal.
9. An amplifier linearizing apparatus comprising:
an amplifier, comprising:
an input end;
an output end; and
a first set of transistors coupled between the input and the output, the first set of transistors comprising one or more transistors; and
a linearizer comprising:
a second set of transistors coupled between a DC power source and the input of the amplifier, the second set of transistors comprising one or more transistors; and
wherein the first set of transistors and the second set of transistors have the same topology.
10. The apparatus of claim 9, wherein the first set of transistors and the second set of transistors each comprise a cascode topology or each comprise a non-cascode topology.
11. The apparatus of claim 10, wherein the first and second sets of transistors each comprise a cascode topology, and wherein respective first and second transistors of the first set of transistors comprise a common control terminal configuration and a common channel terminal configuration.
12. The apparatus of claim 11, wherein channels of a first transistor and a second transistor of the second set of transistors are coupled to each other between the input of the amplifier and the dc power source.
13. The apparatus of claim 12, wherein the first and second transistors of the first set of transistors are Field Effect Transistors (FETs) comprising a common gate configuration and a common source configuration, respectively.
14. The apparatus of claim 10, wherein the first and second sets of transistors each comprise a non-cascode topology, and wherein a first transistor of the first set of transistors comprises a common-channel terminal configuration.
15. The apparatus of claim 14, wherein a channel terminal of a first transistor of the second set of transistors is coupled to the dc power supply and to an input of the amplifier.
16. The apparatus of claim 15, wherein the first transistor of the first set of transistors is a Field Effect Transistor (FET) comprising a common source configuration.
17. The apparatus of claim 9, wherein the second set of transistors is coupled between the input and the output of the amplifier.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/273,261 | 2019-02-12 | ||
| US16/273,261 US11070176B2 (en) | 2018-02-13 | 2019-02-12 | Amplifier linearization and related apparatus thereof |
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| Publication Number | Publication Date |
|---|---|
| CN111555725A true CN111555725A (en) | 2020-08-18 |
| CN111555725B CN111555725B (en) | 2023-07-18 |
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| CN201911308366.4A Active CN111555725B (en) | 2019-02-12 | 2019-12-18 | Amplifier linearization device |
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| CN (1) | CN111555725B (en) |
| TW (1) | TWI745794B (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW202030973A (en) | 2020-08-16 |
| CN111555725B (en) | 2023-07-18 |
| TWI745794B (en) | 2021-11-11 |
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