KR101891619B1 - Linearizing Bias Circuit for GaN MMIC Amplifier - Google Patents

Abstract

In order to improve the linearity of the amplifier, the present invention improves the linearity of the amplifier through a bias circuit that applies a different gate voltage to each amplifier unit, thereby outputting a high quality signal at a high output power. A bias circuit is built in the integrated circuit To a signal amplifier through a gallium nitride integrated circuit, which can be effectively applied to a small amplifier module since no additional external power supply circuit is required.

Description

Technical Field [0001] The present invention relates to a linearization bias circuit for a GaN integrated circuit amplifier,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gallium nitride integrated circuit amplifier, and more particularly to a signal amplifier having a high linear characteristic through a built-in bias circuit of a gallium nitride integrated circuit.

Generally, a signal amplifier increases the power of an input electrical signal and outputs it. The ideal amplifier needs to increase the signal size only linearly without distorting the input signal, but the output signal is distorted due to the nonlinear characteristics of the amplifier. Distortion in the amplifier is caused by a change in gain and phase as the input signal increases.

Predistortion, feed-forward, backoff, and feedback techniques are generally used to improve the linearity of the amplifier. The dual predistortion type linearizer is a widely used technology because it can not only reduce the efficiency of the amplifier but also can be implemented at a small size and low cost and can improve linear characteristics. Gallium nitride amplifiers have high gain characteristics and high efficiency characteristics, but the gain reduction is very large as the output signal increases. As a result, the linearity is not superior to other types of amplifiers.

Korean Patent Registration No. 10-0930200 (2009.11.27)

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a signal amplifying device which applies a bias circuit technique for improving gain distortion (AM-AM) to a gallium nitride integrated circuit, .

In order to achieve the above object, an amplifier for amplifying an input signal according to an embodiment of the present invention includes a first FET (Field Effect Transistor) in a first amplifier (e.g., a first stage amplifier) Amplifying the amplified output using a second FET in a second amplifier (e.g., an output stage amplifier), wherein a common voltage is applied to the first FET and the second FET, and the operating point current of the first FET and the second FET And a linearization bias circuit for generating different bias voltages applied to the gate terminals of the first FET and the second FET to improve linear amplification characteristics.

The linear amplification characteristic can be improved by operating the first FET at a lower operating point voltage between the gate and source terminals than the second FET by the different bias voltages generated by the linearization bias circuit.

And a matching circuit for impedance matching between the terminal of the input signal and the first amplifier, between the first amplifier and the second amplifier, or between the second amplifier and the output terminal.

The first FET and the second FET are transistors made of Group 3 and Group 5 semiconductor compounds. For example, the first FET and the second FET may be gallium nitride transistors.

The linearization bias circuit includes a first resistor, a second resistor, a third FET, and a third resistor for serially being connected in series between a first power source (e.g., ground) and a second power source A gate terminal of the third FET is connected to an end of the third resistor, and a voltage at both ends of the second resistor is applied to gate terminals of the first FET and the second FET, respectively.

The third FET is a transistor made of a Group 3 and Group 5 semiconductor compound. For example, the third FET may be a gallium nitride transistor.

The third FET is operated in the saturation region by the third resistor to generate a voltage across the second resistor.

As described above, according to the signal amplifier through the gallium nitride integrated circuit of the present invention, in order to improve the linearity of the amplifier, the linearity of the amplifier is improved through the bias circuit which applies the gate voltage for each amplifier unit differently, Signal can be output. The bias circuit can be embedded in the integrated circuit, so that an additional external power supply circuit is not required, so that it can be effectively applied to the small-sized amplifier module.

FIG. 1 is a diagram for explaining a two-stage amplifier including a linearization bias circuit according to an embodiment of the present invention.
2 is an example of a bias graph in a FET in general.
3 is an example of a graph of a gain distortion (AM-AM) characteristic of the first stage amplifier of FIG.
4 is an example of a graph of a gain distortion (AM-AM) characteristic in the two-stage amplifier of Fig.
5 is an example of a graph of the IMD3 characteristic in the two-stage amplifier of Fig.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same components are denoted by the same reference symbols as possible. In addition, detailed descriptions of known functions and / or configurations are omitted. The following description will focus on the parts necessary for understanding the operation according to various embodiments, and a description of elements that may obscure the gist of the description will be omitted. Also, some of the elements of the drawings may be exaggerated, omitted, or schematically illustrated. The size of each component does not entirely reflect the actual size, and therefore the contents described herein are not limited by the relative sizes or spacings of the components drawn in the respective drawings.

1 is a diagram illustrating a two-stage amplifier 100 including a linearization bias circuit 200 according to an embodiment of the present invention.

Referring to FIG. 1, an amplifier 100 according to an embodiment of the present invention includes an input terminal 301 for inputting an RF (Radio Frequency) signal, and an output terminal 302 for outputting an amplified signal. An input stage matching circuit 321, a first stage amplifier 331, an intermediate stage matching circuit 322, an output stage amplifier 332, an output stage matching circuit 323 and a linearization bias circuit 200. The amplifier 100 may be configured as a monolithic microwave integrated circuit (MMIC). That is, the amplifier 100 includes a FET (Field Effect Transistor) having a gate terminal G, a source terminal S, and a drain terminal D made of gallium nitride in addition to a resistor, an inductor, a capacitor, ) May be implemented as one integrated circuit.

The first-stage amplifier 331 and the output stage amplifier 332 amplify and output the power of the input signal, that is, the voltage or the current, respectively. Stage amplification structure in which the output of the first-stage amplifier 331 is amplified again by the output stage amplifier 332. The three matching circuits, that is, the input stage matching circuit 321, the intermediate stage matching circuit 322, and the output stage matching circuit 323 perform the function of impedance matching between the respective corresponding ends to transmit signals. In some cases, one or more of the three matching circuits may be omitted.

The first-stage amplifier 331 and the output stage amplifier 332 include a gallium nitride transistor such as the above FET (including other passive elements / active elements), and the output power of the gallium nitride transistor Can be determined.

A predetermined DC voltage (VDD) is commonly applied to the drain terminal (D) of each gallium nitride transistor included in the first-stage amplifier 331 and the output stage amplifier 332.

The gate terminals G of the respective gallium nitride transistors included in the first stage amplifier 331 and the output stage amplifier 332 are connected to different voltages (VG1, VG2) are applied.

Although detailed circuits for the first-stage amplifier 331 and the output stage amplifier 332 are not shown, the drain terminal D and the gate terminal G of each of these gallium nitride transistors are biased and the source terminal S may be amplified and output through the drain terminal D or other additional circuitry. The first-stage amplifier 331 and the output stage amplifier 332 are well known to those skilled in the art, so a detailed description thereof will be omitted.

Generally, the gain reduction when operating from a large operating point current in an amplifier is large and the gain reduction when operating with a small operating point current is relatively small. According to the present invention, the linearization bias circuit 200 is used to improve the linearity of the amplifier by varying the operating point current of the amplifier stage (331/332) according to the characteristics of the amplifier.

The linearization bias circuit 200 includes three resistors R1, R2, R3 coupled between a first power supply (e.g., ground) and a second power supply VS (e.g., a negative power supply) and a gallium nitride transistor Q1 . That is, the second power supply VS (e.g., negative power supply) is a power supply having a lower voltage than the first power supply (e. G., Ground) And the gate terminal G of Q1 is connected to the second power supply VS (e.g., a negative power supply) between R1, R2, and Q1 (a drain terminal and a source terminal are connected between R2 and R3) Or at the R3 end (the end of the series connection). The entire linearization bias circuit 200 as such can be easily integrated into an integrated circuit because it has a simple configuration of one transistor and three resistors.

A feedback resistor R3 is connected between the gate terminal G and the source terminal S of the gallium nitride transistor Q1 so that the gallium nitride transistor Q1 operates in a saturation region where the first power supply The drain current ID of Q1 flows in the direction of the second power supply VS (e.g., negative power). As a result, the voltage VG1 (R1 and R2) input to the gate terminal (G) 342 of the gallium nitride transistor of the output stage amplifier 332 and the voltage The voltage VG2 (the voltage of the drain contact of R2 and Q1) input to the gate terminal (G) 343 of the gallium nitride transistor of the first stage amplifier 331 can be generated.

[Equation 1]

VG1 and VG2 may vary depending on the sizes of the three resistors (R1, R2, R3) and the gallium nitride transistor (Q1). For example, VG1 = -2.6V, VG2 = -2.8V, The gate voltage of the first stage amplifier 331 is lower than that of the gate terminal of the output stage amplifier 332 due to the lower operating point voltage between the gate and the source terminal depending on the bias between the gate terminal G and the source terminal S So that the linearity of the amplifier can be improved.

2 is an example of a bias graph in a FET in general.

For example, in general, when the gate voltage VG of the FET is determined to be as high as -2.6 V in FIG. 2, the gain of the amplifier is high, but the gain reduction characteristic becomes large as the output signal becomes large. Conversely, when the gate voltage VG is determined to be a low value as shown in -2.8 V in FIG. 2, the gain of the amplifier is somewhat low, but the gain reduction characteristic is small as the output signal becomes large. Thus, -2.6 V is supplied to the gate terminal voltage VG1 of the gallium nitride transistor of the output stage amplifier 332 of FIG. 1 to perform the same operation as a general amplifier operation, and the gate terminal voltage VG2 of the gallium nitride transistor of the first stage amplifier 331 When the operating point drain current is lowered by supplying -2.8 V, other gain reduction characteristics are reduced in the output signal, thereby improving the linearity in the region where the output power of the two-stage amplifier 100 is low.

3 is an example of a graph of a gain distortion (AM-AM) characteristic of the first stage amplifier 331 of FIG.

The gain distortion characteristics of the first-stage amplifier 331 according to the final output power when the gate terminal voltage VG2 of the gallium nitride transistor of the first-stage amplifier 331 is -2.6 V and -2.8 V is schematized. When using VG2 at -2.6V, the gain decreases by more than 2dB as the output power increases, while when -2.8V is used, it decreases to less than 0.5dB.

4 is an example of a graph of a gain distortion (AM-AM) characteristic in the two-stage amplifier 100 of FIG.

The gate terminal voltage VG1 of the gallium nitride transistor of the output stage amplifier 332 is supplied at -2.6 V and the final output of the case where the gate terminal voltage VG2 of the gallium nitride transistor of the first stage amplifier 331 is -2.6 V and -2.8 V The amplitude gain distortion (AM-AM) characteristic of the two-stage amplifier 100 is plotted. In the case of using VG2 at -2.6 V, the gain of the first-stage amplifier 331 and the output stage amplifier 332 decreases as the output power increases, and the final gain decreases by 7 dB. When VG2 is used as -2.8 V, The gain distortion value of the amplifier 331 is small and is reduced to within 4.3 dB. Accordingly, it can be seen that the linearity of the two-stage amplifier 100 due to the AM-AM characteristic improvement can be improved.

5 is an example of an IMD3 characteristic graph in the two-stage amplifier 100 of FIG.

The gate terminal voltage VG1 of the gallium nitride transistor of the output stage amplifier 332 is supplied at -2.6 V and the final output of the case where the gate terminal voltage VG2 of the gallium nitride transistor of the first stage amplifier 331 is -2.6 V and -2.8 V The IMD3 characteristic of the two-stage amplifier 100 is plotted. In a typical communication system, IMD3 (3 ^rd order intermodulation distortion) is required to be -25 dB. However, when using VG2 at -2.6 V, the output power satisfying IMD3 -25 dB is 31.4 dBm while VG2 is used at -2.8 V The output power satisfying IMD3 -25 dB is 37 dBm, which is improved by 5.6 dB.

As described above, the present invention has been described with reference to particular embodiments, such as specific elements, and specific embodiments and drawings. However, it should be understood that the present invention is not limited to the above- Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the essential characteristics of the invention. For example, although a gallium nitride transistor is described above as an example, the present invention is not limited thereto. Instead of the above-described gallium nitride transistor, a transistor made of a Group 3 or Group 5 semiconductor compound such as GaAs or GaP may be used. Also, the present invention is not limited to the MMIC, but it may be implemented using other integrated circuits or individual devices. Therefore, the spirit of the present invention should not be construed as being limited to the embodiments described, and all technical ideas which are equivalent to or equivalent to the claims of the present invention are included in the scope of the present invention .

Claims (10)

An amplifier for amplifying an input signal,
A first amplifier;
A second amplifier for amplifying an output of the first amplifier; And
The bias voltage applied to the gate terminals of the first FET and the second FET is differently generated so as to vary the operating point currents of the first FET included in the first amplifier and the second FET included in the second amplifier Linearization bias circuit
Lt; / RTI >
Wherein the linearization bias circuit comprises:
A third FET; And
A feedback resistor connected between the gate terminal and the source terminal of the third FET;
≪ / RTI > The method according to claim 1,
Wherein the linearization bias circuit comprises:
A resistance connected to the drain terminal of the third FET
Further comprising:
The gate terminal of the first FET is connected between the drain terminal and one end of a resistor connected to the drain terminal, and the gate terminal of the second FET is connected to the other end of a resistor connected to the drain terminal. 3. The method of claim 2,
And the third FET is implemented as a gallium nitride transistor. The method according to claim 1,
Wherein at least one of the first FET and the second FET is implemented as a gallium nitride transistor. The method according to claim 1,
A matching circuit for matching at least one of an input signal input to the first amplifier, an input signal input to the second amplifier, and an output signal of the second amplifier,
≪ / RTI > A method of amplifying an amplifier comprising a first amplifier, a second amplifier, and a linearization bias circuit,
Wherein the linearization bias circuit changes the operating point currents of the first FET included in the first amplifier and the second FET included in the second amplifier by a bias applied to gate terminals of the first FET and the second FET, Generating a voltage differently;
Amplifying an input signal in response to a bias voltage applied to a gate terminal of the first FET by the first amplifier; And
Amplifying an output signal of the first amplifier in response to a bias voltage applied to a gate terminal of the second FET by the second amplifier
Lt; / RTI >
Wherein the linearization bias circuit comprises:
A third FET; And
A feedback resistor connected between the gate terminal and the source terminal of the third FET;
≪ / RTI > The method according to claim 6,
The linearization bias circuit
A resistance connected to the drain terminal of the third FET
Further comprising:
A gate terminal of the first FET is connected between the drain terminal and one end of a resistor connected to the drain terminal, and a gate terminal of the second FET is connected to the other terminal of the resistor connected to the drain terminal.
≪ / RTI > 8. The method of claim 7,
Wherein the third FET is implemented as a gallium nitride transistor. The method according to claim 6,
Wherein at least one of the first FET and the second FET comprises a gallium nitride
≪ / RTI > The method according to claim 6,
Matching at least one of an input signal input to the first amplifier, an input signal input to the second amplifier, and an output signal of the second amplifier;
≪ / RTI >

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