CN111510120B - Non-power-consumption analog switch with voltage processing function - Google Patents
Non-power-consumption analog switch with voltage processing function Download PDFInfo
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- CN111510120B CN111510120B CN202010536929.1A CN202010536929A CN111510120B CN 111510120 B CN111510120 B CN 111510120B CN 202010536929 A CN202010536929 A CN 202010536929A CN 111510120 B CN111510120 B CN 111510120B
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- 238000001514 detection method Methods 0.000 claims description 17
- 239000003990 capacitor Substances 0.000 claims description 14
- 230000003068 static effect Effects 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 25
- 238000010586 diagram Methods 0.000 description 10
- 230000005236 sound signal Effects 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
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- Electronic Switches (AREA)
Abstract
The invention discloses a reactive power analog switch with a voltage processing function, which comprises the following components: the invention provides a power consumption-free analog switch with a voltage processing function, which is characterized in that the input and output of the switch are completely symmetrical, the switch can be conducted in two directions, the switch tube has the characteristic of transmitting positive and negative voltage signals, the switch tube can be turned off rapidly after the power supply is powered off, the transmission of positive and negative voltage signals at the input end is blocked, the isolation degree of the switch tube is greatly improved in the power supply voltage power-off state, and the analog switch has no static power consumption.
Description
Technical Field
The invention relates to the technical field of analog switches, in particular to the field of non-power-consumption analog switches with voltage processing capability.
Background
The analog switch mainly completes the signal switching function in the signal link, and the signal link is turned off or turned on by adopting a MOS tube switch mode, and the analog switch is similar to a switch in function and is realized by the characteristics of an analog device, so that the analog switch is called an analog switch, and can be divided into an audio analog switch, a video analog switch, a digital switch, a general analog switch and the like for different application requirements.
At present, for an analog switch used for transmitting an audio signal, the isolation degree of the switch in a power-down state is an important index, the audio analog switch usually adopts a pair of associated pmos transistors and nmos transistors, the switch can only meet the requirements of transmitting positive voltage and negative voltage, if the switch is not processed, the switch transistor cannot be ensured to be in a power-off state after the power supply voltage is powered down, in the prior art, a pull-up resistor is connected to the grid electrode of a first switch transistor, and a pull-down resistor is connected to the grid electrode of a second switch transistor.
However, the switching tube can not be turned off rapidly after the power supply is powered down in the mode, and meanwhile, larger static power consumption can be introduced in the mode, so that the requirement of ultra-low power consumption in application occasions can not be met.
Therefore, a reactive power analog switch with voltage processing capability is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the invention provides a non-power-consumption analog switch with a voltage processing function, which solves the problem that a switching tube can be rapidly turned off and isolate positive and negative voltages after a power supply is powered down, and has the positive and negative voltage processing function.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
A non-reactive analog switch with voltage processing function, comprising:
A first switching tube;
The first driving circuit is connected with the grid electrode of the first switching tube;
The drain electrode of the pull-up tube is connected with the first driving circuit and the grid electrode of the first switching tube;
The drain electrode of the second switching tube is connected with the source electrode of the first switching tube, and the source electrode of the second switching tube is connected with the drain electrode of the first switching tube;
the second driving circuit is connected with the grid electrode of the second switching tube;
The drain electrode of the pull-down tube is connected with the second driving circuit and the grid electrode of the second switching tube;
the first level shifting circuit is respectively connected with the grid electrode of the pull-up tube and the grid electrode of the pull-down tube;
The second level shift circuit is connected with the first driving circuit and the first level shift circuit;
A third level shift circuit connected to the second drive circuit, the first level shift circuit, and the second level shift circuit;
the logic control circuit is respectively connected with the second level shift circuit and the third level shift circuit;
And the power supply voltage detection circuit is respectively connected with the first level shift circuit, the second level shift circuit and the third level shift circuit.
Preferably, the source of the pull-up tube is a high voltage output end, and the high voltage output end is connected with the first driving circuit, the second driving circuit, the first level shift circuit, the second level shift circuit and the third level shift circuit.
Preferably, the source of the pull-down tube is a low voltage output end, and the low voltage output end is connected with the first driving circuit, the second driving circuit, the first level shift circuit, the second level shift circuit and the third level shift circuit.
Preferably, the power supply voltage detection circuit comprises a first pmos tube, a second pmos tube, a first nmos tube, a second nmos tube, a first resistor, a second resistor and a first capacitor, wherein the drain of the first pmos tube is connected with one end of the first resistor, the grid and the source of the first pmos tube are connected with the source of the second pmos tube and one end of the first capacitor, the grid of the second pmos tube is connected with the grid of the first nmos tube and one end of the second resistor, the drain of the second pmos tube is connected with the drain of the first nmos tube and the grid of the second nmos tube, the source of the first nmos tube is grounded, the source of the second nmos tube is grounded, the other ends of the first resistor and the second resistor are respectively connected with the power supply voltage, and the other ends of the first capacitor are connected with the first level shift circuit, the second level shift circuit, the third level shift circuit, the first pull-down drive circuit and the second pull-down drive circuit.
The power supply voltage detection circuit has the beneficial effects that: the detection circuit has a voltage state, and the detection circuit reflects an initial state when an audio signal is input and a state when the power supply voltage is 0, so that the condition of uncertain level caused by insufficient voltage level or noise interference and other factors of other core circuits is avoided.
Preferably, the first level shift circuit, the second level shift circuit and the third level shift circuit are the same level shift circuit, and the level shift circuit comprises a seventh pmos transistor, an eighth pmos transistor, a ninth pmos transistor, a tenth pmos transistor, a seventh nmos transistor, an eighth nmos transistor, a ninth nmos transistor, a tenth nmos transistor, a fourth resistor and an inverter;
the source of the seventh pmos transistor, the source of the eighth pmos transistor, the source of the ninth pmos transistor and the source of the tenth pmos transistor are connected, the gate of the seventh pmos transistor is connected with the drain of the eighth pmos transistor, the drain of the eighth nmos transistor is connected with the gate of the ninth pmos transistor, the drain of the seventh nmos transistor, the gate of the eighth pmos transistor is connected with the gate of the tenth pmos transistor, the drain of the ninth nmos transistor is connected with the gate of the tenth nmos transistor, the drain of the tenth pmos transistor, the drain of the tenth nmos transistor is connected with the gate of the ninth nmos transistor, the gate of the seventh nmos transistor is connected with one end of the fourth resistor, the input end of the inverter is connected with the gate of the eighth nmos transistor, the output end of the eighth nmos transistor is connected with the source of the eighth nmos transistor, and the source of the output end of the eighth nmos transistor is connected with the source of the eighth nmos transistor.
The level shift circuit has the beneficial effects that: the conversion between higher and lower voltages in the overall circuit is achieved.
Compared with the prior art, the reactive power analog switch with the voltage processing function has the following effects:
The input and output of the analog switch circuit are completely symmetrical, the switch tube can be conducted in two directions, the switch tube has the characteristic of transmitting positive and negative voltage signals, the switch tube can be turned off rapidly after the power supply is turned off, the switch tube blocks the transmission of positive and negative voltage signals at the input end, the isolation of the switch in the power supply voltage power-off state is greatly improved, and the analog switch has no static power consumption.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an analog switch provided by the present invention;
FIG. 2 is a diagram of a power supply voltage detection circuit provided by the invention;
FIG. 3 is a diagram of a first level shift circuit according to the present invention;
FIG. 4 is a diagram of a high voltage selection circuit provided by the present invention;
FIG. 5 is a diagram of a low voltage selection circuit provided by the present invention;
FIG. 6 is a schematic diagram of a pmos substrate selection circuit provided by the present invention;
FIG. 7 is a diagram of an nmos substrate select circuit provided by the present invention;
FIG. 8 is a schematic diagram of a voltage port of the circuit provided by the invention when the circuit is powered on and powered off;
FIG. 9 is a schematic diagram of the audio signal input according to the present invention;
FIG. 10 is a schematic diagram of the circuit according to the present invention when the power voltage is 0;
In fig. 1: 11-first switching tube, 12-second switching tube, 13-pull-up tube, 14-pull-down tube 109-pmos substrate selection circuit, 110-nmos substrate selection circuit, 111-logic control circuit, 114-first driving circuit, 115-second driving circuit, 102-first level shift circuit, 112-second level shift circuit, 113-third level shift circuit, 101-power supply voltage detection circuit, 107-high voltage selection circuit, 108-low voltage selection circuit, 103-first voltage port, 104-second voltage port, 105-high voltage selection output port, 106-low voltage selection output port.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the embodiment of the invention discloses a power consumption-free analog switch with a voltage processing function, which comprises:
A first switching tube 11;
the first driving circuit 114, the driving circuit 114 is connected with the grid electrode of the first switching tube 11;
The drain electrode of the pull-up tube 13 is connected with the first driving circuit 114 and the grid electrode of the first switching tube 11;
the drain electrode of the second switching tube 12 is connected with the source electrode of the first switching tube 11, and the source electrode of the second switching tube 12 is connected with the drain electrode of the first switching tube 11;
the second driving circuit 115, the second driving circuit 115 is connected with the grid electrode of the second switching tube 12;
The drain of the pull-down tube 14 is connected with the second driving circuit 115 and the grid electrode of the second switching tube 12;
The first level shift circuit 102, the first level shift circuit 102 is connected with the grid electrode of the pull-up tube 13 and the grid electrode of the pull-down tube 14 respectively;
A second level shift circuit 112, the second level shift circuit 112 being connected to the first driving circuit 114 and the first level shift circuit 102;
A third level shift circuit 113, the third level shift circuit 113 being connected to the second drive circuit 115, the first level shift circuit 102, and the second level shift circuit 112;
A logic control circuit 111, the logic control circuit 111 being connected to the second level shift circuit 112 and the third level shift circuit 113, respectively;
The power supply voltage detection circuit 101, and the power supply voltage detection circuit 101 is connected to the first level shift circuit 102, the second level shift circuit 112, and the third level shift circuit 113, respectively.
In a specific embodiment, the source of the pull-up tube 13 is a high voltage output terminal, and the high voltage output terminal is connected to the first driving circuit 114, the second driving circuit 115, the first level shift circuit 102, the second level shift circuit 112, and the third level shift circuit 113.
In one embodiment, the source of the pull-down tube 14 is a low voltage output terminal, and the low voltage output terminal is connected to the first driving circuit 114, the second driving circuit 115, the first level shift circuit 102, the second level shift circuit 112, and the third level shift circuit 113.
Specifically, in one embodiment, referring to fig. 2, the power supply voltage detection circuit 101 includes a first pmos transistor 21, a second pmos transistor 22, a first nmos transistor 23, a second nmos transistor 24, a first resistor 25, a second resistor 26, and a first capacitor 27, where a drain of the first pmos transistor 21 is connected to one end of the first resistor 25, a gate and a source of the first pmos transistor 21 are connected to one end of a source capacitor 27 of the second pmos transistor 22, a gate of the second pmos transistor 22 is connected to one end of a gate of the first nmos transistor 23 and one end of the second resistor 26, a drain of the second pmos transistor 22 is connected to a drain of the first nmos transistor 23 and a gate of the second nmos transistor 24, a source of the first nmos transistor 23 is grounded, another ends of the first resistor 25 and the second resistor 26 are respectively connected to a power supply voltage, and another ends of the capacitor 27 are connected to a first level shift circuit, a second level shift circuit, a third level shift circuit, a first level shift circuit, a second level shift circuit, a low-voltage drive circuit, and a low-voltage drive circuit 106.
In a specific embodiment, the first level shift circuit 102 is the same level shift circuit as the second level shift circuit 112 and the third level shift circuit 113, and referring to fig. 3, the level shift circuit includes a seventh pmos transistor 31, an eighth pmos transistor 32, a ninth pmos transistor 33, a tenth pmos transistor 34, a seventh nmos transistor 35, an eighth nmos transistor 36, a ninth nmos transistor 37, a tenth nmos transistor 38, a fourth resistor 39, and an inverter 310;
Specifically, the source of the seventh pmos transistor 31, the source of the eighth pmos transistor 32, the source of the ninth pmos transistor 33, and the source of the tenth pmos transistor 34 are connected, the gate of the seventh pmos transistor 31 is connected to the drain of the eighth pmos transistor 32, the drain of the eighth nmos transistor 36 is connected to the gate of the ninth pmos transistor 33, the drain of the seventh pmos transistor 31, the gate of the eighth pmos transistor 32 is connected to the gate of the tenth pmos transistor 34, the drain of the ninth pmos transistor 33, the drain of the ninth nmos transistor 37 is connected to the gate of the tenth pmos transistor 38, the drain of the tenth pmos transistor 34, the drain of the tenth nmos transistor 38 is connected to the gate of the ninth nmos transistor 37, the gate of the seventh nmos transistor 35 is connected to one end of the fourth resistor 39, the input of the inverter 310, the gate of the eighth nmos transistor 36 is connected to the output of the inverter 310, the drain of the seventh nmos transistor 36 is connected to the source of the eighth nmos transistor 37, and the source of the eighth nmos transistor 37 is connected to the other source of the eighth resistor 38.
In a specific embodiment, referring to fig. 4, the high voltage selection circuit 107 further includes a high voltage selection circuit 107, where the high voltage selection circuit 107 includes a first voltage port 103, a second voltage port 104, and a high voltage selection output port 105, the first voltage port 103 is connected to a source of the first switch tube 11 and a drain of the second switch tube 12, the second voltage port 104 is connected to the drain of the first switch tube 11 and a gate of the second switch tube 12, and the high voltage selection output port 105 is connected to sources of the first level shift circuit 102, the second level shift circuit 112, the third level shift circuit 113, the first drive circuit 114, the second drive circuit 115, and the pull-up tube 13;
Specifically, the high voltage selection circuit 107 includes a third pmos transistor 41, a fourth pmos transistor 42, a fifth pmos transistor 43, a sixth pmos transistor 44, a third resistor 45, a first voltage port 103, a second voltage port 104, and a high voltage selection output port 105; the drain electrode of the third pmos transistor 41 is connected to the first voltage port 103 and the gate electrode of the fourth pmos transistor 42, the gate electrode of the third pmos transistor 41 is connected to the drain electrode of the fourth pmos transistor 42 and the second voltage port 104, the source electrode of the third pmos transistor 41 is connected to the source electrode of the fourth pmos transistor 42, the drain electrode of the fifth pmos transistor 43 and the gate electrode of the sixth pmos transistor 44, the gate electrode of the fifth pmos transistor 43 is connected to the drain electrode of the sixth pmos transistor 44 and one end of the third resistor 45, the source electrode of the fifth pmos transistor 43 is connected to the source electrode of the sixth pmos transistor 44, the substrate of the sixth pmos transistor 44 and the high voltage selective output port 105, and the other end of the third resistor 45 is connected to the power supply voltage.
Specifically, the voltage selected by the high voltage selection circuit 107 is the power supply voltage, the highest voltage between the first switching tube and the second switching tube.
In a specific embodiment, referring to fig. 5, the low voltage selection circuit 108 further includes a low voltage selection circuit 108, where the low voltage selection circuit 108 includes a first output port 103, a second output port 104, and a low voltage selection output port 106, the first voltage port 103 is connected to the high voltage selection circuit 107, a source of the first switch tube 11, and a drain of the second switch tube 12, the second voltage port 104 is connected to the high voltage selection circuit 107, the drain of the first switch tube 11, and a gate of the second switch tube 12, and the low voltage selection output port 106 is connected to the first level shift circuit 102, the second level shift circuit 112, the third level shift circuit 113, the first driving circuit 114, the second driving circuit 115, and a source of the pull-up tube 13;
specifically, the low voltage selection circuit 108 includes a third nmos tube 51, a fourth nmos tube 52, a fifth nmos tube 53, a sixth nmos tube 54, a first voltage port 103, a second voltage port 104, and a low voltage selection output port 106; the drain electrode of the third nmos tube 51 is connected to the first voltage port 103 and the gate electrode of the fourth nmos tube 52, the gate electrode of the third nmos tube 51 is connected to the drain electrode of the fourth nmos tube 52 and the second voltage port 104, the source electrode of the third nmos tube 50 is connected to the source electrode of the fourth nmos tube 52, the drain electrode of the fifth nmos tube 53 and the gate electrode of the sixth nmos tube 54, the gate electrode of the fifth nmos tube 53 is grounded to the drain electrode of the sixth nmos tube 54, and the source electrode of the fifth nmos tube 53 is connected to the source electrode of the sixth nmos tube 54 and the low-voltage selective output port 106.
Specifically, the voltage selected by the low-voltage selection circuit is the ground voltage, and the lowest voltage between the first switching tube and the second switching tube.
In a specific embodiment, referring to fig. 6, the pmos substrate selection circuit 109 is further included, where the pmos substrate selection circuit 109 is connected to the drain, gate and first voltage port 103 of the first switch tube 11, and the drain, gate and second voltage port 104 of the second switch tube;
Specifically, the pmos substrate selection circuit 109 includes: an eleventh pmos transistor 61, a twelfth pmos transistor 62, a first voltage port 103, a second voltage port 104; the gate of the eleventh pmos transistor 61 is connected to the second input port and the drain of the twelfth pmos transistor, and the source of the eleventh pmos transistor is connected to the source of the twelfth pmos transistor.
In a specific embodiment, referring to fig. 7, the circuit further includes an nmos substrate selection circuit 110, where the nmos substrate selection circuit 110 is connected to the drain, gate and first voltage port 103 of the first switch tube 11, and the drain, gate and second voltage port 104 of the second switch tube;
specifically, the nmos substrate selection circuit 110 includes: thirteenth nmos tube 71, fourteenth nmos tube 72, first voltage port 103, second voltage port 104; the gate of the thirteenth nmos transistor 71 is connected to the first voltage port 103 and the drain of the fourteenth nmos transistor 72, and the source of the thirteenth nmos transistor 71 is connected to the source of the fourteenth nmos transistor 72.
The specific working principle of the invention is as follows:
When the first switching tube 11 and the second switching tube 12 transmit positive voltages, the voltage at the first voltage port 103 is greater than the voltage at the second voltage port 104, so that the twelfth pmos tube 62 in the pmos transistor substrate selection circuit 109 is closed, the eleventh pmos tube 61 is opened, the first voltage port 103 with high voltage is selected as the substrate voltage of the first switching tube 11, the voltage at the output port 601 in the pmos transistor substrate selection circuit 109 is equal to the voltage at the first voltage port 103, the thirteenth nmos tube 71 in the nmos transistor substrate selection circuit 110 is closed, the fourteenth nmos tube 72 is opened, the second voltage port 104 with low voltage is selected as the substrate of the second switching tube 12, and the voltage at the output port 701 in the nmos transistor substrate selection circuit 110 is equal to the voltage at the second voltage port 104;
When the first switch tube 11 and the second switch tube 12 transmit positive and negative voltages, the voltage at the first voltage port 103 is smaller than the voltage at the second voltage port 104, so that the eleventh pmos tube 61 in the pmos substrate selection circuit 109 is closed, the twelfth pmos tube 62 is opened, the second voltage port 104 with high voltage is selected as the substrate voltage of the first switch tube 11, the voltage at the output port 601 in the pmos substrate selection circuit 109 is equal to the voltage at the second voltage port 104, the fourteenth nmos tube 72 in the nmos substrate selection circuit 110 is closed, the thirteenth nmos tube 71 is opened, the first voltage port 103 with low voltage is selected as the substrate of the second switch tube 12, and the voltage at the output port 701 in the nmos substrate selection circuit 110 is equal to the voltage at the first voltage port 103.
The high voltage selection circuit 107 is configured as a two-stage cascade of pmos substrate selection circuits 109 that ultimately select the highest voltage of the supply voltage, the voltage across the first voltage port 103, and the voltage across the second voltage port 104.
The high voltage selection circuit 108 is configured as a two-stage cascade of pmos substrate selection circuits 110 that ultimately select the lowest voltage of GND, the voltage at the first voltage port 103, and the voltage at the second voltage port 104.
When the power supply voltage is powered on, the logic control circuit 111 controls the first switching tube and the second switching tube to be turned on and off; when the power supply voltage is powered down, the power supply voltage is reduced to 0, the first voltage port 103 is used as an input end and is provided with an audio signal, the second voltage port 104 is used as an output end, the input/output ends 103/104 and the voltages of the output ports 105 and 106 are as shown in fig. 3, the maximum input voltage of the audio signal is VMAX, the minimum input voltage is VMIN, the maximum output voltage of the high-voltage selection output port 105 is VMAX, the minimum output voltage is 0, the maximum output voltage of the high-voltage selection output port 106 is 0V, and the minimum output voltage is VMIN.
One end of the first capacitor 27 in the power supply voltage detection circuit is connected to the low voltage selection output port 106, when an audio signal is input, the voltage at two ends of the first capacitor 27 is 0 in an initial state, when the voltage at the low voltage selection output port 106 is reduced to be lower than the threshold voltage VTHP of the first pmos transistor 21 and the second pmos transistor 22, the voltage at the point a can only be reduced to VTHP due to the parasitic diodes of the first pmos transistor 21 and the second pmos transistor 22, after one period of audio signal, the voltage difference at two ends of the capacitor 27 is raised to VMAX- |vthp|, when the voltage at the low voltage selection output port 106 is 0, the voltage at the upper plate a end of the first capacitor 27 is VMAX- |vthp|, as shown in fig. 9, when the voltage at the upper plate a point of the capacitor 27 is VMAX- |vthp, the gate voltage of the second nmos transistor 24 is VMAX- |vthp, and when the voltage at the upper plate a point of the capacitor 27 is VMAX- |vthp, the gate voltage of the second nmos transistor 24 is greater than the voltage VTHP, the gate voltage at the second nmos transistor 24 is pulled to be turned on, and the gate voltage at the second gate voltage of the second nmos transistor is turned on 201.
When the power supply voltage is 0, the voltages at the output port 105 and the output port 106 in the first level shift circuit 102 are as shown in fig. 8, the voltage at the output port 201 in the first level shift circuit 102 is strongly pulled to 0 due to the action of the second nmos tube 24 in the power supply voltage detection circuit, the voltages at the output port 304 and the output port 305 are as shown in fig. 10 according to the working principle of the level shift circuit, wherein the output port 305 in the level shift circuit 201 is connected with the gate of the pull-up tube 13, the output port 304 is connected with the gate of the pull-down tube 14, and the voltage at the gate of the first switch tube 11 is always consistent with the voltage at the end 105 due to the action of the pull-up tube 13 and the pull-down tube 14, and the voltage at the gate of the switch tube 12 is always consistent with the voltage at the end 106. Since the voltage of the gate of the switching tube 11 is always kept not lower than the input voltage of the 103 terminal, the voltage of the gate of the second switching tube 12 is always kept not higher than the input voltage of the 103 terminal, and the first switching tube 11 and the second switching tube 12 are always kept in the off state.
The output terminal 201 of the power supply voltage detection circuit 101 is connected to the input terminals of the second level shift circuit 112 and the third level shift circuit 113, and when the power supply voltage is turned off, the second level shift circuit 112 outputs a voltage not lower than the voltage of the first voltage port 103, and the third level shift circuit 113 outputs a voltage not higher than the voltage of the first voltage port 103.
When the whole circuit works normally, the second nmos tube 24 in the power supply voltage detection circuit 101 is in an off state, the end 201 in the first level shift circuit 102 has no pull-down effect, the end 304 voltage is output to be in a low level, namely the lowest voltage in the first voltage port 103, the second voltage port 104 and GND, the end 305 is output to be in an off state, namely the highest voltage in the first voltage port 103, the second voltage port 104 and the power supply voltage, the pull-up tube 13 is in an off state, the states of the first switch tube 11 and the second switch tube 12 are controlled by the logic control circuit 111, and the whole circuit has no static power consumption in working.
It can be concluded that the non-power consumption analog switch with the voltage processing function provided by the invention has the advantages that the switching tube can be rapidly turned off after the power supply is powered off, the transmission of positive and negative voltage signals at the input end is blocked, the isolation degree of the switching tube in the power supply voltage power-off state is greatly improved, and the analog switch has no static power consumption.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A power-free analog switch with voltage processing function, comprising:
A first switching tube (11);
A first drive circuit (114), wherein the first drive circuit (114) is connected with the grid electrode of the first switch tube (11);
The drain electrode of the pull-up tube (13) is connected with the first driving circuit (114) and the grid electrode of the first switching tube (11);
The drain electrode of the second switching tube (12) is connected with the source electrode of the first switching tube (11), and the source electrode of the second switching tube (12) is connected with the drain electrode of the first switching tube (11);
A second drive circuit (115), the second drive circuit (115) being connected to the gate of the second switching tube (12);
A pull-down tube (14), wherein the drain of the pull-down tube (14) is connected with the second driving circuit (115) and the grid electrode of the second switching tube (12);
a first level shift circuit (102), wherein the first level shift circuit (102) is connected with the grid electrode of the pull-up tube (13) and the grid electrode of the pull-down tube (14) respectively;
a second level shift circuit (112), the second level shift circuit (112) being connected to the first drive circuit (114) and the first level shift circuit (102);
A third level shift circuit (113), wherein the third level shift circuit (113) is connected to the second drive circuit (115), and the first level shift circuit (102) and the second level shift circuit (112);
a logic control circuit (111), wherein the logic control circuit (111) is connected to the second level shift circuit (112) and the third level shift circuit (113), respectively;
and a power supply voltage detection circuit (101), wherein the power supply voltage detection circuit (101) is connected to the first level shift circuit (102), the second level shift circuit (112), and the third level shift circuit (113), respectively.
2. The reactive power analog switch with voltage processing function according to claim 1, wherein a source of the pull-up tube (13) is a high voltage output terminal, and the high voltage output terminal is connected to the first driving circuit (114), the second driving circuit (115), the first level shift circuit (102), the second level shift circuit (112) and the third level shift circuit (113).
3. The reactive power analog switch with voltage processing function according to claim 1, wherein a source of the pull-down tube (14) is a low voltage output terminal, and the low voltage output terminal is connected to the first driving circuit (114), the second driving circuit (115), the first level shift circuit (102), the second level shift circuit (112) and the third level shift circuit (113).
4. The reactive power analog switch with a voltage processing function according to claim 1, wherein the power supply voltage detection circuit (101) comprises a first pmos transistor, a second pmos transistor, a first nmos transistor, a second nmos transistor, a first resistor, a second resistor and a first capacitor, wherein a drain of the first pmos transistor is connected to one end of the first resistor, a gate and a source of the first pmos transistor are connected to a source of the second pmos transistor and one end of the first capacitor, a gate of the second pmos transistor is connected to a gate of the first nmos transistor and one end of the second resistor, a drain of the second pmos transistor is connected to a drain of the first nmos transistor, a source of the second nmos transistor is grounded, the first resistor and the other end of the second pmos transistor are connected to a voltage level shift circuit (114), a first level shift circuit (114), a second level shift circuit (114), and a second level shift circuit (114).
5. The reactive power analog switch with voltage processing function according to claim 1, wherein the first level shift circuit (102) and the second level shift circuit (112) and the third level shift circuit (113) are the same level shift circuit, and the level shift circuit comprises a seventh pmos transistor, an eighth pmos transistor, a ninth pmos transistor, a tenth pmos transistor, a seventh nmos transistor, an eighth nmos transistor, a ninth nmos transistor, a tenth nmos transistor, a fourth resistor, and an inverter;
the source of the seventh pmos transistor, the source of the eighth pmos transistor, the source of the ninth pmos transistor and the source of the tenth pmos transistor are connected, the gate of the seventh pmos transistor is connected with the drain of the eighth pmos transistor, the drain of the eighth nmos transistor is connected with the gate of the ninth pmos transistor, the drain of the seventh nmos transistor, the gate of the eighth pmos transistor is connected with the gate of the tenth pmos transistor, the drain of the ninth nmos transistor is connected with the gate of the tenth nmos transistor, the drain of the tenth pmos transistor, the drain of the tenth nmos transistor is connected with the gate of the ninth nmos transistor, the gate of the seventh nmos transistor is connected with one end of the fourth resistor, the input end of the inverter is connected with the gate of the eighth nmos transistor, the output end of the eighth nmos transistor is connected with the source of the eighth nmos transistor, and the source of the output end of the eighth nmos transistor is connected with the source of the eighth nmos transistor.
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