CN111508967A - 半导体存储装置及其制造方法 - Google Patents

半导体存储装置及其制造方法 Download PDF

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Publication number
CN111508967A
CN111508967A CN201911069774.9A CN201911069774A CN111508967A CN 111508967 A CN111508967 A CN 111508967A CN 201911069774 A CN201911069774 A CN 201911069774A CN 111508967 A CN111508967 A CN 111508967A
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conductive contact
insulating layer
contact pattern
conductive
pattern
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CN111508967B (zh
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李建泳
金兑京
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SK Hynix Inc
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SK Hynix Inc
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Abstract

半导体存储装置及其制造方法。提供了一种半导体存储装置及其制造方法。该半导体存储装置包括：第一基板，该第一基板包括外围电路、连接到所述外围电路的第一导电接触图案以及具有使所述第一导电接触图案暴露的凹槽的第一上绝缘层；第二基板，该第二基板包括存储单元阵列、设置在所述存储单元阵列上的第二上绝缘层以及第二导电接触图案，所述第二上绝缘层形成在所述存储单元阵列和所述第一上绝缘层之间，所述第二导电接触图案穿过所述第二上绝缘层突出到所述凹槽的开口中；以及导电粘合剂图案，该导电粘合剂图案填充所述凹槽，以将所述第二导电接触图案连接到所述第一导电接触图案。

Description

半导体存储装置及其制造方法
技术领域
本公开总体上涉及半导体存储装置及其制造方法，并且更具体地，涉及三维半导体存储装置及其制造方法。
背景技术
半导体存储装置可以包括具有多个存储单元的存储单元阵列。存储单元阵列可以包括以各种结构布置的存储单元。为了提高存储单元的集成度，已提出了三维半导体存储装置。
三维半导体存储装置包括三维布置的存储单元。当制造三维半导体存储装置时，需要能够提高制造处理的稳定性的技术。
发明内容
按照本公开的一方面，提供了一种半导体存储装置，该半导体存储装置包括：第一基板，该第一基板包括外围电路、连接到所述外围电路的第一导电接触图案以及具有使所述第一导电接触图案暴露的凹槽的第一上绝缘层；第二基板，该第二基板包括存储单元阵列、设置在所述存储单元阵列上的第二上绝缘层以及第二导电接触图案，所述第二上绝缘层形成在所述存储单元阵列和所述第一上绝缘层之间，所述第二导电接触图案穿过所述第二上绝缘层突出到所述凹槽的开口中；以及导电粘合剂图案，所述导电粘合剂图案填充所述凹槽，以将所述第二导电接触图案连接到所述第一导电接触图案。
按照本公开的一方面，提供了一种制造半导体存储装置的方法，该方法包括以下步骤：在第一基板上形成第一结构，其中，所述第一结构包括外围电路、连接到所述外围电路的第一导电接触图案以及具有使所述第一导电接触图案暴露的凹槽的第一上绝缘层；在第二基板上形成第二结构，其中，所述第二结构包括存储单元阵列、设置在所述存储单元阵列上的第二上绝缘层以及第二导电接触图案，所述第二上绝缘层形成在所述存储单元阵列和所述第一上绝缘层之间，所述第二导电接触图案穿过所述第二上绝缘层突出到所述凹槽的开口中；用导电粘合剂材料填充每个所述凹槽；以及将所述第二结构设置在所述第一结构上，使得所述第二上绝缘层形成在所述第一上绝缘层上，并且所述第二导电接触图案的突出部在所述凹槽中对准，使得所述导电粘合剂材料与所述第一导电接触图案和所述第二导电接触图案接触。
附图说明
下文中参照附图更充分地描述示例实施方式；然而，这些实施方式可按不同形式实施，而不应该被理解为限于本文中阐述的实施方式。相反，提供这些实施方式，使得本公开将是可行的并且将把示例实施方式的范围传达给本领域的技术人员。
在附图中，为了图示清晰起见，可夸大尺寸。相似的参考标号始终是指相似的元件。
图1A和图1B是例示了按照本公开的实施方式的制造半导体存储装置的方法的截面图。
图2A、图2B和图2C是例示了本公开的修改的截面图。
图3A、图3B和图3C是例示了在图1A中示出的第一上绝缘层的凹槽中形成导电粘合剂材料的处理的实施方式的截面图。
图4是例示了在图1A中示出的第一上绝缘层的凹槽中形成导电粘合剂材料的处理的实施方式的流程图。
图5是例示了按照本公开的实施方式的半导体存储装置的截面图。
图6A、图6B、图6C、图7A、图7B、图7C和图8是例示了制造图5中示出的半导体存储装置的方法的实施方式的截面图。
图9是例示了按照本公开的实施方式的半导体存储装置的截面图。
图10是例示了按照本公开的实施方式的存储系统的配置的框图。
图11是例示了按照本公开的实施方式的计算系统的配置的框图。
具体实施方式
为了描述根据本公开的构思的实施方式的目的，本文中公开的特定结构或功能描述仅仅是例示性的。根据本公开的构思的实施方式可以按各种形式实现，并且不能被解释为限于本文中阐述的实施方式。
根据本公开的构思的实施方式可以以各种方式修改并且具有各种形状。因此，在附图中例示了实施方式，并且这些实施方式旨在在本文中进行详细描述。然而，根据本公开的构思的实施方式将不被解释为限于指定的公开，而是包括不脱离本公开的精神和技术范围的所有改变、等同物或替代物。
虽然可以使用诸如“第一”和“第二”这样的术语来描述各种组件，但是这些组件不必被理解为限于以上术语。以上术语只是用于将一个组件与另一个区分开。例如，在不脱离本公开的权利范围的情况下，第一组件可以被称为第二组件，同样地，第二组件可以被称为第一组件。
应该理解，当一个元件被称为“连接”或“联接”于另一个元件时，它可以直接连接或联接于另一个元件，或者还可以存在中间元件。相比之下，当一个元件被称为“直接连接”或“直接联接”于另一个元件时，不存在中间元件。
应该理解，当一个元件被称为“在”两个元件“之间”时，它可以是这两个元件之间的唯一元件，或者还可以存在一个或更多个中间元件。
本申请中使用的术语仅用于描述具体实施方式，而不旨在限制本公开。除非上下文中另外清楚指示，否则本公开中的单数形式旨在也包括复数形式。还应该理解，诸如“包括”或“具有”等这样的术语旨在指示存在说明书中公开的特征、数字、操作、动作、组件、部件或其组合，而不旨在排除可存在或可添加一个或更多个其它特征、数字、操作、动作、组件、部件或其组合的可能性。
实施方式提供了能够提高其制造处理的稳定性的半导体存储装置和制造该半导体存储装置的方法。
图1A和图1B是例示了按照本公开的实施方式的制造半导体存储装置的方法的截面图。
参照图1A，制造半导体存储装置的方法可以包括在第一基板101上形成第一结构A的处理、在第二基板121上形成第二结构B的处理、在由第一结构A限定的每个凹槽109中形成导电粘合剂材料111A的处理以及在第一结构A上设置第二结构B的处理。
在基板101上形成第一结构A的处理可以包括在第一基板101上形成第一下结构103的处理、在第一下结构103上形成第一导电接触图案105的处理以及形成包括与第一导电接触图案105交叠的凹槽109的第一上绝缘层107的处理，第一上绝缘层107覆盖第一下结构103。
第一基板101可以是单晶半导体层。例如，第一基板101可以是体硅基板、绝缘体上硅基板、锗基板、绝缘体上锗基板、硅锗基板或者通过选择性外延生长处理形成的外延薄膜。
第一下结构103可以包括存储单元阵列或者包括构成外围电路的晶体管。将参照图5描述构成外围电路的存储单元阵列的示例和晶体管的示例。
第一导电接触图案105可以电连接到第一下结构103。在实施方式中，当第一下结构103包括存储单元阵列时，第一导电接触图案105可以连接到存储单元阵列。在另一实施方式中，当第一下结构103包括构成外围电路的晶体管时，第一导电接触图案105可以连接到晶体管。第一导电接触图案105可以由各种导电材料形成。例如，
第一导电接触图案105可以由铜、铝等形成。
第一上绝缘层107可以由氧化物层形成。形成在第一上绝缘层107中的凹槽109使第一导电接触图案105的上表面暴露。在后续处理中，每个第一导电接触图案105的上表面可以被设置为面对第二导电接触图案127。每个凹槽109的横截面形状可以包括诸如圆形形状、椭圆形形状、矩形形状、正方形形状等这样的各种形状。
在第二基板121上形成第二结构B的处理可以包括在第二基板121上形成第二下结构123的处理以及在第二下结构123上形成第二上绝缘层125的处理。第二上绝缘层125覆盖第二下结构123，并且第二导电接触图案127穿透第二上绝缘层125。
第二基板121可以是单晶半导体层。例如，第二基板121可以是体硅基板、绝缘体上硅基板、锗基板、绝缘体上锗基板、硅锗基板或通过选择性外延生长处理形成的外延薄膜。
第二下结构123可以包括存储单元阵列或者包括构成外围电路的晶体管。在实施方式中，当第一下结构103包括存储单元阵列时，第二下结构123可以包括构成外围电路的晶体管。在另一实施方式中，当第一下结构103包括构成外围电路的晶体管时，第二下结构123可以包括存储单元阵列。
第二导电接触图案127可以电连接到第二下结构123。在实施方式中，当第二下结构123包括存储单元阵列时，第二导电接触图案127可以连接到存储单元阵列。在另一实施方式中，当第二下结构123包括构成外围电路的晶体管时，第二导电接触图案127可以连接到晶体管。第二导电接触图案127可以包括从第二上绝缘层125突出的突出部127P。第二导电接触图案127可以由各种导电材料形成。例如，第二导电接触图案127可以由钨、铝等形成。每个第二导电接触图案127的表面可以被金属屏蔽层(未示出)覆盖。例如，金属屏蔽层可以包括钛氮化物层。
第二上绝缘层125可以包括氧化物层。
第一上绝缘层107的第一高度H1可以比第二导电接触图案127的从第二上绝缘层125突出的突出部127P的第二高度H2更远离第一导电接触图案105地突出(H1>H2)。在后续处理中，能防止第一导电接触图案105与第二导电接触图案127之间直接接触。结果，能减少在后续处理中施加到第二导电接触图案127的突出部127P的应力。
每个凹槽109的第一宽度W1被形成为具有比对应的第二导电接触图案127的第二宽度W2大的宽度(W1>W2)。因此，在后续处理中，第二导电接触图案127可以容易地在凹槽109中对准。
如上所述，独立地执行在第一基板101上形成第一结构A的处理以及在第二基板121上形成第二结构B的处理，使得可以保护第二结构B免受在形成第一结构A的同时产生的高温的影响或者可以保护第一结构A免受在形成第二结构B的同时产生的高温的影响。例如，可以防止外围电路的特性由于在形成存储单元阵列的同时产生的高温而劣化。
导电粘合剂材料111A在每个凹槽109中被涂覆在每个第一导电接触图案105的顶部上。导电粘合剂材料111A可以是可以通过诸如丙酮或醇这样的溶剂来控制其粘度的流体材料。例如，导电粘合剂材料111A可以包括环氧树脂或者包括具有银纳米颗粒、硼氮化物和环氧树脂的混合物。可以控制导电粘合剂材料111A的高度，使得导电粘合剂材料111A在后续处理中不溢流并从凹槽109流出。例如，导电粘合剂材料111A的高度被控制为低于第一高度H1。
当第二结构B设置在第一结构A上时，第二基板121设置在第一基板101上，使得第二上绝缘层125与第一上绝缘层107相对，并且第二导电接触图案127的突出部127P在相应的凹槽109中对准。
参照图1B，第一上绝缘层107和第二上绝缘层125彼此紧密粘附，使得第二导电接触图案127的突出部127P分别在凹槽109中对准。随后，将图1A中示出的导电粘合剂材料111A固化，使得形成导电粘合剂图案111B。导电粘合剂图案111B分别将第一导电接触图案105电连接到第二导电接触图案127。
导电粘合剂图案111B分别设置在凹槽109中。用于形成导电粘合剂图案111B的固化处理可以包括热处理。例如，可以通过在100℃至150℃的温度下执行两个小时或更长时间的热处理来形成导电粘合剂图案111B。按照本公开的实施方式的固化处理不限于此，并且可以根据导电粘合剂材料的组分来改变热处理的温度和热处理的保持时间。
如参照图1A描述的，当第一上绝缘层107的第一高度H1被形成为具有比第二导电接触图案127的每个突出部127P的第二高度H2大的高度(H1>H2)时，第二导电接触图案127可以不与第一导电接触图案105直接接触。因此，可以减小在第一上绝缘层107和第二上绝缘层125彼此紧密粘附的同时施加到第二导电接触图案127的应力。
按照本公开的实施方式，设置在凹槽109中的导电粘合剂材料111A具有如参照
图1A描述的流动性。因此，导电粘合剂材料111A可以在导电粘合剂材料111A填充第一导电接触图案105与第二导电接触图案127之间的空间的状态下被固化。因此，第一导电接触图案105可以经由导电粘合剂图案111B电连接到第二导电接触图案127。
如参照图1A描述的，当每个凹槽109的第一宽度W1被形成为具有比对应于其的第二导电接触图案127的第二宽度W2宽的宽度(W1＞W2)时，可以在将第二导电接触图案127在相应的凹槽109中对准的处理中增加覆盖余量。因此，不必加宽每个第二导电接触图案127的第二宽度W2，因为这只会增加对准余量，因此能够提高半导体存储装置的集成度。
图2A至图2C是例示了本公开的修改的截面图。
参照图2A，形成在凹槽109中的每个导电粘合剂图案111B1可以被形成为具有比每个凹槽109的高度低的高度。因此，当第一基板101与第二基板121彼此紧密地粘附时，可以在第二上绝缘层125与每个导电粘合剂图案111B1之间形成间隙G。导电粘合剂图案111B1被形成为填充第一导电接触图案105与第二导电接触图案127的突出部127P之间的空间。因此，尽管形成了间隙G，但是因为导电粘合剂图案111B1可以与第一导电接触图案105和第二导电接触图案127的突出部127P二者接触，所以第一导电接触图案105仍可以经由导电粘合剂图案111B1电连接到第二导电接触图案127。
参照图2B，第二导电接触图案127的突出部127P1可以被形成为具有与第一上绝缘层107从第一导电接触图案105突出的第一高度相等的高度。因此，当第一基板101与第二基板121彼此紧密地粘附时，第二导电接触图案127可以与第一导电接触图案105直接接触。可以用导电粘合剂图案111B填充由第一上绝缘层107限定的凹槽109。
参照图2C，支撑第二导电接触图案127的第二基板121可在处理期间弯曲。因此，第二导电接触图案127的从第二上绝缘层125朝向第一导电接触图案105突出的突出部127P1和127P2不能均匀地形成。例如，突出部127P1和127P2的面对第一导电接触图案105的上表面不能布置在同一条线上。
按照本公开的实施方式，由于导电粘合剂材料111A具有如前所述的流动性，因此即使在突出部127P1和127P2的上表面没有布置在同一条上时，第二导电接触图案127也可被导电粘合剂图案111B围绕。换句话说，无论不均匀的布置如何，导电粘合剂图案111B都可以与第一导电接触图案105和第二导电接触图案127的突出部127P1和127P2二者接触。因此，在本公开的实施方式中，尽管第二基板121可能弯曲，但是第一导电接触图案105和第二导电接触图案127可以通过导电粘合剂图案111B稳定地连接。
换句话说，当第二基板121在处理期间弯曲时，突出部127P1和127P2中的一些突出部127P1可以被形成为具有与第一上绝缘层107从第一导电接触图案105突出的第一高度相等的高度，并且突出部127P1和127P2中的其它突出部127P2可以被形成为具有比第一高度低的高度。另外，突出部127P1和127P2中的一些突出部127P1可以与第一导电接触图案105直接接触，并且突出部127P1和127P2中的其它突出部127P2可以经由导电粘合剂图案111B电连接到第一导电接触图案105。
如图2B和图2C中所示，导电粘合剂图案111B可以具有被控制为与第二上绝缘层125接触的高度。另一方面，导电粘合剂图案111B可以与第二上绝缘层125间隔开，以在它们之间插置有间隙G，如参照图2A描述的。
图3A至图3C是例示了在图1A中示出的第一上绝缘层107的凹槽109中形成导电粘合剂材料111A的处理的实施方式的截面图。
参照图3A，在第一基板101上形成第一下结构103和第一导电接触图案105之后，可以形成第一上绝缘层107。在通过穿透第一上绝缘层107形成凹槽109之前，可以在第一上绝缘层107上形成保护层161。保护层161可以由具有对在后续处理中形成的导电粘合剂材料111A的粘附力弱于对第一上绝缘层107的粘附力的材料形成。例如，保护层161可以包括光刻胶层或碳层。
随后，可以通过光刻处理和蚀刻处理来形成穿透保护层161和第一上绝缘层107的凹槽109。凹槽109可以使第一导电接触图案105暴露。保护层161可以在第一上绝缘层107的蚀刻处理期间用作蚀刻阻挡件。
随后，用导电粘合剂材料111A填充每个凹槽109。导电粘合剂材料111A与参照图1A描述的导电粘合剂材料111A相同。导电粘合剂材料111A没有留在具有相对弱的粘附力的保护层161周围，而是可以被填充在凹槽109中。导电粘合剂材料111A可以通过旋涂处理来形成，但是本公开不限于此。
参照图3B，去除图3A中示出的导电粘合剂材料111A的一部分，使得每个凹槽109的上部被暴露。因此，在每个凹槽109中以目标高度形成导电粘合剂材料111A。可以通过调整漂洗时间来控制导电粘合剂材料111A的去除高度。
参照图3C，在如参照图1A描述地在第一结构A上设置第二结构B之前，可以去除保护层161。因此，第一上绝缘层107的上表面被暴露。
图4是例示了在图1A中示出的第一上绝缘层107的凹槽109中形成导电粘合剂材料111A的处理的实施方式的流程图。
参照图4，在通过穿透第一上绝缘层来形成凹槽并且随后用导电粘合剂材料填充凹槽之前，可以在处理ST1中对第一上绝缘层的上表面进行表面处理。第一上绝缘层的表面处理工艺可以根据导电粘合剂材料的溶剂性质而改变。在实施方式中，当导电粘合剂材料具有亲水性时，可以对第一上绝缘层的表面进行疏水处理。在另一实施方式中，当导电粘合剂材料具有疏水性时，可以对第一上绝缘层的表面进行亲水处理。
随后，在处理ST3中，可以形成导电粘合剂材料，以填充第一上绝缘层内的凹槽。该导电粘合剂材料与参照图1A描述的导电粘合剂材料111A相同。如先前关于图3A解释的，导电粘合剂材料对表面处理后的第一上绝缘层的上表面的粘附力弱。这意指导电粘合剂材料不留在第一上绝缘层的上表面上，而是可以填充凹槽。
随后，在处理ST5中，去除导电粘合剂材料的一部分，使得每个凹槽的一部分被暴露。因此，在每个凹槽109中形成具有目标高度的导电粘合剂材料111A，如图1A中所示。
下文中，将描述参照图1A描述的第一下结构103和第二下结构123的各种实施方式。
图5是例示了按照本公开的实施方式的半导体存储装置的截面图。图5例示了本公开的实施方式中的半导体存储装置，其中，第一下结构200包括构成外围电路的晶体管，并且第二下结构300包括存储单元阵列。
参照图5，形成在第一基板201上的第一下结构200可以包括构成外围电路的晶体管TR、覆盖晶体管TR的第一多层绝缘层MI1以及穿透第一多层绝缘层MI1的连接结构221、223和225。
晶体管TR可以通过设置在第一基板201中的隔离层203彼此分开。每个晶体管TR可以包括形成在通过隔离层203分隔的有源区上的栅极绝缘层211、形成在栅极绝缘层211上的栅极213以及在栅极213的两侧形成在第一基板210中的杂质区域205。每个杂质区域205是包括n型或p型掺杂物的区域，并且可以被用作源极区域或漏极区域。晶体管TR可以连接到存储单元阵列CAR，并且控制存储单元阵列CAR的操作。
第一多层绝缘层MI1可以包括两个或更多个绝缘层215和227。在一些情况下，第一多层绝缘层MI1可以包括至少一个第一蚀刻阻挡层231。例如，第一多层绝缘层MI1可以包括形成在第一基板201上以覆盖晶体管TR的第一氧化物层215、形成在第一氧化物层215上的第二氧化物层227以及形成在第二氧化物层227上的第一蚀刻阻挡层231。第一多层绝缘层MI1的层叠结构不限于图5中示出的示例，并且可以按各种方式进行修改。例如，第一蚀刻阻挡层231可以由蚀刻速率与氧化物层的蚀刻速率不同的材料形成。换句话说，第一蚀刻阻挡层231可以包括氮化物层。
连接结构221、223和225可以包括穿透第一多层绝缘层MI1的接触插塞221和225以及导电焊盘223。例如，连接结构221、223和225可以包括第一接触插塞221、被形成为宽度比第一接触插塞221的宽度宽的第一导电焊盘223以及连接到第一导电焊盘223的第二接触插塞225。第一接触插塞221可以穿透第一氧化物层215，并且可以连接到晶体管TR的杂质区域205和栅极213。第一导电焊盘223可以连接到第二氧化物层227中的第一接触插塞221中的一些。第二接触插塞225可以穿透第二氧化物层227并且连接到第一导电焊盘223中的一些。连接结构221、223和225不限于图5中示出的示例，并且可以按各种方式进行修改。例如，连接结构221、223和225可以由各种导电材料形成。
第一导电接触图案233和235以及第一上绝缘层237被设置在第一基板201上，在第一导电接触图案233和235以及第一上绝缘层237与第一基板201之间插置有第一下结构200。
第一导电接触图案233和235可以电连接到连接结构221、223和225。例如，第一导电接触图案233和235可以穿透第一蚀刻阻挡层231并且连接到第二接触插塞225。
第一导电接触图案233和235中的每一个可以包括下导电图案233和上导电图案235中的至少一个。下导电图案233可以穿透第一蚀刻阻挡层231，以连接到对应的第二接触插塞225。下导电图案233可以被形成为具有比对应的第二接触插塞225的宽度宽的宽度。上导电图案235可以被设置在下导电图案233上。上导电图案235可以被形成为具有比下导电图案233的宽度窄的宽度。在一些情况下，可以省略上导电图案235。
第一导电接触图案233和235可以由与参照图1A描述的第一导电接触图案相同的材料形成。第一导电接触图案233和235可以经由连接结构221、223和225连接到晶体管TR。例如，第一导电接触图案233和235中的每一个可以经由至少一个连接结构连接到晶体管TR当中的与该第一导电接触图案对应的一个。在实施方式中，彼此对应的第一导电接触图案和晶体管可以经由至少一个接触插塞和至少一个导电焊盘彼此电连接。在图5中示出的示例中，可以使用第一接触插塞221中的一个、第一导电焊盘223中的一个和第二接触插塞225中的一个，使得彼此对应的成对的第一导电接触图案和晶体管彼此电连接。本公开的实施方式不限于此，并且可以按各种方式修改穿透第一多层绝缘层MI1的连接结构的布置和数目，使得彼此对应的成对的
第一导电接触图案和晶体管彼此电连接。
第一上绝缘层237可以包括与第一导电接触图案233和235交叠的凹槽239。凹槽239使第一导电接触图案233和235分别暴露。第一上绝缘层237可以由氧化物层形成。第一上绝缘层237可以形成在晶体管TR上方，在它们之间插置有第一多层绝缘层M1。
形成在第二基板301上的第二下结构300可以包括存储单元阵列CAR、第二多层绝缘层MI2、位线BL、连接结构345、347、363、355和357、多个支撑件321、源极接触结构SCT和狭缝绝缘层331。存储单元阵列CAR包括多个存储串STR。第二多层绝缘层MI2与存储单元阵列CAR交叠。此外，位线BL可以被埋置在第二多层绝缘层MI2中。
第二导电接触图案375和第二上绝缘层370可以被设置在第二基板301上，在第二导电接触图案375和第二上绝缘层370与第二基板301之间插置有第二下结构300。
存储单元阵列CAR可以包括连接在源极区303和位线BL之间的存储串STR。源极区303可以形成在第二基板301中，并且可以包含杂质。源极区303的杂质可以包括n型掺杂物。
存储串STR可以被设置在第二基板301和第二上绝缘层370之间。存储串STR的栅极可以连接到栅极层叠结构GST的导电图案313。
栅极层叠结构GST可以包括交替地层叠在第二基板301和第二多层绝缘层MI2之间的层间绝缘层311和导电图案313。沟道结构CH穿透栅极层叠结构GST。
沟道结构CH用作存储串STR的沟道区。沟道结构CH可以由半导体层形成。可以用芯绝缘层CO填充每个沟道结构CH的中部区域。每个沟道结构CH的一端可以连接到源极区303。每个沟道结构CH的另一端可以连接到与芯绝缘层CO交叠的掺杂图案DP。掺杂图案DP可以包含杂质。例如，掺杂图案DP可以包含n型掺杂剂。掺杂图案DP可以用作漏极区。
存储器层ML可以被设置在每个导电图案313和每个沟道结构CH之间，并且存储数据。存储器层ML可以包括从每个沟道结构CH的侧壁朝向栅极层叠结构GST的侧壁垂直层叠的隧道绝缘层、数据存储器层和阻挡绝缘层。隧道绝缘层可以包括电荷能够隧穿的硅氧化物层。数据存储器层可以由电荷捕获层形成，由包括导电纳米点的材料层形成或者由相变材料层形成。例如，数据存储器层可以由其中能够捕获电荷的硅氮化物层形成。阻挡绝缘层可以包含能够阻挡电荷的氧化物。
可以在导电图案313与沟道结构CH的交叉部分处限定构成每个存储串STR的源极选择晶体管、存储单元和漏极选择晶体管。源极选择晶体管的栅极连接到导电图案313当中的与源极区303相邻的源极侧导电图案，并且漏极选择晶体管的栅极连接到导电图案313当中的与各条位线BL相邻的位线侧导电图案。存储单元的栅极连接到导电图案313当中的中间导电图案。中间导电图案是设置在源极侧导电图案和位线侧导电图案之间的导电图案。
可以通过穿透栅极层叠结构GST的狭缝绝缘层331将栅极层叠结构GST分成多个存储块。源极接触结构SCT可以穿透栅极层叠结构GST并且将电信号传输到源极区303。源极接触结构SCT可以形成有单个导电层或者形成有两个或更多个导电层。源极接触结构SCT和栅极层叠结构GST可以通过设置在它们之间的侧壁绝缘层333来彼此绝缘。
栅极层叠结构GST的导电图案313可以包括以阶梯结构形成的接触区域。多个支撑件321可以穿透以阶梯结构形成的接触区域。
第二多层绝缘层MI2可以被设置在存储单元阵列CAR和第二上绝缘层370之间，并且包括两个或更多个绝缘层341、343和361。在一些情况下，第二多层绝缘层MI2可以包括至少一个第二蚀刻阻挡层351。例如，第二多层绝缘层MI2可以包括第三氧化物层341、第四氧化物层343、第二蚀刻阻挡层351和第五氧化物层361。第三氧化物层341可以被设置在第二基板301的一个表面上，以覆盖栅极层叠结构GST的阶梯结构。第四氧化物层343、第二蚀刻阻挡层351和第五氧化物层361可以被依次设置在第二上绝缘层370和第三氧化物层341之间。第二多层绝缘层MI2的层叠结构不限于图5中示出的示例，并且可以按各种方式进行修改。例如，第二蚀刻阻挡层351可以由蚀刻速率与氧化物层不同的材料形成。换句话说，第二蚀刻阻挡层351可以包括氮化物层。
源极接触结构SCT可以延伸以穿透第四氧化物层343。
位线BL可以被埋置在第二蚀刻阻挡层351和第五氧化物层361中。
连接结构345、347、363、355和357可以包括穿透第二多层绝缘层MI2的接触插塞345、347和363以及导电焊盘355和357。例如，连接结构345、347、363、355和357可以包括漏极接触插塞345、栅极接触插塞347、源极焊盘355、栅极焊盘357和上接触插塞363。源极焊盘355可以被形成为具有比源极接触结构SCT的宽度宽的宽度，并且栅极焊盘357可以被形成为具有比栅极接触插塞347的宽度宽的宽度。漏极接触插塞345可以穿透第四氧化物层343并且将沟道结构CH连接到位线BL。栅极接触插塞347可以与导电图案313接触并且延伸以穿透第三氧化物层341和第四氧化物层343。源极焊盘355可以与源极接触结构SCT接触，并且延伸以穿透第二蚀刻阻挡层351和第五氧化物层361的一部分。上接触插塞363可以与位线BL、源极焊盘355和栅极焊盘357接触，并且延伸以穿透第五氧化物层361。连接结构345、347、363、355和357不限于图5中示出的示例，并且可以按各种方式进行修改。例如，连接结构345、347、363、355和357可以由各种导电材料形成。
第二上绝缘层370被设置在第二多层绝缘层MI2和第一基板201之间，并且可以被形成在第一上绝缘层237上。第二上绝缘层370与第一上绝缘层327直接接触。第二上绝缘层370可以被形成为由氧化物层371和蚀刻阻挡层373构成的层叠结构。第二上绝缘层370的层叠结构不限于此，并且可按各种方式进行修改。例如，第二蚀刻阻挡层370可以被形成为氧化物层的单层结构。
第二导电接触图案375与上接触插塞363接触，并且延伸以穿透第二上绝缘层370。第二导电接触图案375具有向凹槽239的洞穴区域突出的突出部375P。第二导电接触图案375可以由与参照图1A描述的第二导电接触图案相同的材料形成。第二导电接触图案375可以经由连接结构345、347、363、355和357连接到存储单元阵列CAR。例如，导电图案313、位线BL和源极接触结构SCT中的每一个可以经由至少一个连接结构连接到对应的第二导电接触图案375。按照图5中示出的实施方式，彼此对应的成对的位线BL和第二导电接触图案375可以经由上接触插塞363中的一个电连接。此外，彼此对应的成对的导电图案313和第二导电接触图案375可以经由栅极接触插塞347中的一个、栅极焊盘357中的一个和上接触插塞363中的一个电连接。本公开的实施方式不限于此，并且可以按各种方式修改穿透第二多层绝缘层MI2的连接结构的布置和数目，以便将每个第二导电接触图案375连接到导电图案313、位线BL和源极接触结构SCT当中的与该第二导电接触图案375对应的一个。
第二导电接触图案375的突出部375P和第一上绝缘层237的凹槽239的布置、宽度和高度可以与参照图1A描述的相同。因此，第二导电接触图案357可以与第一导电接触图案235间隔开。另选地，第二导电接触图案375的突出部375P和第一上绝缘层237的凹槽239的布置、宽度和高度可以与参照图2B或图2C描述的相同。可以通过用导电粘合剂图案241B填充相应的凹槽239来将第二导电接触图案375电连接到第一导电接触图案235。导电粘合剂图案241B可以在第二导电接触图案375和第一导电接触图案235之间延伸。导电粘合剂图案241B可以包含环氧树脂的固化材料或者包含具有银纳米颗粒、硼氮化物和环氧树脂的混合物的固化材料。在另一实施方式中，在每个导电粘合剂图案241B与第二上绝缘层370之间可以存在空间，从而在它们之间产生间隙G，如参照图2A描述的。
图6A至图6C、图7A至图7C和图8是例示了制造图5中示出的半导体存储装置的方法的实施方式的截面图。在下面的附图中，第一下结构和第二下结构的结构与参照图5描述的相同，因此将省略重复的描述。
图6A至图6C是例示了在第一基板上形成第一结构的处理的截面图。
参照图6A，在第一基板201上形成参照图5描述的第一下结构200。
参照图6B，在第一下结构200上形成第一导电接触图案233和235。第一导电接触图案233和235连接到如参照图5描述的第一下结构200的晶体管TR。
随后，可以在第一下结构200上形成覆盖第一导电接触图案233和235的第一上绝缘层237。随后，可以使用光刻处理和蚀刻处理来形成凹槽239，由此使对应的第一导电接触图案233和235暴露。例如，可以通过凹槽239来使第一导电接触图案的上图案235暴露。当省略了上图案235时，可以通过凹槽239来使第一导电接触图案的下图案233暴露。
在第一上绝缘层237中形成凹槽239的处理中，可以如参照图3A描述地形成保护层161。另选地，可以在参照图4描述的处理ST1中对第一上绝缘层237的上表面进行表面处理。
参照图6C，可以形成抗氧化层290，以保护第一导电接触图案的被暴露的表面。例如，可以在第一上绝缘层237的表面上共形地形成抗氧化层290，以覆盖上图案235的被暴露的表面。抗氧化层290可以由具有与第一上绝缘层237的蚀刻速率不同的蚀刻速率的材料形成，以减少对第一上绝缘层237的损害并且被选择性地去除。例如，抗氧化层290可以包含氮化物。
图7A至图7C是例示了在第二基板上形成第二结构的处理的截面图。
参照图7A，在第二基板301上形成参照图5描述的第二下结构300。
参照图7B，可以在第二下结构300上形成至少一个氧化物层。在实施方式中，可以在第二下结构300上形成其中层叠有氧化物层371、蚀刻阻挡层373和氧化物层374的结构。蚀刻阻挡层373可以包括氮化物层。
随后，可以形成穿透其中层叠有氧化物层371、蚀刻阻挡层373和氧化物层374的结构的第二导电接触图案375。第二导电接触图案375可以连接到如参照图5描述的第二下结构300的存储单元阵列CAR。例如，第二导电接触图案375可以经由第二下结构300的位线BL、源极接触结构SCT和导电图案313电连接到存储单元阵列CAR。
参照图7C，去除图7B中示出的氧化物层374，以使蚀刻阻挡层373暴露。因此，可以形成包括氧化物层371和蚀刻阻挡层373的第二上绝缘层370。另外，可以使第二导电接触图案375的突出部375P暴露，突出部375P从第二上绝缘层370突出。
图8是例示了将第二结构设置在第一结构上的处理的截面图。
参照图8，在第一结构上设置第二结构之前，通过去除参照图6C描述的抗氧化层290来使第一导电接触图案暴露。例如，去除抗氧化层290，使得第一接触图案的上图案235可以被暴露。随后，可以在每个凹槽239中形成导电粘合剂材料241A。可以使用参照图3A至图3C描述的方法来形成或者使用参照图4描述的方法来形成导电粘合剂材料241A。
随后，在第一基板201上设置第二基板301，使得在第一上绝缘层237上形成第二上绝缘层370。第二基板301在第一基板201上对准，使得第二导电接触图案375的突出部375P与它们对应的凹槽239交叠。
随后，如参照图1B描述的，第一上绝缘层237和第二上绝缘层370彼此紧密粘附，使得第二导电接触图案375的突出部127P在凹槽239中对准。然后，使导电粘合剂材料241A固化。因此，第一导电接触图案的上图案235可以利用导电粘合剂图案241B电连接到第二导电接触图案375，如参照图5描述的。
图9是例示了按照本公开的实施方式的半导体存储装置的截面图。图9例示了按照本公开的实施方式的半导体存储装置，其中，第一下结构400包括存储单元阵列和第二下结构500，第二下结构500包括构成外围电路的晶体管。
参照图9，形成在第一基板401上的第一下结构400以与如参照图5描述的第二下结构300相同的结构形成。换句话说，存储单元阵列CAR可以被形成在第一基板401上。第一导电接触图案435和第一上绝缘层437被设置在第一基板401上，在第一导电接触图案435和第一上绝缘层437与第一基板401之间插置有第一下结构400。
第一导电接触图案435可以通过与图5中示出的连接结构345、347、363、355和357相同的连接结构连接到第一下结构400的存储单元阵列CAR。例如，第一导电接触图案435可以通过与图5中示出的连接结构345、347、363、355和357相同的连接结构经由第一下结构400的位线BL、源极接触结构SCT和导电图案413连接到存储单元阵列CAR。
第一上绝缘层437可以由与参照图5描述的第一上绝缘层327相同的材料以与参照图5描述的第一上绝缘层327相同的结构形成。换句话说，第一上绝缘层437可以包括与第一导电接触图案435交叠的凹槽439。
形成在第二基板501上的第二下结构500以与参照图5描述的第一下结构200相同的结构形成。换句话说，构成外围电路的晶体管TR可以被形成在第二基板501上。第二导电接触图案575和第二上绝缘层570可以被形成在第二基板501上，第二导电接触图案575和第二上绝缘层570与第二基板501之间插置有第二下结构500。
第二导电接触图案575可以通过与图5中示出的连接结构221、223和235相同的连接结构连接到第二下结构500的晶体管TR。第二导电接触图案575可以由与图5中示出的第二导电接触图案375相同的材料以与图5中示出的第二导电接触图案375相同的结构形成。换句话说，第二导电接触图案575可以包括从第二上绝缘层570突出的突出部575P。第二导电接触图案375可以被形成在下图案533上。下图案533可以以与参照图5描述的下图案233相同的结构形成。
第二上绝缘层570可以由与参照图5描述的第二上绝缘层370相同的材料以与参照图5描述的第二上绝缘层370相同的结构形成。
第一导电接触图案435和第二导电接触图案575可以通过填充凹槽439的导电粘合剂图案441B电连接。导电粘合剂图案441B可以由与参照图5描述的导电粘合剂图案241B相同的材料形成。
可以使用参照图6A、图6B、图6C、图7A、图7B、图7C和图8描述的制造半导体存储装置的方法来形成参照图9描述的半导体存储装置。
图10是例示根据本公开的实施方式的存储系统的配置的框图。
参照图10，根据本公开的实施方式的存储系统1100包括存储装置1120和存储控制器1110。
存储装置1120可以是配置有多个闪存存储芯片的多芯片封装。存储装置1120可以包括图5和图9中示出的半导体存储装置中的任一个。
存储控制器1110被配置为控制存储装置1120，并且可以包括静态随机存取存储器(SRAM)1111、CPU 1112、主机接口1113、纠错码(ECC)1114和存储器接口1115。SRAM 1111用作CPU 1112的操作存储器，CPU 1112对存储控制器1110的数据交换执行整体控制操作，并且主机接口1113包括用于与存储系统1100连接的主机的数据交换协议。ECC 1114检测并且纠正从存储装置1120读取的数据中包括的错误，并且存储器接口1115与存储装置1120接口连接。另外，控制器1110还可以包括与主机接口连接的用于存储代码数据的ROM等。
如上所述配置的存储系统1100可以是其中存储装置1120与控制器1110组合的存储卡或固态盘(SSD)。例如，当存储系统1100是SSD时，存储控制器1100可以通过诸如通用串行总线(USB)协议、多媒体卡(MMC)协议、外围组件互连(PCI)协议、PCI-快速(PCI-E)协议、高级技术附件(ATA)协议、串行ATA(SATA)协议、并行ATA(PATA)协议、小型计算机小接口(SCSI)协议、增强型小磁盘接口(ESDI)协议和集成驱动电子(IDE)协议等这样的各种接口协议当中的一种来与外部(例如，主机)通信。
图11是例示根据本公开的实施方式的计算系统的配置的框图。
参照图11，根据本公开的实施方式的计算系统1200可以包括与系统总线1260电连接的CPU 1220、随机存取存储器(RAM)1230、用户接口1240、调制解调器1250和存储系统1210。当计算系统1200是移动装置时，还可以包括用于向计算系统1200供应操作电压的电池，并且还可以包括应用芯片集、相机图像处理器(CIS)、移动D-RAM等。
按照本公开，第一导电接触图案和第二导电接触图案通过使用绝缘层的凹槽和填充凹槽的导电粘合剂材料来彼此连接，使得存储单元和外围电路可以彼此连接。
凹槽提供了供第二导电接触图案的突出部插入的空间，使得能提高第二导电接触图案的对准稳定性。
可以通过粘度控制来使导电粘合剂材料具有流动性。因此，尽管第二导电接触图案和第一导电接触图案没有彼此直接接触，但是第一导电接触图案可以通过填充凹槽的导电粘合剂材料的固化材料来稳定地连接到设置在凹槽中的第二导电接触图案。
如上所述，在本公开中，可以通过使用绝缘层的凹槽和导电粘合剂材料来提高半导体存储装置的制造处理的稳定性。
已经在附图和说明书中描述了本公开的实施方式。尽管这里使用了特定术语，但是这些术语仅是为了解释本公开的实施方式。因此，本公开不限于上述实施方式，并且在本公开的精神和范围内许多变形是可能的。对于本领域技术人员而言应该显而易见的是，除了本文中公开的实施方式之外，还可以基于本公开的技术范围进行各种修改。
就没有被不同地定义而论，本文中使用的所有术语(包括技术术语或科学术语)具有本公开所属领域的技术人员通常所理解的含义。应当理解具有在字典中所定义的定义的术语，使得它们具有与相关技术的上下文一致的含义。就没有在本申请中被清楚地定义而论，不应该以理想的或过度正式的方式理解术语。
相关申请的交叉引用
本申请要求于2019年1月30日在韩国知识产权局提交的韩国专利申请号10-2019-0012123的优先权，该韩国专利申请的全部公开以引用方式并入本文中。

Claims (22)

1.一种半导体存储装置，该半导体存储装置包括：
第一基板，该第一基板包括外围电路、连接到所述外围电路的第一导电接触图案以及具有使所述第一导电接触图案暴露的凹槽的第一上绝缘层；
第二基板，该第二基板包括存储单元阵列、设置在所述存储单元阵列上的第二上绝缘层以及第二导电接触图案，所述第二上绝缘层形成在所述存储单元阵列和所述第一上绝缘层之间，所述第二导电接触图案穿过所述第二上绝缘层突出到所述凹槽的开口中；以及
导电粘合剂图案，所述导电粘合剂图案填充所述凹槽，以将所述第二导电接触图案连接到所述第一导电接触图案。
2.根据权利要求1所述的半导体存储装置，其中，所述导电粘合剂图案围绕所述第二导电接触图案，以接触所述第二导电接触图案和所述第一导电接触图案。
3.根据权利要求1所述的半导体存储装置，其中，所述导电粘合剂图案完全地填充所述凹槽。
4.根据权利要求1所述的半导体存储装置，其中，所述导电粘合剂图案部分地填充所述凹槽，以产生间隙。
5.根据权利要求1所述的半导体存储装置，其中，每个所述导电粘合剂图案包含环氧树脂的固化材料。
6.根据权利要求1所述的半导体存储装置，其中，每个所述导电粘合剂图案包含具有银纳米颗粒、硼氮化物和环氧树脂的混合物的固化材料。
7.根据权利要求1所述的半导体存储装置，所述半导体存储装置还包括：
多个晶体管，所述多个晶体管在所述外围电路内；
多层绝缘层，该多层绝缘层被设置在所述第一基板和所述第一上绝缘层之间，所述多层绝缘层覆盖所述晶体管；以及
连接结构，该连接结构穿透所述多层绝缘层，所述连接结构将每个所述第一导电接触图案电连接到所述多个晶体管当中的与该第一导电接触图案对应的晶体管。
8.根据权利要求1所述的半导体存储装置，其中，所述存储单元阵列包括：
栅极层叠结构，该栅极层叠结构被设置在所述第二基板和所述第二上绝缘层之间，所述栅极层叠结构包括交替层叠的导电图案和层间绝缘层；
沟道结构，所述沟道结构穿透所述栅极层叠结构；以及
存储器层，该存储器层被设置在每个所述导电图案和每个所述沟道结构之间。
9.根据权利要求8所述的半导体存储装置，所述半导体存储装置还包括：
多层绝缘层，该多层绝缘层被设置在所述存储单元阵列和所述第二上绝缘层之间；
位线，所述位线被埋置在所述多层绝缘层中，以连接到所述沟道结构；以及
连接结构，该连接结构穿透所述多层绝缘层，所述连接结构将每个所述第二导电接触图案电连接到与该第二导电接触图案对应的导电图案和与该第二导电接触图案对应的位线。
10.根据权利要求1所述的半导体存储装置，其中，所述第一上绝缘层从所述第一导电接触图案的突出部的高度大于每个所述第二导电接触图案从所述第二上绝缘层的突出部的高度。
11.根据权利要求1所述的半导体存储装置，其中，所述第一上绝缘层从所述第一导电接触图案的突出部具有与每个所述第二导电接触图案从所述第二上绝缘层的突出部相同的高度。
12.根据权利要求1所述的半导体存储装置，其中，所述第一上绝缘层从所述第一导电接触图案的突出部具有与所述第二导电接触图案从所述第二上绝缘层的一些突出部相同的高度，并且所述第一上绝缘层从所述第一导电接触图案的一些突出部的高度大于所述第二导电接触图案从所述第二上绝缘层的其余突出部的高度。
13.根据权利要求1所述的半导体存储装置，其中，每个所述凹槽被形成为具有比所述第二导电接触图案当中的与该凹槽对应的第二导电接触图案宽的宽度。
14.一种半导体存储装置，该半导体存储装置包括：
外围电路和存储单元阵列，该外围电路和该存储单元阵列彼此相对，在所述外围电路和所述存储单元阵列之间插置有第一上绝缘层；
第一导电接触图案和第二导电接触图案，所述第一导电接触图案连接到所述外围电路和所述存储单元阵列中的一个，所述第二导电接触图案连接到所述外围电路和所述存储单元阵列中的另一个，所述第一导电接触图案与所述第二导电接触图案相对，所述第一导电接触图案与凹槽交叠，所述第二导电接触图案具有向所述凹槽内部突出的突出部；以及
导电粘合剂图案，所述导电粘合剂图案填充所述凹槽，使得所述第二导电接触图案分别连接到所述第一导电接触图案。
15.根据权利要求14所述的半导体存储装置，其中，所述第一上绝缘层更远地突出到比所述第一导电接触图案的高度高的第一高度，以限定所述凹槽，
其中，所述第二导电接触图案的所述突出部被形成为等于或小于所述第一高度的高度。
16.根据权利要求14所述的半导体存储装置，其中，所述导电粘合剂图案在所述第一导电接触图案和所述第二导电接触图案之间延伸。
17.根据权利要求14所述的半导体存储装置，其中，每个所述凹槽被形成为具有比所述第二导电接触图案当中的与该凹槽对应的第二导电接触图案的宽度宽的宽度。
18.根据权利要求14所述的半导体存储装置，其中，每个所述导电粘合剂图案包含环氧树脂的固化材料或者包含具有银纳米颗粒、硼氮化物和环氧树脂的混合物的固化材料。
19.根据权利要求14所述的半导体存储装置，其中，所述存储单元阵列和所述外围电路形成在第一基板和第二基板之间，
其中，所述第一导电接触图案连接到设置在所述第一基板上的所述存储单元阵列，并且
所述第二导电接触图案连接到构成设置在所述第二基板上的所述外围电路的晶体管。
20.根据权利要求1所述的半导体存储装置，其中，所述存储单元阵列包括：
栅极层叠结构，该栅极层叠结构包括交替地层叠在所述第一基板上的层间绝缘层和导电图案；
沟道结构，所述沟道结构穿透所述栅极层叠结构；以及
存储器层，该存储器层被设置在每个所述导电图案和每个所述沟道结构之间。
21.根据权利要求20所述的半导体存储装置，所述半导体存储装置还包括：
多层绝缘层，该多层绝缘层被设置在所述存储单元阵列和所述第一上绝缘层之间；
位线，所述位线被埋置在所述多层绝缘层中，以连接到所述沟道结构；以及
连接结构，该连接结构穿透所述多层绝缘层，所述连接结构将每个所述第一导电接触图案电连接到所述导电图案和所述位线当中的与该第一导电接触图案对应的导电图案和位线，
其中，所述第一导电接触图案被埋置在所述第一上绝缘层中，面对所述第二导电接触图案，并且具有因所述凹槽而敞露的表面。
22.根据权利要求20所述的半导体存储装置，所述半导体存储装置还包括：
多层绝缘层，该多层绝缘层被设置在所述晶体管和第二上绝缘层之间；以及
连接结构，该连接结构穿透所述多层绝缘层，所述连接结构将每个所述第二导电接触图案电连接到所述晶体管当中的与该第二导电接触图案对应的晶体管。
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