CN111504526A - Piezoresistive pressure sensor chip with stress concentration structure and preparation method thereof - Google Patents
Piezoresistive pressure sensor chip with stress concentration structure and preparation method thereof Download PDFInfo
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- CN111504526A CN111504526A CN202010478838.7A CN202010478838A CN111504526A CN 111504526 A CN111504526 A CN 111504526A CN 202010478838 A CN202010478838 A CN 202010478838A CN 111504526 A CN111504526 A CN 111504526A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/20—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
- G01L9/02—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0264—Pressure sensors
Abstract
The invention discloses a piezoresistive pressure sensor chip with a stress concentration structure and a preparation method thereof. The shallow groove film structure is divided into a shallow groove structure and a film structure, the shallow groove structure is composed of four shallow grooves distributed along the edge of the film and square shallow grooves distributed in the film, stress is concentrated between the end parts of the two shallow groove structures, the distributed square shallow grooves further concentrate and adjust stress distribution, and the sensitivity of the sensor is improved. Four piezoresistor strips are uniformly arranged at the stress concentration position, the four piezoresistor strips are connected by a metal lead to form a semi-open-loop Wheatstone full bridge, and the bridge is connected with five bonding pads arranged on the substrate to realize the input and output of electric signals. The back cavity consists of a peninsula and an island, and a gap between the peninsula and the island corresponds to the end parts of the two shallow groove structures; the peninsula and the islands improve the stress concentration effect, improve the rigidity of the sensor and improve the linearity of the sensor.
Description
Technical Field
The invention belongs to the technical field of micro-electromechanical sensors, and particularly relates to a piezoresistive pressure sensor chip with a stress concentration structure and a preparation method thereof.
Background
With the development of micro-mechanical electronic system technology, micro-pressure sensors have been widely applied in the fields of aerospace, smart home, invasive medical equipment and the like; with the rapid development of various fields, the performance, volume and the like of the sensor have more strict requirements, the MEMS sensor is undoubtedly an ideal choice, and particularly, a micro-pressure measurement sensor with stable performance, high dynamic performance and high sensitivity is urgently needed to guarantee in the field of biomedicine.
The MEMS micro-pressure sensor adopts many measurement principles, mainly including piezoresistive, piezoelectric, capacitive, resonant, etc., but compared with MEMS micro-pressure sensors of other principles, the MEMS piezoresistive micro-pressure sensor has the advantages of wide measurement range, measurable static and dynamic signals, good dynamic response, simple post-processing circuit, low processing cost, etc., and thus is widely applied.
The sensitivity and linearity of the MEMS piezoresistive pressure sensor are the most important working indexes, so the structure of the sensor is often designed with the sensitivity and linearity as the optimization targets in the design process. However, sensitivity and linearity have a mutually restricted relationship, which affects further improvement of sensor performance. In the design of the MEMS piezoresistive pressure sensor, the mutual restriction relationship between the sensitivity and the linearity of the sensor is weakened, and the obtaining of the optimal values of the sensitivity and the linearity is particularly important.
At present, the minimum measuring range of the MEMS piezoresistive micro-pressure sensor is mostly in the order of kPa, but pressure measurement in the Pa order is needed in the biomedical field. Therefore, how to improve the sensitivity of the sensor, balance the contradiction between the sensitivity and the linearity is a difficult point which needs to be broken through when the MEMS piezoresistive micro-pressure sensor carries out reliable and accurate measurement.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a piezoresistive pressure sensor chip with a stress concentration structure, which can measure Pa-level micro-pressure and has the characteristics of high linearity, high dynamic performance and the like.
In order to achieve the purpose, the piezoresistive pressure sensor chip with the stress concentration structure comprises a substrate and a glass substrate bonded with the substrate, wherein a back cavity is etched on the back surface of the substrate, the bottom surface of the back cavity is the back surface of a thin film, a first peninsula, a second peninsula, a third peninsula and a fourth peninsula are arranged in the back cavity, one ends of the first peninsula, the second peninsula, the third peninsula and the fourth peninsula are all connected with the side wall of the back cavity, a first island is arranged at the other end of the first peninsula, a second island is arranged at the other end of the second peninsula, a third island is arranged at the other end of the third peninsula, and a fourth island is arranged at the other end of the fourth peninsula; a first piezoresistor strip, a second piezoresistor strip, a third piezoresistor strip and a fourth piezoresistor strip are arranged on the front surface of the film, the first piezoresistor strip is positioned right above a gap between the first peninsula and the first island, the second piezoresistor strip is positioned right above a gap between the second peninsula and the second island, the third piezoresistor strip is positioned right above a gap between the third peninsula and the third island, and the fourth piezoresistor strip is positioned right above a gap between the fourth peninsula and the fourth island;
the first piezoresistor strip, the second piezoresistor strip, the third piezoresistor strip and the fourth piezoresistor strip are connected through metal leads and bonding pads to form a Wheatstone bridge.
Furthermore, a first stress concentration groove, a second stress concentration groove, a third stress concentration groove and a fourth stress concentration groove are formed in the inner side of the film; a first stress concentration groove and a second stress concentration groove are respectively formed in two sides of the first piezoresistor strip, and a third stress concentration groove and a fourth stress concentration groove are respectively formed in two sides of the third piezoresistor strip; and a second piezoresistor strip is arranged between the second stress concentration groove and the third stress concentration groove, and a fourth piezoresistor strip is arranged between the fourth stress concentration groove and the first stress concentration groove.
Furthermore, the depth of the first stress concentration groove, the second stress concentration groove, the third stress concentration groove and the fourth stress concentration groove is 10% -80% of the thickness of the film.
Furthermore, a first stress adjusting groove and a second stress adjusting groove are respectively formed in two sides of the position right above the first island; a third stress adjusting groove and a fourth stress adjusting groove are respectively arranged on two sides of the position right above the second island; a fifth stress adjusting groove and a sixth stress adjusting groove are respectively formed in two sides of the position right above the third island; and a seventh stress adjusting groove and an eighth stress adjusting groove are respectively arranged on two sides right above the fourth island.
Furthermore, the glass substrate is provided with a groove.
Further, the widths of the first peninsula, the second peninsula, the third peninsula, the fourth peninsula, the first island, the second island, the third island and the fourth island are equal and are all 140-200 um.
Further, the wheatstone bridge is a half-open loop wheatstone bridge, and an open loop of the loop wheatstone bridge is used for being connected with an external resistor.
The preparation method of the piezoresistive pressure sensor chip with the stress concentration structure comprises the following steps:
step 2, carrying out double-sided high-temperature oxidation on the cleaned SOI silicon wafer, forming a first silicon dioxide layer on the upper surface of the SOI silicon wafer, and forming a second silicon dioxide layer on the lower surface of the SOI silicon wafer;
step 3, etching silicon dioxide in the piezoresistor area in the first silicon dioxide layer by using the piezoresistor plate, carrying out boron ion light doping to form a first piezoresistor strip, a second piezoresistor strip, a third piezoresistor strip and a fourth piezoresistor strip, and then annealing;
step 4, depositing a third silicon dioxide layer on the front surface of the product obtained in the step 3, carrying out photoetching and reactive ion etching by using an ohmic contact plate to realize patterning of the first silicon dioxide layer and the third silicon dioxide layer, removing silicon dioxide in an ohmic contact area between the first silicon dioxide layer and the third silicon dioxide layer, using the silicon dioxide layers in the rest areas as masks, and then carrying out boron ion heavy doping to form the ohmic contact area;
and 9, bonding the substrate manufactured in the step with the glass substrate processed in the step in a vacuum manner to obtain the ultra-low pressure sensor chip.
Further, after the step 4 is completed, annealing treatment is carried out on the SOI silicon wafer, so that the impurity doping concentration of the ohmic contact region is further uniform.
Compared with the prior art, the invention has at least the following beneficial technical effects:
the sensor chip provided by the invention has the characteristics of reasonable structure, high reliability, high linearity, high frequency response, low cost and the like, and is favorable for realizing batch production.
The invention improves the traditional film structure, and the maximum stress distribution is not concentrated according to the stress distribution condition of the traditional film structure under the action of pressure, and the stress value is smaller, thus the requirement of high sensitivity cannot be met; in order to improve the defects, a peninsula and an island structure are additionally arranged in a film back cavity, a gap is reserved between the peninsula and the island, the principle of stress mutation is applied, stress is concentrated right above the gap, and a piezoresistor strip is arranged right above the gap, so that the problems that the stress value is not concentrated and the stress value is not large in the traditional film structure are solved, the rigidity of the film structure is also improved by the peninsula island structure, the linearity and the natural frequency are improved to a certain extent, and the dynamic performance of the sensor is improved by the improvement of the natural frequency.
In order to make the effect of stress transverse concentration obvious, four stress concentration grooves are added, so that the stress is concentrated in the area between two adjacent stress grooves. Peninsula island structure and stress concentration groove, stress adjustment groove make stress concentration's vertical and horizontal position all obtain the restriction, and then make stress concentration in the region of restriction, arrange the position of restriction here with the piezo-resistor strip for the piezo-resistor strip is under the effect of pressure, and the change of resistance value of piezo-resistor strip is increaseed, thereby has improved wheatstone bridge's output voltage, has finally played the effect that has improved sensor sensitivity.
In order to further adjust the distribution and the magnitude of the stress in the limited area, eight square stress adjusting grooves are etched on the thin film structure, and the positions of every two stress adjusting grooves are distributed on the thin film, namely on two sides of the position corresponding to the island structure. Therefore, the stress distribution in the limited area is adjusted, so that the stress concentration effect is more obvious. Eventually improving the sensitivity of the overall sensor.
Furthermore, the Wheatstone bridge is a half-open loop Wheatstone bridge, and the open loop is used for being connected with an external resistor, so that the phenomenon that the resistance of the four voltage-sensitive resistor strips is inconsistent due to process errors is compensated.
The preparation method of the sensor chip is simple in manufacturing method, high in reliability and easy for batch production.
Drawings
FIG. 1 is a schematic axial view of the present invention;
FIG. 2 is a schematic front view of the present invention;
FIG. 3 is a rear isometric view of the present invention;
FIG. 4 is a perspective view of the present invention;
FIG. 5 is an enlarged view of a portion of FIG. 4 at A;
FIG. 6a is a schematic diagram of a first varistor strip distribution;
FIG. 6b is a schematic diagram of a third strip distribution;
FIG. 7a is a schematic diagram of a second varistor strip distribution;
FIG. 7b is a fourth schematic view of a varistor strip distribution;
FIG. 8 is a schematic diagram of a Wheatstone bridge formed by connecting varistor strips according to the present invention;
FIG. 9 is a schematic axial view of a glass substrate according to the present invention;
FIG. 10a is a schematic view of the path from 1 to 2 under pressure;
FIG. 10b is a schematic view of the stress distribution under pressure of the present invention;
FIG. 11 is a schematic diagram of a process for fabricating the present invention.
In the drawings: 1. a substrate, 2-1, a first stress concentration groove, 2-2, a second stress concentration groove, 2-3, a third stress concentration groove, 2-4, a fourth stress concentration groove, 3-1, a first stress adjustment groove, 3-2, a second stress adjustment groove, 3-3, a third stress adjustment groove, 3-4, a fourth stress adjustment groove, 3-5, a fifth stress adjustment groove, 3-6, a sixth stress adjustment groove, 3-7, a seventh stress adjustment groove, 3-8, an eighth stress adjustment groove, 4-1, a first piezoresistor strip, 4-2, a second piezoresistor strip, 4-3, a third piezoresistor strip, 4-4, a fourth piezoresistor strip, 5, a glass substrate, 5-1, a groove, 6, a film, 7-1, a first metal lead wire, 7-2, second metal leads, 7-3, third metal leads, 7-4, fourth metal leads, 7-5, fifth metal leads, 7-6, sixth metal leads, 7-7, seventh metal leads, 7-8, eighth metal leads, 8-1, first pads, 8-2, second pads, 8-3, third pads, 8-4, fourth pads, 8-5, fifth pads, 9-1, first islands, 9-2, second islands, 9-3, third islands, 9-4, fourth islands, 10-1, first peninsulas, 10-2, second peninsulas, 10-3, third peninsulas, 10-4, fourth peninsulas, 11, upper monocrystalline silicon, 12, buried silicon dioxide layers, 13, lower monocrystalline silicon, 14. a first silicon dioxide layer 15, an ohmic contact region 17, a second silicon dioxide layer 18 and a back cavity.
Detailed Description
In order to make the objects and technical solutions of the present invention clearer and easier to understand. The present invention will be described in further detail with reference to the following drawings and examples, wherein the specific examples are provided for illustrative purposes only and are not intended to limit the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Referring to fig. 1, a piezoresistive pressure sensor chip with a stress concentration structure is structurally divided into a thin film structure layer and a back cavity structure layer.
Referring to fig. 2, the thin film structure layer includes a square thin film 6, four L-shaped first stress concentration grooves 2-1, second stress concentration grooves 2-2, third stress concentration grooves 2-3, fourth stress concentration grooves 2-4 located on the inner side of the thin film 6 and sequentially arranged along the edge of the thin film 6, and eight square first stress adjustment grooves 3-1, second stress adjustment grooves 3-2, third stress adjustment grooves 3-3, fourth stress adjustment grooves 3-4, fifth stress adjustment grooves 3-5, sixth stress adjustment grooves 3-6, seventh stress adjustment grooves 3-7 and eighth stress adjustment grooves 3-8 located in the thin film 6, wherein the depths of the first to fourth stress concentration grooves and the depths from the first to eighth stress adjustment grooves are 10% -80% of the thickness of the thin film 6.
A gap is reserved between every two adjacent stress concentration grooves, a stress concentration area is formed between two end portions of each of the first to fourth stress concentration grooves, a first piezoresistor strip 4-1 is arranged in the stress concentration area between the first stress concentration groove 2-1 and the second stress concentration groove 2-2, a second piezoresistor strip 4-2 is arranged in the stress concentration area between the second stress concentration groove 2-2 and the third stress concentration groove 2-3, a third piezoresistor strip 4-3 is arranged in the stress concentration area between the third stress concentration groove 2-3 and the fourth stress concentration groove 2-4, and a fourth piezoresistor strip 4-4 is arranged in the stress concentration area between the fourth stress concentration groove 2-4 and the first stress concentration groove 2-1. And the effective length of all piezoresistor strips is along the crystal orientation with the largest piezoresistive coefficient, the first piezoresistor strip, the second piezoresistor strip, the third piezoresistor strip, the fourth piezoresistor strip, the fifth bonding pad 8 and the fourth piezoresistor strip are connected through metal leads to form a half-open-loop.
Referring to fig. 2 and 8, a first metal lead 7-1 connects a first end of the first varistor strip 4-1 to the first pad 8-1, and a second metal lead 7-2 connects a second end of the first varistor strip 4-1 to the second pad 8-2; a third metal lead 7-3 connects a first end of the fourth piezo-resistive strip 4-4 with the second pad 8-2, and a fourth metal lead 7-4 connects a second end of the fourth piezo-resistive strip 4-4 with the third pad 8-3; a fifth metal lead 7-5 connects a first end of the third piezoresistive strip 4-3 with the third pad 8-3, and a sixth metal lead 7-6 connects a second end of the third piezoresistive strip 4-3 with the fourth pad 8-4; a seventh metal lead 7-7 connects a first end of the second strip 4-2 to the fifth pad 8-5 and an eighth metal lead 7-8 connects a second end of the second strip 4-2 to the first pad 8-1. The fourth bonding pad 8-4 and the fifth bonding pad 8-5 are arranged into open loops and are used for being connected with an external resistor so as to compensate the phenomenon that the four voltage-sensitive resistor strips are inconsistent in resistance due to process errors.
Referring to fig. 3, the back cavity structure mainly includes: the first peninsula 10-1, the second peninsula 10-2, the third peninsula 10-3, the fourth peninsula 10-4, the first island 9-1, the second island 9-2, the third island 9-3 and the fourth island 9-4 which are connected with the matrix 1 and are uniformly distributed in the middle of the side edges of the film 6 and have the same width. A first island 9-1 is arranged at the end of the first peninsula 10-1, a second island 9-2 is arranged at the end of the second peninsula 10-2, a third island 9-3 is arranged at the end of the third peninsula 10-3, and a fourth island 9-4 is arranged at the end of the fourth peninsula 10-4. Central axes of the first island 9-1, the third island 9-3, the first peninsula 10-1 and the third peninsula 10-3 coincide, and central axes of the second island 9-2, the fourth island 9-4, the second peninsula 10-2 and the fourth peninsula 10-4 coincide; gaps of 35um to 50um are formed between the first peninsula 10-1 and the first island 9-1, between the second peninsula 10-2 and the second island 9-2, between the third peninsula 10-3 and the third island 9-3, and between the fourth peninsula 10-4 and the fourth island 9-4. The gap further concentrates the stress. The widths of the first to fourth peninsulas and the widths of the first to fourth islands are the same as the length of a gap between two adjacent stress concentration grooves, and are all 140-200 um.
Referring to fig. 4 and 5, the first to fourth stress concentration grooves have the same structure and size, and the first to eighth stress adjustment grooves have the same structure and size. The first stress adjusting groove 3-1 and the second stress adjusting groove 3-2 are respectively positioned at two sides right above the first island 9-1; the third stress adjusting groove 3-3 and the fourth stress adjusting groove 3-4 are respectively positioned at two sides right above the second island 9-2; the fifth stress adjusting groove 3-5 and the sixth stress adjusting groove 3-6 are respectively positioned at two sides right above the third island 9-3; the seventh stress adjustment groove 3-7 and the eighth stress adjustment groove 3-8 are respectively located at positions on both sides directly above the fourth island 9-4. First piezoresistive strip 4-1 is located directly above the gap between first peninsula 10-1 and first island 9-1; second piezoresistive strip 4-2 is located directly above the gap between second peninsula 10-2 and second island 9-2; a third piezoresistive strip 4-3 is located directly above the gap between the third peninsula 10-3 and the third island 9-3; fourth piezo-resistive strip 4-4 is located directly above the gap between fourth peninsula 10-4 and fourth island 9-4.
The back surface of the base 1 is vacuum bonded to the glass substrate 5. Referring to fig. 9, a groove 5-1 is further formed in the glass substrate 5, and the depth of the groove is determined by the displacement of the chip under the maximum pressure, so that the islands are ensured not to interfere with the glass, and the measurement of the absolute pressure is realized.
As a preferred embodiment of the invention, the film 2 is a square film, the first stress concentration groove 2-1, the second stress concentration groove 2-2, the third stress concentration groove 2-3 and the fourth stress concentration groove 2-4 which are uniformly distributed along the edge of the film are L-shaped, the two sides of the L shape are equal in length, and eight stress adjustment groove junctions in the film are square structures, so that the film is convenient to manufacture and equal in size.
Referring to fig. 6a and 6b, the first and third varistor strips 4-1 and 4-3 are of a four-fold strip configuration. Referring to fig. 7a and 7b, the second varistor strip 4-2 and the fourth varistor strip 4-4 are single-resistor strip structures, the initial resistance values of the four resistor strips are the same, and the effective length directions of the four resistor strips are all along the crystal direction of the maximum piezoresistive coefficient.
The working principle of the invention is as follows:
when the sensor chip is pressed, the film 6 deforms, and according to the piezoresistive effect of silicon, the resistance values of all the piezoresistor strips on the film 6 change under the action of stress, and the relationship between the resistance value change rate and the stress is as follows:
the sensor comprises a piezoresistor strip, a first piezoresistor strip 4-1, a second piezoresistor strip 4-2, a third piezoresistor strip 4-3 and a fourth piezoresistor strip 4-4, wherein R is the initial resistance value of the piezoresistor strip, pi is the piezoresistive coefficient of the piezoresistor strip, and sigma is the stress of the piezoresistor strip, △ R is the resistance of the piezoresistor changing under the action of pressure, the first piezoresistor strip 4-1, the second piezoresistor strip 4-2, the third piezoresistor strip 4-3 and the fourth piezoresistor strip 4-4 form a Wheatstone full bridge, when stress acts, the Wheatstone full bridge loses balance, and the voltage output by the bridge is in proportional relation with the external pressure, so that the pressure detection is realized, and the:
wherein: u shapeout-the output voltage of the wheatstone bridge; u shapein-supply voltage of a wheatstone bridge; pi44-a shear piezoresistive coefficient; sigmal-longitudinal stress; sigmat-a transverse stress; p-full scale pressure.
Referring to fig. 10a and 10b, under the action of pressure, the thin film structure layer begins to sink downward, the stress is adjusted by the square first to eighth stress adjustment grooves, and the stress at the end part of the shallow groove structure is further concentrated, so that the variation of the resistance values of the first to fourth piezoresistor strips is increased, and the sensitivity of the sensor is improved. As shown in fig. 10b, the stress of the sensor chip is more concentrated and the concentration area is enlarged compared to a flat film of the same size, ensuring that the varistor strips can be completely arranged in the concentration area. Meanwhile, the first to fourth peninsulas and the first to fourth islands of the back cavity increase the support and the mass of the structure, so that the rigidity of the structure is increased, and the linearity of the sensor is improved.
The peninsula and island structures of the back cavity structure improve the overall rigidity of the sensor, and the interval between the peninsula and the island structure improves the stress concentration effect again. Therefore, the structure has the characteristics of good linearity and high sensitivity.
The preparation method of the chip of the invention comprises the following steps:
referring to fig. 11, a method for manufacturing a piezoresistive pressure sensor chip with a stress concentration structure according to the present invention includes the following steps:
1, using an N-type (100) crystal face double-sided polishing SOI silicon wafer and BF33 glass, and cleaning the SOI silicon wafer by using HF solution, wherein the SOI silicon wafer consists of an upper monocrystalline silicon 11, a buried silicon dioxide layer 12 and a lower monocrystalline silicon 13, and the buried silicon dioxide layer 12 separates the upper monocrystalline silicon 11 from the lower monocrystalline silicon 13;
2, carrying out double-sided high-temperature oxidation on the SOI silicon wafer at 900-1200 ℃, forming a first silicon dioxide layer 14 on the upper surface of the SOI silicon wafer, and forming a second silicon dioxide layer 17 on the lower surface of the SOI silicon wafer;
3, removing silicon dioxide in a piezoresistor area in the first silicon dioxide layer 14 by using a piezoresistor plate and using a Reactive Ion Etching (RIE) process, carrying out boron Ion light doping to respectively form a first piezoresistor strip 4-1, a second piezoresistor strip 4-2, a third piezoresistor strip 4-3 and a fourth piezoresistor strip 4-4, and then annealing to ensure that the boron Ion impurity concentration is uniformly distributed;
4 forming a third silicon dioxide layer on the front surface of the product obtained in the step 3 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process on the front surface, wherein the third silicon dioxide layer is used for ensuring that the piezoresistor region is not influenced in heavy doping; photoetching and reactive ion etching processes are carried out by using an ohmic contact plate to realize the patterning of the first silicon dioxide layer 14 and the third silicon dioxide layer, silicon dioxide of the ohmic contact area 15 in the first silicon dioxide layer 14 and the third silicon dioxide layer is removed, the silicon dioxide layers in the rest areas are used as masks, and then boron ion heavy doping is carried out to form the ohmic contact area 15 with low resistance; then annealing treatment is carried out, so that the impurity doping concentration of the ohmic contact region 15 is further uniform, and stable contact is guaranteed to be formed;
5, photoetching the shape of the metal lead on the front surface of the product obtained in the step 4 by using a metal lead plate, sputtering a metal layer to form a metal lead 7 and a bonding pad 8, and then carrying out alloying treatment at high temperature;
6, photoetching the front surface of the SOI sheet obtained in the step 5 by using a front surface shallow groove structure etching plate to form four L-shaped stress concentration grooves and eight square stress adjusting grooves, wherein the stress concentration grooves comprise a first stress concentration groove 2-1, a second stress concentration groove 2-2, a third stress concentration groove 2-3 and a fourth stress concentration groove 2-4, the stress adjusting grooves comprise a first stress adjusting groove 3-1, a second stress adjusting groove 3-2, a third stress adjusting groove 3-3, a fourth stress adjusting groove 3-4, a fifth stress adjusting groove 3-5, a sixth stress adjusting groove 3-6, a seventh stress adjusting groove 3-7 and an eighth stress adjusting groove 3-8, and the depths of the first to fourth stress concentration grooves and the depths of the first to eighth stress adjusting grooves are the same and are 10-80% of the thickness of the film;
7, photoetching the back surface of the SOI chip by using a back cavity etching plate, and removing redundant silicon by using a silicon dioxide buried layer 12 in the SOI chip as an etching stop layer in a dry method to form a back cavity 18 and four peninsulas and four islands in the back cavity 18, wherein the four peninsulas are a first peninsula 10-1, a second peninsula 10-2, a third peninsula 10-3 and a fourth peninsula 10-4, and the four islands are as follows: islands 9-1, second islands 9-2, third islands 9-3 and fourth islands 9-4; the bottom surface of the back cavity 18 is the film 6, and the SOI sheet after the step is finished is the substrate 1;
8, etching the BF33 glass substrate 5 to form a groove 5-1;
and 9, carrying out vacuum bonding on the base body 1 manufactured in the step 7 and the glass substrate 5 processed in the step 8 to manufacture the absolute pressure ultra-low pressure sensor chip.
The main technical indexes achieved by the invention are as follows:
1. measurement range: 0 to 500 Pa;
2. and (3) measuring precision: better than 0.5% FS;
3. sensitivity: greater than 30 μ V/V/Pa;
4. working temperature: -50 to 120 ℃;
5. first-order natural frequency: greater than 10 kHz.
The above description is only one embodiment of the present invention, and not all or only one embodiment, and any equivalent alterations made by those skilled in the art after reading the present specification are covered by the claims of the present invention.
Claims (9)
1. The piezoresistive pressure sensor chip with the stress concentration structure is characterized by comprising a base body (1) and a glass substrate (5) bonded with the base body (1), wherein a back cavity (18) is etched on the back surface of the base body (1), the bottom surface of the back cavity (18) is the back surface of a thin film (6), a first peninsula (10-1), a second peninsula (10-2), a third peninsula (10-3) and a fourth peninsula (10-4) are arranged in the back cavity (18), one end of each of the first peninsula (10-1), the second peninsula (10-2), the third peninsula (10-3) and the fourth peninsula (10-4) is connected with the side wall of the back cavity (18), a first island (9-1) is arranged at the other end of the first peninsula (10-1), and a second island (9-2) is arranged at the other end of the second peninsula (10-2), a third island (9-3) is arranged at the other end of the third peninsula (10-3), and a fourth island (9-4) is arranged at the other end of the fourth peninsula (10-4); the front surface of the film (6) is provided with a first piezoresistor strip (4-1), a second piezoresistor strip (4-2), a third piezoresistor strip (4-3) and a fourth piezoresistor strip (4-4), the first piezoresistive strip (4-1) is located directly above the gap between the first peninsula (10-1) and the first island (9-1), the second piezo-resistive strip (4-2) is located directly above the gap between the second peninsula (10-2) and the second island (9-2), the third piezo-resistive strip (4-3) is located directly above the gap between the third peninsula (10-3) and the third island (9-3), the fourth piezo-resistive strip (4-4) is located directly above the gap between the fourth peninsula (10-4) and the fourth island (9-4);
the first piezoresistor strip (4-1), the second piezoresistor strip (4-2), the third piezoresistor strip (4-3) and the fourth piezoresistor strip (4-4) are connected through a metal lead and a bonding pad to form a Wheatstone bridge.
2. The piezoresistive pressure sensor chip with a stress concentration structure according to claim 1, wherein the thin film (6) is internally provided with a first stress concentration groove (2-1), a second stress concentration groove (2-2), a third stress concentration groove (2-3) and a fourth stress concentration groove (2-4); a first stress concentration groove (2-1) and a second stress concentration groove (2-2) are respectively formed in two sides of the first piezoresistor strip (4-1), and a third stress concentration groove (2-3) and a fourth stress concentration groove (2-4) are respectively formed in two sides of the third piezoresistor strip (4-3); and a second piezoresistor strip (4-2) is arranged between the second stress concentration groove (2-2) and the third stress concentration groove (2-3), and a fourth piezoresistor strip (4-4) is arranged between the fourth stress concentration groove (2-4) and the first stress concentration groove (2-1).
3. The piezoresistive pressure sensor chip with a stress concentration structure according to claim 2, wherein the depth of the first stress concentration groove (2-1), the second stress concentration groove (2-2), the third stress concentration groove (2-3) and the fourth stress concentration groove (2-4) is 10% to 80% of the thickness of the thin film (6).
4. The piezoresistive pressure sensor chip with a stress concentration structure according to claim 1, wherein a first stress adjusting groove (3-1) and a second stress adjusting groove (3-2) are respectively formed on two sides of the position right above the first island (9-1); a third stress adjusting groove (3-3) and a fourth stress adjusting groove (3-4) are respectively formed in two sides of the position right above the second island (9-2); a fifth stress adjusting groove (3-5) and a sixth stress adjusting groove (3-6) are respectively formed in two sides of the position right above the third island (9-3); and a seventh stress adjusting groove (3-7) and an eighth stress adjusting groove (3-8) are respectively arranged on two sides of the position right above the fourth island (9-4).
5. The piezoresistive pressure sensor chip with a stress concentration structure according to claim 1, wherein the glass substrate (5) is provided with a groove (5-1).
6. The piezoresistive pressure sensor chip with a stress concentration structure according to claim 1, wherein the widths of the first peninsula (10-1), the second peninsula (10-2), the third peninsula (10-3), the fourth peninsula (10-4), the first island (9-1), the second island (9-2), the third island (9-3) and the fourth island (9-4) are equal and are all 140um to 200 um.
7. The piezoresistive pressure sensor chip having a stress concentrating structure according to claim 1, wherein said wheatstone bridge is a half-open loop wheatstone bridge, and an open loop of said loop wheatstone bridge is used for connecting with an external resistor.
8. A method for preparing the piezoresistive pressure sensor chip with the stress concentration structure according to claim 1, comprising the following steps:
step 1, cleaning an SOI silicon wafer, wherein the SOI silicon wafer consists of an upper monocrystalline silicon layer (11), a silicon dioxide buried layer (12) and a lower monocrystalline silicon layer (13);
step 2, carrying out double-sided high-temperature oxidation on the cleaned SOI silicon wafer, forming a first silicon dioxide layer (14) on the upper surface of the SOI silicon wafer, and forming a second silicon dioxide layer (17) on the lower surface of the SOI silicon wafer;
step 3, etching silicon dioxide in a piezoresistor area in the first silicon dioxide layer (14) by using a piezoresistor plate, carrying out boron ion light doping to form a first piezoresistor strip (4-1), a second piezoresistor strip (4-2), a third piezoresistor strip (4-3) and a fourth piezoresistor strip (4-4), and then annealing;
step 4, depositing a third silicon dioxide layer on the front surface of the product obtained in the step 3, carrying out photoetching and reactive ion etching by using an ohmic contact plate to realize patterning of the first silicon dioxide layer (14) and the third silicon dioxide layer, removing silicon dioxide of an ohmic contact area (15) in the first silicon dioxide layer (14) and the third silicon dioxide layer, using the silicon dioxide layers of the rest areas as masks, and then carrying out boron ion heavy doping to form the ohmic contact area (15);
step 5, photoetching the shape of the metal lead on the front surface of the product obtained in the step 4 by using a metal lead plate, sputtering a metal layer to form the metal lead and a bonding pad, and then carrying out alloying treatment;
6, photoetching the front surface of the SOI sheet obtained in the step 5 to form a first stress concentration groove (2-1), a second stress concentration groove (2-2), a third stress concentration groove (2-3), a fourth stress concentration groove (2-4), a first stress adjusting groove (3-1), a second stress adjusting groove (3-2), a third stress adjusting groove (3-3), a fourth stress adjusting groove (3-4), a fifth stress adjusting groove (3-5), a sixth stress adjusting groove (3-6), a seventh stress adjusting groove (3-7) and an eighth stress adjusting groove (3-8);
step 7, carrying out photoetching on the back surface of the SOI sheet obtained in the step 5 by using a back cavity etching plate, and removing redundant silicon by using a silicon dioxide buried layer (12) in the SOI sheet as an etching stop layer in a dry method to form a back cavity (18), a first peninsula (10-1), a second peninsula (10-2), a third peninsula (10-3), a fourth peninsula (10-4), an island (9-1), a second island (9-2), a third island (9-3) and a fourth island (9-4), so as to obtain a matrix (1); the bottom surface of the back cavity (18) is the film (6);
step 8, etching the glass substrate (5) to form a groove (5-1);
and 9, bonding the base body (1) manufactured in the step 7 and the glass substrate (5) processed in the step 8 in a vacuum mode to obtain the ultra-low pressure sensor chip.
9. The method for manufacturing a piezoresistive pressure sensor chip having a stress concentration structure according to claim 8, wherein after step 4, the SOI wafer is annealed to make the impurity doping concentration of the ohmic contact region (15) more uniform.
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