CN112034204A - Linked contact capacitance type acceleration sensitive chip and manufacturing method thereof - Google Patents
Linked contact capacitance type acceleration sensitive chip and manufacturing method thereof Download PDFInfo
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- CN112034204A CN112034204A CN202010785862.5A CN202010785862A CN112034204A CN 112034204 A CN112034204 A CN 112034204A CN 202010785862 A CN202010785862 A CN 202010785862A CN 112034204 A CN112034204 A CN 112034204A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/125—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by capacitive pick-up
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00047—Cavities
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00055—Grooves
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/0802—Details
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P2015/0862—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with particular means being integrated into a MEMS accelerometer structure for providing particular additional functionalities to those of a spring mass system
Abstract
The invention discloses a linkage contact capacitance type acceleration sensitive chip and a manufacturing method thereof. The chip is manufactured by adopting silicon-on-insulator (SOI) and combining with silicon-silicon direct bonding technology, the Z axis is the sensitive direction of the chip, and the chip comprises a monocrystalline silicon substrate carved with a groove, a suspended movable lower polar plate, a silicon nitride dielectric layer, a sealed cavity, an upper polar plate and a metal layer. In an initial state, the interior of the cavity of the sensitive structure has air pressure difference with the outside, and the upper polar plate and the dielectric layer on the lower polar plate are in a contact state; when external acceleration acts on the sensitive structure, the contact area of the two polar plates changes, the lower polar plate is suspended and movable, the upper polar plate and the lower polar plate form a linkage effect, and the lower polar plate and an external circuit are connected through a pressure welding point to form a capacitance detection circuit, so that an acceleration signal is converted into a capacitance signal to be output. The linkage contact capacitance type acceleration sensitive chip has the advantages of good linearity, large linear measuring range, strong overload capacity, small cross coupling coefficient, high reliability, small temperature drift and the like.
Description
Technical Field
The invention mainly relates to a linkage contact capacitance type acceleration sensitive chip and a manufacturing method thereof, belonging to the field of Micro Electro Mechanical Systems (MEMS).
Background
With the development of the MEMS technology, accelerometers become indispensable key devices in various industries, and have been widely used in the fields of automotive electronics, industrial control, biomedicine, national defense, military industry, and the like. Compared with a piezoresistive acceleration sensor, the capacitive acceleration sensor has the advantages of high sensitivity, low power consumption, good temperature characteristic and the like, is more suitable for developing a high-precision acceleration sensor, and particularly has high importance in the research of the MEMS capacitive acceleration sensor at home and abroad under the background that the requirements on acceleration measurement precision and reliability are increasingly increased in the aspects of modern aerospace technology, modern national defense equipment and the like.
At present, the mainstream capacitive acceleration sensor usually adopts a comb-tooth type structure and a sandwich type structure. The two sensitive structures realize acceleration detection mainly by changing the distance between the electrode plates to cause capacitance change, the nonlinearity between input and output signals of the two sensitive structures is serious, the displacement of the mass block is generally required to be controlled to obtain a relatively linear working area, but the range is smaller, the linearity has space for further improving, and the defect of small capacitance change exists, so that the two sensitive structures not only bring great difficulty to a subsequent processing circuit, but also influence the precision and the sensitivity of a device. In order to improve the performance of the capacitance type acceleration sensor, the invention provides a contact capacitance type acceleration sensitive structure, which realizes acceleration measurement by changing the mutual contact area of an upper polar plate and a lower polar plate. The structure is characterized in that: the metal layer is manufactured on the upper polar plate to increase the mass of the upper polar plate, so that the deformation of the upper polar plate is more sensitive to the external acceleration effect, and the lower polar plate is suspended and movable in the structure; when the sensitive structure is not subjected to the acceleration, the upper polar plate and the lower polar plate are already in a mutual contact state due to the fact that the air pressure difference exists between the inside of the sensitive structure cavity and the outside; when acceleration acts on the sensitive structure, the contact area between the upper polar plate and the lower polar plate can be changed, the output capacitor mainly takes the contact capacitor between the two polar plates as a main part, in the process, the lower polar plate also deforms along with the movement of the upper polar plate and plays a role in regulation to form a linkage effect, so that the contact area is changed at a rate which is approximately constant, the output capacitance value can be approximately linear with the acceleration change, the sensor shows superior linearity and higher output capacitance value, and the problems of poor linearity, small capacitance variation and the like between the input and the output of a common capacitive acceleration sensor are solved.
The structure can be realized by adopting SOI material and utilizing the methods of dry etching and silicon-silicon direct bonding technology. The precision of the thickness of the top silicon film of the SOI silicon chip can be controlled within a few nanometers, so that the precision of the thickness of the pole plate can be obviously improved by adopting the silicon film of the SOI material to prepare the upper pole plate and the lower pole plate with sensitive structures. The silicon-silicon direct bonding technology is a method for tightly combining a silicon wafer with materials such as the silicon wafer, an oxide wafer and the like through chemical and physical effects, can realize perfect transfer of a top monocrystalline silicon film of an SOI silicon wafer, enables the manufacturing process of an upper polar plate and a lower polar plate to be more convenient to control and easy to realize, and can accurately set the internal air pressure of a sensitive structure cavity by controlling the air pressure of a bonding cavity.
Under the background of the research, the invention provides a linkage contact capacitance type acceleration sensitive chip and a manufacturing method thereof.
Disclosure of Invention
The purpose of the invention is as follows:
the invention relates to a linkage contact capacitance type acceleration sensitive chip and a manufacturing method thereof, in particular to an acceleration sensitive chip and a manufacturing method thereof shown in the attached drawing. The purpose is to improve the linearity, sensitivity and overload capacity of the MEMS capacitive acceleration sensor, enlarge the range of the linear region, make the manufacturing process of the chip easier to control and realize, reduce the chip area and reduce the cost.
The invention is realized by the following technical scheme:
a linkage contact capacitance type acceleration sensitive chip and a manufacturing method thereof are characterized in that: the chip comprises a monocrystalline silicon substrate etched with a groove, a lower polar plate positioned on the substrate, a dielectric layer on the lower polar plate, an upper polar plate, a sealed cavity formed by the upper polar plate and the groove of the substrate, and a metal layer on the upper polar plate; the upper and lower electrode plates are connected with an external circuit through a welding point to form an acceleration detection circuit, and the acceleration signal is converted into a capacitance signal to be output.
The upper polar plate and the substrate groove form a sealed cavity, the lower polar plate is positioned between the upper polar plate and the groove on the substrate and is suspended relative to the silicon substrate, and the suspension height is determined by the etching depth of the groove on the substrate.
The inside of the sealed cavity has a pressure difference with the outside, when the sensitive chip is not subjected to acceleration, the upper polar plate and the dielectric layer on the lower polar plate are already in a contact state to a certain degree, when the sensitive chip is subjected to the external acceleration, the contact area between the two polar plates is changed, the lower polar plate deforms along with the deformation of the upper polar plate, the two polar plates form a linkage effect, and the dielectric layers on the upper polar plate and the lower polar plate are always in the contact state within a range.
The lower polar plate is made of a silicon film on a first SOI substrate (A), one side of the silicon film of the first SOI substrate (A) is bonded with a substrate silicon wafer etched with a groove through a silicon-silicon direct bonding technology, and the silicon substrate and an oxide layer of the original SOI substrate (A) are removed, so that the lower polar plate is manufactured.
The upper polar plate is made of a silicon film on a second SOI substrate (B), one side of the silicon film of the second SOI substrate (B) is bonded with a substrate silicon wafer which is provided with a suspended lower polar plate and is etched with a cavity through a silicon-silicon direct bonding technology, the substrate and the oxide layer of the original SOI substrate (B) are removed, and the manufacturing of the upper polar plate and the sealing of the cavity are completed.
When the silicon-silicon direct bonding technology is used for manufacturing the upper polar plate, the air pressure difference value between the inside of the sealed cavity and the outside is set by controlling the air pressure of the bonding cavity of the bonding equipment.
A metal layer is formed on the upper plate.
A dielectric layer is deposited on the lower polar plate, and a through hole is formed in the dielectric layer.
A linkage contact capacitance type acceleration sensitive chip and a manufacturing method thereof are disclosed, the main process steps are as follows:
(1) etching the monocrystalline silicon substrate to form a groove, as shown in FIG. 4;
(2) thermally oxidizing a layer of silicon dioxide on the monocrystalline silicon substrate with the groove etched in the figure 4 to be used as an insulating layer, as shown in figure 5;
(3) bonding the silicon thin film side of the first SOI substrate (a) in fig. 3 and the silicon substrate with the recess in fig. 5 together, as shown in fig. 6;
(4) removing the substrate silicon of the original SOI substrate (A) in the structure of FIG. 6, as shown in FIG. 7;
(5) etching the oxide layer above the lower plate in the structure of fig. 7 to form a cavity structure, as shown in fig. 8;
(6) depositing a layer of silicon nitride as a dielectric layer in the structure of FIG. 8, as shown in FIG. 9;
(7) etching the silicon nitride dielectric layer in the structure of fig. 9, and etching the bottom plate to form a through hole, as shown in fig. 10(a) and (b);
(8) bonding the silicon thin film side of the second SOI substrate (B) in fig. 11 with the structure in fig. 10, as shown in fig. 12;
(9) removing the substrate silicon and oxide layer of the original SOI substrate (B) in the structure of FIG. 12, as shown in FIG. 13;
(10) sputtering a layer of metallic gold (Au) on the structure shown in fig. 13, as shown in fig. 14;
(11) etching the gold metal and the single crystal silicon layer in the structure of FIG. 14, and etching the surface of the oxide layer under the upper plate to form an upper plate and a metal layer structure, as shown in FIG. 15;
(12) etching the silicon oxide and the single crystal silicon layer in the structure of FIG. 15 to the silicon oxide surface under the bottom plate to form the bottom plate, as shown in FIG. 16;
(13) depositing a layer of silicon dioxide as an insulating passivation layer in the structure of fig. 16, as shown in fig. 17;
(14) etching electrode contact holes of the upper and lower electrode plates in the structure of FIG. 17, as shown in FIG. 18;
(15) a layer of metallic gold is sputtered in the structure of fig. 18 and gold wires are etched to form the acceleration sensitive structure shown in fig. 19.
Advantages and effects
The invention has the following advantages and beneficial effects:
the linkage contact capacitance type acceleration sensitive chip provided by the invention realizes acceleration measurement mainly by changing the contact area between the two polar plates, and designs the suspended movable lower polar plate in the structure, so that the upper polar plate and the lower polar plate are both movable structures, thereby improving the linearity and enlarging the range of a linear region; in the manufacturing method, the dry etching can greatly reduce the technical difficulty in front pattern protection and can safely finish the manufacture of the groove and the cavity; the precision of the thickness of the top silicon film of the SOI substrate can be controlled within a few nanometers, so that the precision of the thickness of the pole plate can be obviously improved by adopting the silicon film of the SOI material to prepare the upper pole plate and the lower pole plate with sensitive structures; the silicon-silicon direct bonding technology can realize perfect transfer of the top monocrystalline silicon film of the SOI substrate, so that the manufacturing process of the bipolar plate is easier to control and realize, and the internal air pressure of the sensitive structure cavity can be accurately set by controlling the air pressure of the bonding cavity.
Drawings
FIG. 1 is a top view of a chip of the present invention.
FIG. 2 is a schematic cross-sectional view of the AA' of the chip of the present invention.
Fig. 3 is a schematic cross-sectional view of a first SOI substrate (a) used in the chip processing of the present invention.
FIG. 4 is a schematic cross-sectional view of AA' after etching a single crystal silicon substrate to form a recess during the chip processing of the present invention.
FIG. 5 is a schematic cross-sectional view of AA' after thermal oxidation of a grooved silicon substrate to form a layer of silicon dioxide during chip processing according to the present invention.
Fig. 6 is a schematic cross-sectional view of the AA' of the present invention after bonding the silicon thin film side of the first SOI substrate (a) to the silicon substrate with the grooves during chip processing.
FIG. 7 is a schematic cross-sectional view of AA' after removal of the silicon substrate of the original SOI substrate (A) in the structure during chip processing according to the present invention.
FIG. 8 is a schematic cross-sectional view of the AA' of the present invention after etching the oxide layer on the lower plate in the chip processing to form the cavity structure.
FIG. 9 is a schematic cross-sectional view of AA' after a silicon nitride dielectric layer is deposited during the chip processing of the present invention.
FIG. 10(a) is a schematic cross-sectional view of the AA' after etching the silicon nitride dielectric layer and the through-hole of the bottom plate in the chip processing process of the present invention; FIG. 10(b) is a top view of the silicon nitride dielectric layer and the bottom plate via hole etched during the chip processing process of the present invention.
Fig. 11 is a schematic cross-sectional view of a second SOI substrate (B) used in the chip processing of the present invention.
Fig. 12 is a schematic cross-sectional view AA' after the silicon film side of the second SOI substrate (B) and the substrate are silicon bonded together during the chip processing of the present invention.
FIG. 13 is a schematic cross-sectional view of AA' after removal of the silicon and oxide layers of the original SOI substrate (B) in the structure during chip processing according to the present invention.
FIG. 14 is a cross-sectional view of AA' after sputtering a layer of gold (Au) on the structure during the chip processing of the present invention.
FIG. 15 is a schematic cross-sectional view of the AA' of the present invention after etching the gold metal and the monocrystalline silicon layer above the silicon wafer to form the top plate during the chip processing.
FIG. 16 is a schematic cross-sectional view of the AA' of the present invention after etching the silicon oxide and monocrystalline silicon layers above the silicon wafer to form the bottom plate during the chip processing.
FIG. 17 is a schematic cross-sectional view of AA' after a layer of silicon dioxide has been deposited as an insulating passivation layer during the fabrication of a chip according to the present invention.
FIG. 18 is a schematic cross-sectional view of AA' after etching an electrode contact hole during the chip processing of the present invention.
FIG. 19 is a schematic cross-sectional view of AA' after a layer of gold is sputtered and gold leads are etched during the chip processing of the present invention.
FIG. 20 is an output characteristic curve of an acceleration sensitive chip with a designed range of 30000g in the example.
Description of reference numerals:
1. the structure comprises a substrate silicon chip, 2. a lower polar plate, 3. a dielectric layer, 4. an upper polar plate, 5. a cavity, 6. gold and 7. a through hole.
The four squares in the lower part of the figure indicate the material represented by the pattern of different colors.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
the invention provides a linkage contact capacitance type acceleration sensitive chip and a manufacturing method thereof, and relates to a manufacturing method of an acceleration sensitive chip or a similar sensitive chip shown in the attached drawing of the invention. The method is characterized in that: the chip comprises a monocrystalline silicon substrate 1 etched with a groove, a lower polar plate 2 positioned on the substrate 1, a dielectric layer 3 on the lower polar plate 2, an upper polar plate 4, a sealed cavity 5 formed by the upper polar plate 4 and the groove of the substrate, and a metal layer 6 on the upper polar plate; the upper and lower electrode plates are connected with an external circuit through a welding point to form an acceleration detection circuit, and the acceleration signal is converted into a capacitance signal to be output.
The upper polar plate 4 and the substrate groove form a sealed cavity 5, the lower polar plate 2 is positioned between the upper polar plate 4 and the groove on the substrate 1 and is suspended relative to the silicon substrate 1, and the suspension height is determined by the etching depth of the groove on the substrate.
The inside of the sealed cavity 5 has a pressure difference with the outside, when the sensitive chip is not subjected to acceleration, the upper polar plate 4 and the dielectric layer 3 on the lower polar plate 2 are already in a contact state to a certain degree, when the sensitive chip is subjected to the external acceleration, the contact area between the two polar plates changes, the lower polar plate 2 deforms along with the deformation of the upper polar plate 4, the two polar plates form a linkage effect, and the upper polar plate 4 and the dielectric layer 3 on the lower polar plate 2 are always in the contact state within a measuring range.
The lower polar plate 2 is made of a silicon film on a first SOI substrate (A), one side of the silicon film of the first SOI substrate (A) is bonded with a substrate silicon wafer 1 etched with a groove through a silicon-silicon direct bonding technology, and the silicon substrate and an oxide layer of the original SOI substrate (A) are removed, so that the lower polar plate 2 is manufactured.
The upper polar plate 4 is made of a silicon film on a second SOI substrate (B), one side of the silicon film of the second SOI substrate (B) is bonded with a substrate silicon wafer 1 which is provided with a suspended lower polar plate 2 and is etched with a cavity 5 through a silicon-silicon direct bonding technology, the substrate and an oxide layer of the original SOI substrate (B) are removed, and the manufacture of the upper polar plate 4 and the sealing of the cavity 5 are completed.
When the upper polar plate 4 is manufactured by using the silicon-silicon direct bonding technology, the air pressure difference value between the inside of the sealed cavity 5 and the outside is set by controlling the air pressure of the bonding cavity of the bonding equipment.
A metal layer 6 is formed on the upper plate 4.
A dielectric layer 3 is deposited on the lower plate 2 and is provided with a through hole 7.
The design principle of the invention is as follows:
the invention provides a linkage contact capacitance type acceleration sensitive structure which mainly comprises a silicon substrate, a lower polar plate, a dielectric layer, an upper polar plate and a metal layer. In the structure, an upper polar plate and a lower polar plate are both movable structures, the lower polar plate is arranged on a monocrystalline silicon substrate with a groove etched in advance and can move in the air relative to the monocrystalline silicon substrate, and a silicon nitride dielectric layer is arranged above the lower polar plate and is etched with a through hole; a sealed cavity is formed between the upper polar plate and the groove on the substrate, the inside of the cavity has air pressure difference with the outside, and the metal layer is manufactured on the upper polar plate to increase the mass of the upper polar plate, so that the deformation of the upper polar plate is more sensitive to the external acceleration; the two electrode plates are connected with an external circuit through pressure welding points, and acceleration signals are converted into capacitance signals to be output. The structure realizes acceleration measurement by changing the mutual contact area of the upper polar plate and the lower polar plate, and when the structure is not subjected to acceleration, the upper polar plate and the lower polar plate are already in a mutual contact state due to the fact that the pressure difference exists between the inside of a sensitive structure cavity and the outside; when acceleration acts on the sensitive structure, the contact area between the upper polar plate and the lower polar plate can be changed, the output capacitor mainly takes the contact capacitor between the two polar plates as a main part, in the process, the lower polar plate also deforms along with the movement of the upper polar plate and plays a role in regulation to form a linkage effect, so that the contact area is changed at a rate which is approximately constant, the output capacitance value can be approximately linear with the acceleration change, the sensor shows superior linearity and higher output capacitance value, and the problems of poor linearity, small capacitance variation and the like between the input and the output of a common capacitive acceleration sensor are solved.
The manufacturing method mainly utilizes MEMS technologies such as silicon-silicon direct bonding, dry etching and the like to manufacture the SOI substrate and the substrate silicon wafer into the linkage contact capacitance type acceleration sensitive chip. The groove on the substrate is made by dry etching, and the depth of the groove is determined by the suspension height of the designed lower polar plate; the upper polar plate and the lower polar plate are both made by combining a silicon film of an SOI substrate with a silicon-silicon direct bonding technology, when the upper polar plate is manufactured, the air pressure of a bonding cavity of bonding equipment is controlled to set the air pressure inside the cavity of the sensitive structure, and the air pressure difference between the inside of the cavity and the outside is ensured, so that when the sensitive chip is not subjected to acceleration, the upper polar plate and the dielectric layer on the lower polar plate are already in a contact state to a certain extent.
Example (b):
the design range of the linked contact capacitance type acceleration sensitive structure provided by the invention is 30000g (g is 9.8 m/s)2) The acceleration sensitive chip has the following structural parameters:
the upper polar plate and the lower polar plate are in a circular shape, the radius of the upper polar plate and the radius of the lower polar plate are both 400 micrometers, the thickness of the upper polar plate is 5 micrometers, the thickness of the lower polar plate is 10 micrometers, the suspension height of the lower polar plate relative to the silicon substrate is 5 micrometers, the thickness of the silicon nitride dielectric layer is 50nm, the distance between the upper polar plate and the dielectric layer is 0.5 micrometer, the thickness of metal gold (Au) is 5 micrometers, and the air pressure inside the cavity is 81.5 kPa.
For the acceleration sensitive chip with the above size parameters, a finite element software is used for simulation analysis, and an output characteristic curve is obtained and is shown in fig. 20. In fig. 20, point a is an initial state of the sensor chip, where the upper plate is already in contact with the dielectric layer on the lower plate; when the sensitive chip is subjected to the action of external acceleration, the sensitive chip works in a linear region range (point B-point C), a superior linear relation is shown between output capacitance and acceleration, the nonlinearity is about 0.87% FS, the capacitance variation in a full scale is about 3.23pF, 15.4% of an initial capacitance value (21pF) is reached, the natural frequency is about 94264Hz, overload reaches 36 times of the range, and the cross coupling coefficient is less than 1%.
The manufacturing method of the linkage contact capacitance type acceleration sensitive chip comprises the following steps:
the first SOI substrate (a) used is shown in fig. 3, and its specifications are as follows:
thickness of the top silicon film: 10 μm, doping type: p-type, resistivity: 0.01-0.02 omega cm; thickness of an oxide layer: 0.5 μm; thickness of substrate silicon: 500 μm;
the second SOI substrate (B) used is shown in fig. 11, and its specifications are as follows:
thickness of the top silicon film: 5 μm, doping type: p-type, resistivity: 0.01-0.02 omega cm; thickness of an oxide layer: 0.5 μm; thickness of substrate silicon: 500 μm;
(1) etching the monocrystalline silicon substrate to form a groove with a depth of 5 μm, as shown in FIG. 4;
(2) thermally oxidizing the silicon substrate with the groove etched in the figure 4 to form a layer of SiO with the thickness of 1 micron2As an insulating layer, as shown in fig. 5;
(3) bonding the silicon thin film side of the first SOI substrate (a) in fig. 3 and the silicon substrate with the recess in fig. 5 together, as shown in fig. 6;
(4) removing the substrate silicon of the original SOI substrate (A) in the structure of FIG. 6, as shown in FIG. 7;
(5) etching the oxide layer above the lower plate in the structure of fig. 7 to form a cavity structure, as shown in fig. 8;
(6) depositing a low-stress silicon nitride dielectric layer with a thickness of 50nm by low-pressure chemical vapor deposition (LPCVD) as shown in FIG. 9;
(7) etching the silicon nitride dielectric layer in the structure of fig. 9, and etching the bottom plate to form a through hole, as shown in fig. 10(a) and (b);
(8) setting the gas pressure in the bonding chamber of the bonding apparatus to 81.5kPa, bonding the silicon thin film side of the second SOI substrate (B) in fig. 11 and the structure in fig. 10 together, as shown in fig. 12;
(9) removing the silicon and oxide layers of the original SOI substrate (B) in the structure of FIG. 12, as shown in FIG. 13;
(10) sputtering a layer of metal gold (Au) 5 μm thick on the structure shown in fig. 13, as shown in fig. 14;
(11) etching the gold metal and the single crystal silicon layer in the structure of FIG. 14, and etching the surface of the oxide layer under the upper plate to form an upper plate and a metal layer structure, as shown in FIG. 15;
(12) etching the silicon oxide and the single crystal silicon layer in the structure of FIG. 15 to the silicon oxide surface under the bottom plate to form the bottom plate, as shown in FIG. 16;
(13) depositing a layer of 0.5 μm thick silicon dioxide as an insulating passivation layer in the structure of fig. 16, as shown in fig. 17;
(14) etching electrode contact holes of the upper and lower electrode plates in the structure of FIG. 17, as shown in FIG. 18;
(15) a layer of 1 μm thick metal gold was sputtered in the structure of fig. 18 and the gold wire was etched to form the acceleration sensitive structure shown in fig. 19.
The linkage contact capacitance type acceleration sensitive chip can be widely applied to the measurement of acceleration signals in a plurality of fields such as industrial control, automotive electronics, aerospace, national defense and military industry and the like.
Claims (9)
1. A linkage contact capacitance type acceleration sensitive chip and a manufacturing method thereof are characterized in that: the chip comprises a monocrystalline silicon substrate (1) etched with a groove, a lower polar plate (2) positioned on the substrate (1), a dielectric layer (3) on the lower polar plate (2), an upper polar plate (4), a sealed cavity (5) formed by the upper polar plate (4) and the groove of the substrate, and a metal layer (6) on the upper polar plate; the upper and lower electrode plates are connected with an external circuit through a welding point to form an acceleration detection circuit, and the acceleration signal is converted into a capacitance signal to be output.
2. The chip of claim 1, wherein the chip comprises: the upper polar plate (4) and the substrate groove form a sealed cavity (5), the lower polar plate (2) is positioned between the upper polar plate (4) and the groove on the substrate (1) and is suspended relative to the silicon substrate (1), and the suspension height is determined by the etching depth of the groove on the substrate.
3. The chip of claim 1, wherein the chip comprises: the inside of the sealed cavity (5) has a pressure difference with the outside, when the sensitive chip is not subjected to acceleration, the upper polar plate (4) and the dielectric layer (3) on the lower polar plate (2) are already in a contact state to a certain degree, when the sensitive chip is subjected to the action of the external acceleration, the contact area between the two polar plates is changed, the lower polar plate (2) deforms along with the deformation of the upper polar plate (4), the upper polar plate and the lower polar plate form a linkage effect, and in a measuring range, the upper polar plate (4) and the dielectric layer (3) on the lower polar plate (2) are always in the contact state.
4. The chip of claim 1, wherein the chip comprises: the lower polar plate (2) is made of a silicon film on a first SOI substrate (A), one side of the silicon film of the first SOI substrate (A) is bonded with a substrate silicon wafer (1) etched with a groove through a silicon-silicon direct bonding technology, and the silicon substrate and an oxide layer of the original SOI substrate (A) are removed, so that the lower polar plate (2) is manufactured.
5. The chip of claim 1, wherein the chip comprises: the upper polar plate (4) is made of a silicon film on a second SOI substrate (B), one side of the silicon film of the second SOI substrate (B) is bonded with a substrate silicon wafer (1) which is provided with a suspended lower polar plate (2) and is etched with a cavity (5) through a silicon-silicon direct bonding technology, the substrate and an oxide layer of the original SOI substrate (B) are removed, and the manufacture of the upper polar plate (4) and the sealing of the cavity (5) are completed.
6. The chip of claim 1, wherein the chip comprises: when the upper polar plate (4) is manufactured by using a silicon-silicon direct bonding technology, the air pressure difference between the inside of the sealed cavity (5) and the outside is set by controlling the air pressure of a bonding cavity of bonding equipment.
7. The chip of claim 1, wherein the chip comprises: a metal layer (6) is formed on the upper electrode plate (4).
8. The chip of claim 1, wherein the chip comprises: a dielectric layer (3) is deposited on the lower polar plate (2), and a through hole (7) is arranged.
9. The coupled contact capacitive acceleration sensitive chip and the manufacturing method thereof according to claim 1, wherein the main process steps are as follows:
(1) etching the monocrystalline silicon substrate to form a groove, as shown in FIG. 4;
(2) thermally oxidizing a layer of silicon dioxide on the monocrystalline silicon substrate with the groove etched in the figure 4 to be used as an insulating layer, as shown in figure 5;
(3) bonding the silicon thin film side of the first SOI substrate (a) in fig. 3 and the silicon substrate with the recess in fig. 5 together, as shown in fig. 6;
(4) removing the substrate silicon of the original SOI substrate (A) in the structure of FIG. 6, as shown in FIG. 7;
(5) etching the oxide layer above the lower plate in the structure of fig. 7 to form a cavity structure, as shown in fig. 8;
(6) depositing a layer of silicon nitride as a dielectric layer in the structure of FIG. 8, as shown in FIG. 9;
(7) etching the silicon nitride dielectric layer in the structure of fig. 9, and etching the bottom plate to form a through hole, as shown in fig. 10(a) and (b);
(8) bonding the silicon thin film side of the second SOI substrate (B) in fig. 11 with the structure in fig. 10, as shown in fig. 12;
(9) removing the substrate silicon and oxide layer of the original SOI substrate (B) in the structure of FIG. 12, as shown in FIG. 13;
(10) sputtering a layer of metallic gold (Au) on the structure shown in fig. 13, as shown in fig. 14;
(11) etching the gold metal and the single crystal silicon layer in the structure of FIG. 14, and etching the surface of the oxide layer under the upper plate to form an upper plate and a metal layer structure, as shown in FIG. 15;
(12) etching the silicon oxide and the single crystal silicon layer in the structure of FIG. 15 to the silicon oxide surface under the bottom plate to form the bottom plate, as shown in FIG. 16;
(13) depositing a layer of silicon dioxide as an insulating passivation layer in the structure of fig. 16, as shown in fig. 17;
(14) etching electrode contact holes of the upper and lower electrode plates in the structure of FIG. 17, as shown in FIG. 18;
(15) a layer of metallic gold is sputtered in the structure of fig. 18 and gold wires are etched to form the acceleration sensitive structure shown in fig. 19.
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