CN111490791A - Incremental successive approximation analog-to-digital converter - Google Patents
Incremental successive approximation analog-to-digital converter Download PDFInfo
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- CN111490791A CN111490791A CN202010399521.4A CN202010399521A CN111490791A CN 111490791 A CN111490791 A CN 111490791A CN 202010399521 A CN202010399521 A CN 202010399521A CN 111490791 A CN111490791 A CN 111490791A
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- H03M1/12—Analogue/digital converters
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- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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Abstract
The invention belongs to the technical field of data quantization processing in an integrated circuit, and discloses an incremental successive approximation analog-to-digital converter, which mainly comprises four parts, namely a digital-to-analog converter, a comparator, a digital logic control part and a dynamic capacitance matching decision module, wherein the four parts comprise: the digital-to-analog converter comprises 2M incremental capacitor arrays, and each incremental capacitor array is formed by 2N-1 capacitor component of equal size; the dynamic capacitance matching decision module is used for adjusting the turning sequence of a lower plate in the incremental capacitor array; in summary, in the present invention, the incremental capacitor array is used to replace the traditional monotonic binary capacitor array, so as to effectively reduce the number of capacitors required to be turned over during each sampling, thereby reducing the driving pressure of the comparator and reducing the power consumption of the whole converter; and the dynamic capacitance matching decision module enables the whole converter to form a dynamic structure, so that the problem of high-order capacitance mismatch can be solved in the data quantization processing of the whole converter.
Description
Technical Field
The invention belongs to the technical field of data quantization processing in an integrated circuit, and particularly relates to an incremental successive approximation analog-to-digital converter.
Background
Data quantization is an essential ring in the whole flow of data processing, and determines the quantity and data of the whole data circulation. Data quantization is how to accurately convert an analog signal into a digital signal, and a circuit for converting an analog signal into a digital signal is called an analog-to-digital converter. At present, the successive approximation type analog-to-digital converter has wide application due to good performance and simple realization.
In the prior art, a successive approximation analog-to-digital converter mainly comprises a digital-to-analog converter (ADC), a comparator and a digital logic control part, and the specific structural form of the successive approximation analog-to-digital converter is shown in fig. 1, and most of the corresponding digital-to-analog converters adopt a monotonic capacitor array (the overall accuracy of the digital-to-analog converter is N) shown in fig. 2. The working process of the conventional successive approximation analog-to-digital converter is as follows:
the method comprises the following steps: during sampling, the upper polar plates of the capacitor arrays 101 and 102 are switched on by the sampling switch in fig. 1, and the lower polar plates of the capacitor arrays are connected with reference voltage;
step two: after the comparison is started, the sampling switch is switched off, and according to the output of the comparator 103 and the control of the digital control circuit 104, the potential of the lower electrode plate of the capacitor of the positive end or negative end capacitor array is sequentially turned from high reference voltage to low reference voltage, so that the potential of the P end and the N end of the comparator are converged;
step three: and a digital output part in the analog-to-digital converter is used for obtaining the potential of the lower electrode plate of the capacitor and outputting the potential.
In summary, it can be seen from the above working process that the conventional successive approximation analog-to-digital converter has the following drawbacks:
(1) the overturning capacitance is more: the comparison process of the comparator 103 is a process of sequentially performing the step from the high reference voltage to the low reference voltage for all the capacitors, and needs to go through all the capacitors in the whole converter.
(2) The harmonic error is large: in the traditional monotonic capacitor array, each bit capacitor adopts a structure of reducing half bit by bit, so that the size of a high-order capacitor accounts for half of the total capacitor, the error caused by mismatch of the high-order capacitor is the largest at the moment, a harmonic error is generated, and the precision of an ADC (analog to digital converter) is reduced.
(3) The power consumption is large: the method comprises the following steps: the large number of the turning capacitors causes large power consumption of the capacitor driving circuit and the capacitors; the second is as follows: when the capacitor is turned over, the output voltage of the capacitor array exceeds the sampling voltage, and when the voltage exceeds the sampling voltage, the capacitor is turned over in the opposite direction to offset the exceeding voltage, so that unnecessary power consumption is generated.
Disclosure of Invention
In view of the above, an objective of the present invention is to provide an incremental successive approximation adc, so as to effectively solve the problems of high dynamic power consumption, large influence of capacitance mismatch, and large driving pressure of the comparator of the conventional successive approximation adc proposed in the background art.
In order to achieve the purpose, the invention provides the following technical scheme: an increment successive approximation analog-to-digital converter mainly comprises a digital-to-analog converter, a comparator, a digital logic control part and a dynamic capacitance matching decision module, wherein:
the digital-to-analog converter comprises an incremental capacitor array used for executing sampling in data quantization processing; during sampling, the upper plate of the incremental capacitor array is connected with the sampling switch, and the lower plate of the incremental capacitor array is connected with the high reference voltage;
the positive end and the negative end of the comparator are matched with the incremental capacitor array and used for comparing whether the potentials of the positive end and the negative end are converged; during comparison, the upper plate of the incremental capacitor array is disconnected from the sampling switch, and the lower plate of the incremental capacitor array is sequentially turned over from the high reference voltage to the low reference voltage;
the digital logic control part is connected to the output end of the comparator and executes corresponding operation according to the output structure of the comparator; when the potentials of the positive end and the negative end of the comparator are close to the same time, the digital-to-analog converter is controlled to fetch and output the potential of the lower polar plate of the capacitor; when the potentials of the positive end and the negative end of the comparator are not close to each other, feeding back to the comparator for re-comparison;
the dynamic capacitance matching decision module is used for adjusting the turning sequence of a lower plate in the incremental capacitor array; and during comparison, the turning of the lower-stage plate of the incremental capacitor array is executed according to the sequence adjusted by the dynamic capacitor matching decision module.
Preferably, the number of the incremental capacitor arrays in the digital-to-analog converter is 2M, and M is any positive integer from 1 to M.
Preferably, the positive terminal and the negative terminal of the comparator are respectively matched with different incremental capacitor arrays.
Preferably, each incremental capacitor array is 2N1 capacitors of the same size, and N is a positive integer from 1 to N.
Preferably, the digital-to-analog converter further comprises a digital output part, and the operations of the digital-to-analog converter for fetching and outputting the potential of the lower electrode plate of the capacitor are both completed by the digital output part.
Preferably, the adjustment period of the dynamic capacitance matching decision module to the flipping sequence of the lower plate in the incremental capacitor array is one sampling period.
Preferably, the adjustment time of the dynamic capacitance matching decision module to the flipping sequence of the lower plate in the incremental capacitor array is as follows: after the end of the previous sampling period and before the start of the next sampling period.
Preferably, when the dynamic capacitance matching decision module adjusts the turning sequence of the lower plate in the incremental capacitor array, the obtained turning sequence of the same lower plate in the same incremental capacitor array sequentially circulates under a plurality of sampling periods.
Compared with the prior art, the invention has the following beneficial effects:
in the invention, a new digital-to-analog converter is arranged, and particularly, an incremental capacitor array is used for replacing a traditional monotone capacitor array so as to replace a traditional capacitor structure which is halved bit by bit into a unit structure, so that the quantity of capacitors which need to be turned over each time of sampling can be effectively reduced in the data quantization processing of the whole converter, the driving pressure of a comparator is reduced, and the power consumption of the whole converter is reduced.
In the invention, a dynamic capacitance matching decision module is also arranged, so that the whole converter forms a dynamic structure; specifically, the dynamic capacitance matching decision module is used for changing the turning sequence of the capacitors in the incremental capacitor array, so that the order of turning the capacitors in each sampling period forms a cycle, the problem of high-order capacitor mismatch is effectively solved, and the precision of the whole digital-to-analog converter is greatly improved.
In addition, compared with the traditional structure, the dynamic structure provided by the invention has higher signal-to-noise ratio and linearity under the same mismatch capacitance, thereby effectively improving the precision of the whole converter.
In summary, the incremental successive approximation analog-to-digital converter provided by the invention has the advantages of low power consumption requirement, high tolerance degree to capacitor mismatch and low requirement on the driving capability of a comparator.
Drawings
Fig. 1 is a schematic structural diagram of a conventional successive approximation analog-to-digital converter;
FIG. 2 is a schematic diagram of a monotonic capacitor array employed in a conventional successive approximation analog-to-digital converter;
FIG. 3 is a schematic diagram of an incremental successive approximation analog-to-digital converter according to the present invention;
FIG. 4 is a schematic diagram of an incremental capacitor array employed in the incremental successive approximation analog-to-digital converter provided by the present invention;
FIG. 5 is a flow chart of dynamic capacitance matching decision module performing incremental capacitor array lower level panel flipping sequence adjustment over multiple sampling periods;
FIG. 6 is a diagram illustrating power consumption of an incremental successive approximation analog-to-digital converter over a plurality of sampling periods;
FIG. 7 is a graph comparing the number of flip capacitors generated by a converter provided by the present invention with the number of flip capacitors of a prior art converter over a plurality of sampling periods;
FIG. 8 is a graph of a signal-to-noise ratio spectrum of a conventional successive approximation analog-to-digital converter;
FIG. 9 is a graph of the signal-to-noise ratio spectrum of the incremental successive approximation analog-to-digital converter provided by the present invention;
FIG. 10 is a differential and integral non-linear diagram of a conventional successive approximation analog-to-digital converter;
FIG. 11 is a differential, integral non-linear plot of an incremental successive approximation analog to digital converter provided by the present invention;
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The present invention provides an incremental successive approximation analog-to-digital converter, which has a specific structure shown in fig. 3, and mainly includes four parts, namely, a digital-to-analog converter, a comparator (305 shown in fig. 3), a digital logic control part (306 shown in fig. 3), and a dynamic capacitance matching decision module (303 and 304 shown in fig. 3), based on the four parts mentioned above, the flow of the overall converter when performing data quantization processing is as follows (taking data quantization processing in one sampling period as an example):
the method comprises the following steps: the digital-to-analog converter comprises incremental capacitor arrays (301 and 302 shown in fig. 3) for performing sampling in data quantization processing; specifically, during sampling, an upper-stage plate of the incremental capacitor array is connected with a sampling switch, and a lower-stage plate of the incremental capacitor array is connected with a high reference voltage;
specifically, in the digital-to-analog converter, 2M incremental capacitor arrays are required to be provided, and M is any positive integer from 1 to M.
With respect to incremental capacitor arraysStructure, each incremental capacitor array is composed of 2N1 capacitors with the same size, wherein N is any positive integer from 1 to N; the specific form of the incremental capacitor array is shown in fig. 4, and it can be seen from the figure that the total accuracy of the whole digital-to-analog converter is N1+ N2 … … + NX.
As can be seen from fig. 3, the sampling switches respectively include a positive input switch and a negative input switch, and are respectively connected to the upper boards of two different incremental capacitor arrays.
Step two: performs comparison in cooperation with the comparator 305 and the digital logic control section 306; specifically, during comparison, the upper plate of the incremental capacitor array is disconnected from the sampling switch, the lower plate of the incremental capacitor array is sequentially flipped from a high reference voltage to a low reference voltage, and the comparator 305 compares whether the potentials of the positive terminal and the negative terminal of the incremental capacitor array are the same in the capacitor flipping process;
specifically, this step is a loop step, the comparison result of the comparator 305 is input to the digital logic control portion 306, if yes, the step three is entered, and the loop is ended; if not, the feedback is sent to the comparator 305, and the comparison is performed again to execute a loop;
for turning over the lower plates of the incremental capacitor array, taking the same incremental capacitor array as an example, the lower plates of the capacitors are turned over one by one from a high reference voltage to a low reference voltage, so that the potentials of the positive terminal and the negative terminal of the comparator 305 converge, and in the process, if the potentials of the positive terminal and the negative terminal do not converge, the next capacitor in the incremental capacitor array is continuously turned over, that is, the cyclic comparison is continuously performed; the same applies to the cyclic principle for a plurality of incremental capacitor arrays.
In addition, as can be seen from fig. 3, the positive terminal and the negative terminal of the comparator 305 should correspond to different incremental capacitor arrays.
Step three: when the positive terminal and the negative terminal of the comparator 305 become close, the digital logic control portion 306 controls the digital-to-analog converter to fetch and output the capacitor bottom plate potential.
Specifically, the digital-to-analog converter further comprises a digital output part, and the operations of taking and outputting the potential of the lower electrode plate of the capacitor by the digital-to-analog converter are completed by the digital output part.
Step four: based on the first step to the third step, the whole converter completes one sampling period, and before the next sampling period starts, the dynamic capacitance matching decision modules (303 and 304) are adopted to respectively adjust the overturning sequence of the capacitance in the incremental capacitor arrays (301 and 302);
specifically, in this step, the principle of adjusting the capacitance inversion sequence by the dynamic capacitance matching decision module is shown in fig. 5: from the figure, it can be seen (taking 3 capacitors as an example):
the capacitance inversion sequence in the sampling period 1 is (NX-1), (2), (1);
the capacitance inversion sequence in the sampling period 2 is (1), (NX-1), (2);
the capacitance inversion sequence in the sampling period 3 is (2), (1), (NX-1);
in summary, the inversion sequence for the same capacitor (lower plate) in the incremental capacitor array forms a cycle over multiple cycles.
For the converter disclosed above, tests of energy consumption, number of capacitance flips, signal to noise ratio and linearity were performed, and compared with existing converters:
(1) energy consumption, according to experimental tests, a comparison graph shown in fig. 6 is obtained, wherein a corresponds to a conventional converter, and b corresponds to a converter provided by the present invention;
as can be seen, compared to the conventional converter, the dynamic power consumption provided by the present invention is less with the same accuracy; specifically, the average power consumption is 88% of the power consumption of the conventional structure.
(2) The number of capacitor flips, according to experimental tests, a comparison graph shown in fig. 7 is obtained, where c corresponds to the existing converter and d corresponds to the converter provided by the present invention;
as can be seen, the average number of unit capacitors flipped by the comparator provided by the present invention is 75% of the number of capacitor flips in the conventional converter.
(3) Signal-to-noise ratio, according to experimental tests, signal-to-noise ratio spectrograms shown in fig. 8 and fig. 9 are respectively obtained, fig. 8 corresponds to a conventional converter, fig. 9 corresponds to a converter provided by the present invention, and in combination with comparison, under the same mismatch capacitance (when the standard deviation of capacitance mismatch takes 0.1), the signal-to-noise ratio of the converter provided by the present invention is 2.89dB better than that of the conventional converter.
(4) Linearity, according to experimental tests, differential and integral non-linear graphs shown in fig. 10 and fig. 11 are obtained respectively, fig. 10 corresponds to a conventional converter, fig. 11 corresponds to a converter provided by the present invention, and in combination with comparison, under the same mismatch capacitance (when the standard deviation of the capacitance mismatch is 0.1), the non-linearity of the converter provided by the present invention is significantly reduced.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. An increment successive approximation analog-to-digital converter is characterized by mainly comprising a digital-to-analog converter, a comparator, a digital logic control part and a dynamic capacitance matching decision module, wherein:
the digital-to-analog converter comprises an incremental capacitor array used for executing sampling in data quantization processing; during sampling, the upper plate of the incremental capacitor array is connected with the sampling switch, and the lower plate of the incremental capacitor array is connected with the high reference voltage;
the positive end and the negative end of the comparator are matched with the incremental capacitor array and used for comparing whether the potentials of the positive end and the negative end are converged; during comparison, the upper plate of the incremental capacitor array is disconnected from the sampling switch, and the lower plate of the incremental capacitor array is sequentially turned over from the high reference voltage to the low reference voltage;
the digital logic control part is connected to the output end of the comparator and executes corresponding operation according to the output structure of the comparator; when the potentials of the positive end and the negative end of the comparator are close to the same time, the digital-to-analog converter is controlled to fetch and output the potential of the lower polar plate of the capacitor; when the potentials of the positive end and the negative end of the comparator are not close to each other, feeding back to the comparator for re-comparison;
the dynamic capacitance matching decision module is used for adjusting the turning sequence of a lower plate in the incremental capacitor array; and during comparison, the turning of the lower-stage plate of the incremental capacitor array is executed according to the sequence adjusted by the dynamic capacitor matching decision module.
2. The incremental successive approximation analog-to-digital converter of claim 1, wherein: the number of the incremental capacitor arrays in the digital-to-analog converter is 2M, and M is any positive integer from 1 to M.
3. The incremental successive approximation analog-to-digital converter of claim 2, wherein: and the positive end and the negative end of the comparator are respectively matched with different incremental capacitor arrays.
4. A delta successive approximation analog-to-digital converter as claimed in claim 2 or 3, characterized in that: each incremental capacitor array is composed of 2N1 capacitors of the same size, and N is a positive integer from 1 to N.
5. The incremental successive approximation analog-to-digital converter of claim 1, wherein: the digital-to-analog converter also comprises a digital output part, and the operations of taking and outputting the potential of the lower electrode plate of the capacitor by the digital-to-analog converter are completed by the digital output part.
6. The incremental successive approximation analog-to-digital converter of claim 2, wherein: and the dynamic capacitance matching decision module adjusts the turning sequence of the lower plate in each incremental capacitor array into a sampling period.
7. The incremental successive approximation analog-to-digital converter according to claim 6, wherein the dynamic capacitance matching decision module adjusts the flipping sequence of the lower plate in the incremental capacitor array by the following time: after the end of the previous sampling period and before the start of the next sampling period.
8. An incremental successive approximation analog-to-digital converter as claimed in claim 6 or 7, characterized in that: and when the dynamic capacitance matching decision module adjusts the turning sequence of the lower plate in the incremental capacitor array, the obtained turning sequence of the same lower plate in the same incremental capacitor array is sequentially circulated in a plurality of sampling periods.
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