CN111490058A - Semiconductor assembly and its manufacturing method - Google Patents

Abstract

The invention discloses a semiconductor assembly and a manufacturing method thereof. The semiconductor component comprises a substrate, a first doping area, a plurality of second doping areas and a plurality of photodiodes, wherein the first doping area, the plurality of second doping areas and the plurality of photodiodes are positioned in the substrate, and the semiconductor component comprises a plurality of color filter patterns arranged on the substrate. The substrate has a first conductivity type, and the first doped region and the second doped region have a second conductivity type. The photodiode extends from the top surface of the substrate to the inside. The color filter patterns are longitudinally overlapped with the photodiodes respectively. The plurality of second doped regions are in contact with the first doped regions and are located between the plurality of photodiodes and the first doped regions. The upper spacing regions are arranged between every two adjacent second doping regions, and the upper spacing regions are longitudinally overlapped with a plurality of color filtering patterns with the penetration wavelength of 620nm to 1000 nm.

Description

Semiconductor component and method of manufacturing the same

technical field

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to an image sensor and a manufacturing method thereof.

Background technique

An image sensor fabricated by a semiconductor fabrication process can be used to sense light incident on a substrate. Image sensors use an array of sensing units to receive light energy and convert it into digital signals. However, due to the different absorption depths of the substrate for different wavelengths of light, there will be different degrees of crosstalk between the sensing units. Specifically, the substrate needs to have a larger absorption depth for incident light with a longer wavelength to increase the absorption efficiency of photons. The carriers generated by the incident light deep in the substrate are far away from the electric field range of the sensing unit, and can diffuse to adjacent sensing units of other colors. As a result, the sensing units of various colors cannot absorb the carriers generated only by the corresponding color light, resulting in sensing errors.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor component and a manufacturing method thereof. The semiconductor device can be used as an image sensor and can reduce crosstalk between adjacent sensing units.

The semiconductor device of the present invention includes a substrate, a plurality of photodiodes, a plurality of color filter patterns, a first doped region, and a plurality of second doped regions. The substrate has a first conductivity type. A plurality of photodiodes extend from the top of the substrate toward the interior of the substrate. A plurality of color filter patterns are disposed on the substrate, and are respectively vertically overlapped with the plurality of photodiodes. The first doped region is disposed in the substrate and has the second conductivity type. A plurality of second doped regions are disposed in the substrate and have the second conductivity type. The plurality of second doping regions are in contact with the first doping regions and are located between the plurality of photodiodes and the first doping regions. There are upper spacers between two adjacent second doped regions, and the plurality of upper spacers are longitudinally overlapped in the plurality of color filter patterns and have a plurality of transmission wavelengths in the range of 620 nm to 1000 nm.

In some embodiments, the substrate includes a semiconductor substrate and an epitaxial layer. The epitaxial layer is disposed on the semiconductor substrate. The first doped region extends from the semiconductor substrate into the bottom of the epitaxial layer, and the plurality of second doped regions are located in the epitaxial layer.

In some embodiments, the first doped region extends continuously and vertically overlaps the plurality of second doped regions and the plurality of photodiodes.

In some embodiments, the top surface of the first doped region defines the bottom surface of the plurality of upper spacers.

In some embodiments, the number of the first doped regions is a majority. There are lower spacers between two adjacent first doped regions, and the plurality of lower spacers are respectively longitudinally connected to some of the plurality of upper spacers.

In some embodiments, the plurality of lower spacers vertically overlap one of the plurality of color filter patterns with a transmission wavelength in the range of 760 nm to 1000 nm.

In some embodiments, a plurality of second doped regions extend into the first doped regions.

In some embodiments, the semiconductor component further includes a third doped region. The third doped region is disposed in the substrate and has the second conductivity type. The third doping region is electrically connected to the plurality of second doping regions and the first doping region.

In some embodiments, the semiconductor device further includes a plurality of isolation structures extending from the top surface of the substrate to the interior of the substrate and located between two adjacent photodiodes respectively.

In some embodiments, the depth of the plurality of isolation structures is less than the depth of the plurality of photodiodes.

In some embodiments, the depth of the plurality of isolation structures is greater than the depth of the plurality of photodiodes.

In some embodiments, the semiconductor device further includes a plurality of field doped regions disposed in the substrate and having the first conductivity type. A plurality of isolation structures are located in the plurality of field doped regions.

The method for manufacturing a semiconductor component according to an embodiment of the present invention includes: forming a first initial doped region in a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type, and the first initial doped region has a second conductivity type; on the semiconductor substrate forming an epitaxial layer, and diffusing the first initial doping region upward to extend into the epitaxial layer to form a first doping region, wherein the epitaxial layer has a first conductivity type; a plurality of second doping regions, wherein a plurality of second doping regions are in contact with the first doping regions, and are located between the top surface of the epitaxial layer and the first doping regions; a plurality of photodiodes are formed in the epitaxial layer, wherein A plurality of second doping regions are located between the plurality of photodiodes and the first doping regions; a plurality of color filter patterns are formed on the epitaxial layer, wherein the plurality of color filter patterns overlap the plurality of photodiodes respectively. There are upper spacers between two adjacent second doped regions, and the plurality of upper spacers are vertically overlapped in the plurality of color filter patterns and have a plurality of transmission wavelengths in the range of 620 to 1000 nm.

In some embodiments, the plurality of second doped regions are located in the epitaxial layer and the semiconductor substrate. A method of forming a plurality of second doping regions includes forming a plurality of second initial doping regions in a semiconductor substrate after forming the first initial doping regions. A plurality of second initial doping regions are located between the top surface of the semiconductor substrate and the first initial doping regions. When the epitaxial layer is formed, the plurality of second initial doped regions are diffused upward to extend into the epitaxial layer to form a plurality of second doped regions.

In some embodiments, the numbers of the first initial doped regions and the first doped regions are respectively a majority. There are lower spacers between two adjacent first doped regions, and the plurality of lower spacers vertically overlap with some of the plurality of upper spacers and vertically overlap in the plurality of color filter patterns Several in the range of 760 nm to 1000 nm of penetration wavelength.

In some embodiments, the method of fabricating the semiconductor device further includes: forming a third doped region having the second conductivity type in the epitaxial layer. The third doping region is electrically connected to the plurality of second doping regions and the first doping region.

Based on the above, the semiconductor device according to the embodiment of the present invention can be used as an image sensor, and includes a first doped region and a plurality of second doped regions buried in the substrate and electrically connected to each other. By biasing the first doped region and the second doped region, the carriers formed inside the substrate can be guided to leave the substrate through the first doped region and the second doped region. In this way, the crosstalk between adjacent sub-pixels (or sensing units) can be reduced. In addition, the plurality of second doped regions located above the first doped regions are separated from each other, and a portion of the substrate extending between two adjacent second doped regions longitudinally overlaps the long-wavelength sub-pixels. In this way, the absorption depth of the absorption region through which the long-wavelength incident light passes can be increased. Therefore, the quantum efficiency of the long-wavelength subpixel can be improved.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

FIG. 1 is a flowchart of a method of manufacturing a semiconductor device according to some embodiments of the present invention;

2A to 2F are schematic cross-sectional views of structures at various stages in the manufacturing method of the semiconductor device shown in FIG. 1;

3 to 5 are schematic cross-sectional views of a central region of a semiconductor device according to some embodiments of the present invention;

6 is a flowchart of a method of manufacturing a semiconductor device according to some embodiments of the present invention;

7A to 7C are schematic cross-sectional views of structures at various stages in the manufacturing method of the semiconductor device shown in FIG. 6;

8 to 10 are schematic cross-sectional views of a central region of a semiconductor device according to some embodiments of the present invention.

Symbol Description

10, 10a, 10b, 10c, 20, 20a, 20b, 20c: Semiconductor components

102: first initial doping region

102a: first doped region

104, 204a: the second doping region

106, 106a, 106b: the third doped region

108, 108a, 108b: Fourth doped regions

110a, 110b: Contact area

204: the second initial doping region

AD: Active (Active) Components

AR, AR-1: Absorption zone

CF: Color filter layer

CFB: Blue Color Filter Pattern

CFG: Green Color Filter Pattern

CFI: Infrared light color filter pattern

CFR: Red color filter pattern

CR: Central District

D1, D2, D3, D4, D5, D6, D7, D8: Depth

DA, DA-1: absorption depth

DE: Drain

DL: Dielectric Layer

E1: first electrode

E2: Second electrode

EP: Epitaxial layer

FI, FI-1: Field doped regions

GD: Gate Dielectric Layer

GE: Grid

GS: Gate Structure

IS, ISa, ISa-1, ISb: Isolated structure

LI: lower compartment

M: Inline structure

ML: Micro lens

PD: Photodiode

PR: marginal zone

R: region

S100, S102, S102a, S104, S106, S108, S110, S112, S114, S116, S118: Steps

SB: base

SE: source

SP: Spacer

T1, T2, T3, T4, T5: Thickness

UI: Upper Spacer

W: Semiconductor substrate

W1: width

Detailed ways

FIG. 1 is a flowchart of a method of fabricating a semiconductor device in accordance with some embodiments of the present invention. 2A to 2F are schematic cross-sectional views of structures at various stages in the manufacturing method of the semiconductor device shown in FIG. 1 .

Referring to FIG. 1 and FIG. 2A , step S100 is performed to provide a semiconductor substrate W. In some embodiments, the semiconductor substrate W is a semiconductor wafer. In other embodiments, the semiconductor substrate W is a semiconductor-on-insulator (SOI) wafer including a buried insulating layer. The semiconductor material in the semiconductor substrate W may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, and the like. Compound semiconductors may include SiC, III-V semiconductor materials, or II-VI semiconductor materials. Additionally, the semiconductor material may be doped to the first conductivity type. In some embodiments, the first conductivity type is P-type, but the embodiments of the present invention are not limited thereto.

In some embodiments, the finally formed semiconductor device (such as the semiconductor device 10 shown in FIG. 2F ) has a central region CR and a peripheral region PR surrounding the central region CR. A plurality of photodiodes (such as photodiodes PD as shown in FIG. 2F ) are arranged in the central region CR, while no photodiodes are arranged in the edge region PR. In these embodiments, the semiconductor substrate W and the material layers formed thereon can also be divided into a central region CR and a peripheral region PR.

Step S102 is performed to form the first initial doping region 102 in the semiconductor substrate W. As shown in FIG. The first initial doped region 102 has a second conductivity type complementary to the first conductivity type, eg, an N-type. For example, the doping concentration of the first initial doping region 102 may be in the range of 10 ¹³ cm ⁻² to 10 ¹⁶ cm ⁻² . In some embodiments, the first preliminary doped region 102 extends continuously within the central region CR but does not extend into the edge region PR. In addition, the first initial doped region 102 is a shallow doped region. In some embodiments, the depth D1 from the top surface of the semiconductor substrate W to the top surface of the first preliminary doped region 102 is in the range of 0 μm to 1 μm. On the other hand, the thickness T1 of the first initial doped region 102 may be in the range of 10 nm to 1 μm.

Referring to FIG. 1 and FIG. 2B , step S104 is performed to form an epitaxial layer EP on the semiconductor substrate W. As shown in FIG. The semiconductor substrate W and the epitaxial layer EP can be collectively denoted as a substrate SB. In some embodiments, the epitaxial layer EP substantially completely covers the semiconductor substrate W, and extends in the central region CR and the edge region PR. In some embodiments, the thickness T2 of the epitaxial layer EP ranges from 4 μm to 8 μm. In addition, both the epitaxial layer EP and the semiconductor substrate W have the first conductivity type, for example, the P type. In some embodiments, the doping may be performed simultaneously in the epitaxial fabrication process used to form the epitaxial layer EP. In other embodiments, doping may also be performed after the epitaxial fabrication process by means of, for example, ion implantation. On the other hand, since the epitaxial fabrication process is performed at a high temperature (eg, 1000° C. to 1200° C.), the semiconductor substrate W adjacent to the epitaxial layer EP is also heated. In this way, the first initial doping region 102 in the semiconductor substrate W is diffused upward to extend into the epitaxial layer EP to form the first doping region 102a. In other words, the first doped region 102a longitudinally spans the interface between the semiconductor substrate W and the epitaxial layer EP. The first doped region 102a formed by this method may be located at the bottom of the epitaxial layer EP. In other words, the first doped region 102a of the embodiment of the present invention can have a relatively large depth D2 compared to the method of directly forming the doped region in the epitaxial layer by ion implantation. In some embodiments, the depth D2 of the first doped region 102a is in the range of 3 μm to 6 μm. In addition, in some embodiments, the first initial doped region 102 also slightly diffuses in other directions. In some embodiments, the formed first doped region 102a may have a thickness T3 of 0.5 μm to 4 μm.

Referring to FIG. 1 and FIG. 2C , step S106 is performed to form a plurality of second doped regions 104 in the epitaxial layer EP. Both the second doped region 104 and the first doped region 102a have a second conductivity type, eg, an N-type. In some embodiments, the doping concentration of the second doped region 104 is in the range of 10 ¹² cm ⁻² to 10 ¹⁴ cm ⁻² . In addition, the position of the second doping region 104 is close to the bottom of the epitaxial layer EP, and is located above the first doping region 102a. For example, the depth D3 from the top surface of the epitaxial layer EP to the top surface of the second doping region 104 may be in the range of 1.5 μm to 3 μm, and the thickness T4 of the second doping region 104 may be in the range of 0.5 μm to 3 μm In the range.

A plurality of second doped regions 104 are located in the central region CR and the edge region PR. A plurality of second doped regions 104 located in the central region CR are located between the top surface of the epitaxial layer EP and the first doped regions 102a. Furthermore, the bottom surface of the second doped region 104 located in the central region CR may be in contact with the top surface of the first doped region 102a. In some embodiments, the second doped region 104 located in the central region CR may further extend longitudinally into the first doped region 102a. In such embodiments, the bottom surface of the second doped region 104 in the central region CR is lower than the top surface of the first doped region 102a. In addition, the plurality of second impurity regions 104 within the central region CR are separated from each other. A portion of the epitaxial layer EP between adjacent second doped regions 104 may be referred to as an upper spacer UI. The mutually facing sidewalls of the adjacent second doped regions 104 define the side surfaces of the upper spacer region UI, and the top surface of the underlying first doped region 102a defines the bottom surface of the upper spacer region UI. In some embodiments, the width of the upper spacer UI is about the width of a single sub-pixel or a single sensing unit in the final image sensor (eg, the semiconductor device 10 of FIG. 2F ). For example, the width W1 of the upper spacer UI may be in the range of 1 μm to 6 μm. Viewed from another angle, the upper spacer region UI can also be regarded as an extension portion of the epitaxial layer EP extending between two adjacent second doped regions 104 . In addition, the upper spacer UI vertically overlaps some color filter patterns formed on the epitaxial layer EP subsequently. For example, the upper spacer UI vertically overlaps some color filter patterns (such as the red color filter pattern CFR shown in FIG. 2F or the infrared light shown in FIG. Color filter pattern CFI). On the other hand, the edge region PR may have one or more second doping regions 104 .

In some embodiments, the plurality of second doped regions 104 in the central region CR and the edge region PR may be formed by an ion implantation process. In addition, the positions of the plurality of second doped regions 104 in the central region CR can be defined by a photoresist pattern (not shown) formed on the epitaxial layer EP during the ion implantation process.

Referring to FIG. 1 and FIG. 2D , step S108 is performed to form a plurality of field doped regions FI in the epitaxial layer EP. Both the field doped region FI and the epitaxial layer EP have a first conductivity type (eg P-type), and the doping concentration of the field doped region FI is higher than that of the epitaxial layer EP. For example, the doping concentration of the field-doped region FI is in the range of 10 ¹² cm ⁻² to 10 ¹⁴ cm ⁻² . In some embodiments, a plurality of field doped regions FI are disposed in the central region CR and are separated from each other. The portion of the epitaxial layer EP located between two adjacent field doped regions FI can be used to form a plurality of photodiodes (eg, the photodiodes PD shown in FIG. 2F ) in subsequent steps. In some embodiments, the field doped layer FI extends downward from the surface of the epitaxial layer EP. In some embodiments, the depth D4 of the field-doped layer FI is in the range of 0 μm to 3 μm.

In some embodiments, before or after step S108, a third doped region 106 may also be formed in the epitaxial layer EP. The first doped region 102a, the second doped region 104 and the third doped region 106 all have a second conductivity type, such as N-type. In some embodiments, the doping concentration of the third doped region 106 is in the range of 10 ¹² cm ⁻² to 10 ¹⁴ cm ⁻² . The third doped region 106 may be located within the central region CR, and may be located outside the plurality of field doped regions FI. In some embodiments, the third doped region 106 may include a third doped region 106a and a third doped region 106b. The third doping region 106a extends downward from the top surface of the epitaxial layer EP, and the third doping region 106b is connected between the third doping region 106a and the second doping region 104 . In addition, the second doping region 104 is electrically connected to the first doping region 102a. As such, the third doped region 106a, the third doped region 106b, the second doped region 104, and the first doped region 102a are electrically connected to each other, and can be configured to receive a bias, such as a positive bias. In some embodiments, the top of the third doped region 106b may extend upward into the third doped region 106a and the bottom of the third doped region 106b may extend downward into the second doped region 104 .

In some embodiments, a fourth doped region 108 may also be formed in the epitaxial layer EP before or after step S108. Both the epitaxial layer EP and the fourth doped region 108 have a first conductivity type, such as P-type. For example, the doping concentration of the fourth doping region 108 is in the range of 10 ¹² cm ^-2 to 10 ¹⁴ cm ^-2 . In some embodiments, the fourth doped region 108 may include a fourth doped region 108a and a fourth doped region 108b. The fourth doped region 108a is located within the central region CR, and may be located between the third doped region 106a and the plurality of field doped regions FI. In some embodiments, the fourth doped region 108a may also extend laterally into the outermost field doped region FI. Since the epitaxial layer EP and the fourth doped region 108 have the same conductivity type, they can be electrically connected to each other, and can be configured to receive a reference voltage or a negative bias voltage. On the other hand, the fourth doped region 108b is located in the edge region PR. In some embodiments, the fourth doped region 108b may extend laterally in a portion of the epitaxial layer EP located in the edge region PR, and may serve as an active component (eg, the active component of FIG. 2F ) formed in the edge region PR subsequently. well area of components AD).

Step S110 is performed to form an isolation structure IS in the epitaxial layer EP. In some embodiments, the isolation structures IS may include a plurality of isolation structures ISa and a plurality of isolation structures ISb. A plurality of isolation structures ISa are disposed in the central region CR and are respectively located in the plurality of field doping regions FI. The isolation structure ISa may extend from the top surface of the epitaxial layer EP to the interior of the epitaxial layer EP. In addition, the bottom surface of the isolation structure ISa is higher than the bottom surface of the field doped region FI. In other words, the depth D5 of the isolation structure ISa may be smaller than the depth D4 of the field doped region FI. For example, the depth D5 of the isolation structure ISa may be in the range of 250 nm to 400 nm. The isolation structure ISa and the field doped region FI can be combined to reduce crosstalk between photodiodes (eg, the photodiodes PD shown in FIG. 2F ) subsequently formed on opposite sides of the isolation structure ISa. On the other hand, some isolation structures ISb are located in the central region CR, while other isolation structures ISb are located in the edge region PR. In some embodiments, the isolation structure ISb in the central region CR may be disposed near the interface between the third doped region 106a and the fourth doped region 108a. In such embodiments, the isolation structure ISb located in the central region CR may also extend laterally into the third doped region 106a and the fourth doped region 108a. In addition, the isolation structures ISb located in the edge region PR may be disposed in the fourth doping region 108b separately from each other. In the subsequent fabrication process, active components (eg, active components AD shown in FIG. 2F ) may be formed between adjacent isolation structures ISb. In some embodiments, the isolation structure IS (for example, including the isolation structure ISa and the isolation structure ISb) is a shallow trench isolation (STI) structure. Furthermore, in some embodiments, the depth of the isolation structure ISb may be substantially equal to the depth of the isolation structure ISa.

In some embodiments, the method of forming the isolation structure IS may include forming a trench (not shown) on the surface of the epitaxial layer EP. Next, an insulating material is formed in the trench by a method such as a chemical vapor deposition process, so as to form the isolation structure IS.

Referring to FIG. 1 and FIG. 2E , step S112 is performed to form a plurality of photodiodes PD in the epitaxial layer EP. A plurality of photodiodes PD are disposed in the central region CR. In some embodiments, the photodiode PD is disposed on top of the epitaxial layer EP. In other words, the second doped region 104 may be located between the photodiode PD and the first doped region 102a. In addition, the photodiode PD is longitudinally overlapped with the second doping region 104 and the first doping region 102a. In some embodiments, a plurality of photodiodes PD can be respectively disposed between two adjacent field doped regions FI (ie, between two isolation structures ISa). The photodiode PD may include a first electrode E1 and a second electrode E2. In some embodiments, both the first electrode E1 and the second electrode E2 are doped regions formed in the epitaxial layer EP. The first electrode E1 has a first conductivity type (eg, P-type), and the second electrode E2 has a second conductivity type (eg, N-type). In some embodiments, the doping concentration of the first electrode E1 is in the range of 10 ¹² cm ⁻² to 10 ¹⁵ cm ⁻² , and the doping concentration of the second electrode E2 is in the range of 10 ¹² cm ⁻² to 10 ¹⁴ cm ⁻² within the range of ² . In some embodiments, the first electrode E1 is disposed above the second electrode E2. In these embodiments, the first electrode E1 may extend from the top surface of the epitaxial layer EP to the interior of the epitaxial layer EP, and the second electrode E2 may extend downward from the bottom surface of the first electrode E1. In some embodiments, the bottom surface of the first electrode E1 is higher than the bottom surface of the isolation structure ISa. In addition, the bottom surface of the second electrode E2 may be higher than the bottom surface of the field doping region FI, and may be lower than the bottom surface of the isolation structure ISa.

In some embodiments, before or after step S112, a contact region 110a may be formed on top of the third doped region 106a. In some embodiments, the contact region 110a is a doped region and extends downward from the top surface of the epitaxial layer EP. In some embodiments, the bottom surface of the contact region 110a is higher than the bottom surface of the isolation structure ISb, and is higher than the bottom surface of the third doped region 106a. In addition, the contact region 110a has a second conductivity type (eg, N-type), and can be electrically connected to the third doping region 106, the second doping region 104 and the first doping region 102a. In some embodiments, the contact region 110a is a heavily doped region. In such embodiments, the doping concentration of the contact region 110 a is higher than the doping concentration of the third doping region 106 . In this way, by providing the contact region 110a, the contact resistance between the third doped region 106 and the interconnection structure (eg, the interconnection structure M shown in FIG. 2F ) formed on the epitaxial layer EP subsequently can be reduced. On the other hand, a contact region 110b may be formed on top of the fourth doped region 108a. Similar to the contact region 110a, the contact region 110b may also be a doped region and extend downward from the top surface of the epitaxial layer EP. In some embodiments, the bottom surface of the contact region 110b is higher than the bottom surface of the isolation structure ISb (or the isolation structure ISa), and is higher than the bottom surface of the fourth doped region 108a. The contact region 110b has a first conductivity type (eg, P-type), and can be electrically connected to the fourth doped region 108a and the epitaxial layer EP. In some embodiments, the contact region 110b is a heavily doped region. In such embodiments, the doping concentration of the contact region 110b is higher than the doping concentration of the fourth doping region 108a. In this way, by providing the contact region 110b, the contact resistance between the fourth doped region 108a and the interconnection structure (eg, the interconnection structure M shown in FIG. 2F ) formed on the epitaxial layer EP subsequently can be reduced.

In some embodiments, before or after step S112, the active component AD may be formed in the edge region PR. Each active component AD may be located between adjacent isolation structures ISb. For example, the active device AD may be a field effect transistor. In some embodiments, the active device AD may include a gate structure GS, a drain DE and a source SE. The gate structure GS may be located on the epitaxial layer EP, and includes a gate electrode GE, a gate dielectric layer GD, and a spacer SP. The gate dielectric layer GD is located between the gate electrode GE and the top surface of the epitaxial layer EP, and the spacer SP surrounds the gate electrode GE and the gate dielectric layer GD. On the other hand, the drain electrode DE and the source electrode SE may be disposed in the epitaxial layer EP on opposite sides of the gate structure GS. In some embodiments, the drain DE and the source SE are disposed in the fourth doped region 108b. The drain electrode DE and the source electrode SE have the same conductivity type, and the conductivity type can be complementary to the conductivity type of the fourth doped region 108b. For example, the drain electrode DE and the source electrode SE have a second conductivity type (eg, N-type), and the fourth doped region 108b has a first conductivity type (eg, P-type). In other embodiments, the active device AD may also include a diode, a bipolar junction transistor (BJT), the like, or a combination thereof. Those with ordinary knowledge in the art can select the type and configuration of the active component AD according to the design requirements, and the embodiment of the present invention is not limited to this.

Referring to FIG. 1 and FIG. 2F , step S114 is performed to form a plurality of dielectric layers DL and interconnect structures M on the epitaxial layer EP. FIG. 2F only shows a plurality of dielectric layers DL and the interconnect structure M in a schematic diagram. The dielectric layer DL and the interconnect structure M are formed in the central region CR and the edge region PR. A plurality of dielectric layers DL may be stacked on the epitaxial layer EP, and the interconnect structure M may be formed in the plurality of dielectric layers DL. The plurality of photodiodes PD can be electrically connected to a logic circuit (not shown) through the interconnect structure M. In addition, the interconnect structure M can be electrically connected to the contact area 110a, the contact area 110b and the active device AD, respectively. In some embodiments, the portion of the dielectric layer DL overlapping the plurality of photodiodes PD in the longitudinal direction (eg, the region R shown in FIG. 2F ) may not have an interconnect structure. In this way, the light incident from the outside can smoothly pass through the regions R to enter the photodiode PD, and the chance of being reflected by the interconnect structure M is reduced.

Go to step S116 to form a color filter layer CF on the uppermost dielectric layer DL. The color filter layer CF is formed in the central region CR and overlaps the plurality of photodiodes PD. In some embodiments, the color filter layer CF may include a plurality of color filter patterns, such as a blue color filter pattern CFB, a green color filter pattern CFG, and a red color filter pattern CFR. In some embodiments, the transmission wavelength band of the blue color filter pattern CFB is 476 nm to 495 nm. The transmission band of the green color filter pattern CFG may be 495 nm to 570 nm. The transmission band of the red color filter pattern CFR may be 620 nm to 750 nm. The plurality of color filter patterns are respectively vertically overlapped with the plurality of photodiodes PD. Only the incident light of a specific wavelength band can penetrate the color filter pattern of a specific color, then pass through the region R of the dielectric layer DL and enter the photodiode PD. As such, each photodiode PD is configured to receive light in a particular wavelength band and convert it into an electrical signal. Each photodiode PD and its vertical overlapping structure can be regarded as a sub-pixel or a sensing unit.

Proceed to step S118 to form a plurality of microlenses ML on the color filter layer CF. The plurality of microlenses ML may be longitudinally overlapped with the plurality of color filter patterns, and may be longitudinally overlapped with the plurality of photodiodes PD.

So far, the semiconductor device 10 according to some embodiments of the present invention has been completed. The semiconductor device 10 can be used as an image sensor. The semiconductor device 10 includes a first doped region 102a and a second doped region 104 disposed in the epitaxial layer EP. By subjecting the first doped region 102a and the second doped region 104 to receive a positive bias voltage, electrons generated deep in the epitaxial layer EP by the incident light with long wavelengths can be guided to leave the epitaxial layer EP. In this way, the crosstalk between adjacent sub-pixels can be further reduced. On the other hand, by causing the fourth doped region 108a disposed in the epitaxial layer EP to receive a reference voltage or a negative voltage, holes generated deep in the epitaxial layer EP by long wavelength incident light can be guided away from the epitaxial layer EP. In addition, for long-wavelength incident light (eg, red light passing through the red color filter pattern CFR), a large absorption depth is required to enable the corresponding photodiode PD to achieve sufficient quantum efficiency. The absorption depth mentioned herein refers to the thickness of the portion of the epitaxial layer EP that overlaps the photodiode PD longitudinally, and this portion does not include the first doped region 102 a and the second doped region 104 . In the embodiment of the present invention, the second doped regions 104 are separately disposed in the epitaxial layer EP, and the gaps between adjacent second doped regions 104 are vertically overlapped with the color filter pattern that can transmit long-wavelength light. In this way, the long wavelength incident light can enter the absorption region with a larger absorption depth. For example, the upper spacer region UI of the epitaxial layer EP located between the adjacent second doping regions 104 is longitudinally overlapped with the red color filter pattern CFR, so that the red light enters into the region with a larger absorption depth DA. Absorption area AR. Therefore, the quantum efficiency of the corresponding photodiode PD can be improved.

3 is a schematic cross-sectional view of the central region CR of the semiconductor device 10a according to some embodiments of the present invention. The semiconductor device 10a shown in FIG. 3 is similar to the semiconductor device 10 shown in FIG. 2F , and only the differences between the two are described below, and the same or similar parts will not be repeated. Additionally, the same or similar reference numerals represent the same or similar components.

Referring to FIG. 3, the isolation structure ISa-1 of the semiconductor device 10a is a deep trench isolation (DTI). The depth D6 of the isolation structure ISa-1 may be greater than the depth of the photodiode PD. In some embodiments, the isolation structure ISa- 1 may extend longitudinally to contact the top surface of the second doped region 104 . In other embodiments, the bottom surface of the isolation structure ISa- 1 is higher than the top surface of the second doped region 104 . In other embodiments, the isolation structure ISa-1 may also extend into the second doped region 104, or may also extend into the first doped region 102a. For example, the depth D6 of the isolation structure ISa-1 may be in the range of 1 μm to 8 μm. In the embodiment shown in FIG. 3, the field doped region FI-1 also has a greater depth. In some embodiments, the field doped region FI- 1 may extend into the second doped region 104, or may also extend into the first doped region 102a. In other embodiments, the bottom surface of the field doped region FI-1 may also be higher than or in contact with the top surface of the second doped region 104, or may be higher than or in contact with the top surface of the first doped region 102a. For example, the depth D7 of the field-doped region FI-1 may be in the range of 1.2 μm to 8.5 μm.

Crosstalk between adjacent photodiodes PD or adjacent sub-pixels can be further reduced by increasing the depth of the isolation structure and the field-doped region between adjacent photodiodes PD.

4 is a schematic cross-sectional view of the central region CR of the semiconductor device 10b according to some embodiments of the present invention. The semiconductor device 10b shown in FIG. 4 is similar to the semiconductor device 10 shown in FIG. 2F , and only the differences between the two are described below, and the same or similar parts will not be repeated. Additionally, the same or similar reference numerals represent the same or similar components.

Referring to FIG. 4, the color filter layer CF-1 of the semiconductor device 10b further includes an infrared color filter pattern CFI. In some embodiments, the transmission band of the infrared color filter pattern CFI is 760 nm to 1000 nm. In addition, the semiconductor device 10b includes a plurality of first doped regions 102a. The plurality of first doped regions 102a are separated from each other. A portion of the epitaxial layer EP and the semiconductor substrate W located between the adjacent first doped regions 102a may be referred to as a lower spacer LI. Some of the upper spacers UI respectively located between the two adjacent second doping regions 104 are longitudinally communicated with the lower spacers LI, while other upper spacers UI are not longitudinally overlapped with the lower spacers LI. In some embodiments, the upper spacer UI and the lower spacer L1, which are longitudinally overlapped with each other, are longitudinally overlapped with the infrared color filter pattern CFI. On the other hand, some of the upper spacers UI that are not longitudinally overlapped with the lower spacers LI are longitudinally overlapped with the red color filter pattern CFR.

In the embodiment shown in FIG. 4, the infrared light enters the absorption region AR-1 with a larger absorption depth DA-1. In this way, the quantum efficiency of the photodiode PD vertically overlapping with the infrared color filter pattern CFI can be further improved.

5 is a schematic cross-sectional view of the central region CR of the semiconductor device 10c according to some embodiments of the present invention. The semiconductor device 10c shown in FIG. 5 is similar to the semiconductor device 10b shown in FIG. 4 . Specifically, the semiconductor device 10c shown in FIG. 5 can be regarded as the deep trench isolation structure ISa-1 and the field doped region FI-1 shown in FIG. 3 respectively replacing the shallow surface of the semiconductor device 10b shown in FIG. 4 The trench isolation structure ISa and the field doped region FI.

FIG. 6 is a flowchart of a method of fabricating semiconductor device 20 in accordance with some embodiments of the present invention.

7A to 7C are schematic cross-sectional views of structures at various stages in the manufacturing method of the semiconductor device 20 shown in FIG. 6 . The semiconductor device 20 and its manufacturing method shown in FIGS. 6 and 7A to 7C are similar to the semiconductor device 10 and its manufacturing method shown in FIGS. 1 and 2A to 2F , and only the differences between the two are described below. Similarities will not be repeated. Additionally, the same or similar reference numerals represent the same or similar components.

Referring to FIG. 6 and FIG. 7A , step S102 a is performed after step S100 to form a first initial doping region 102 and a plurality of second initial doping regions 204 in the semiconductor substrate W. As shown in FIG. Both the first initial doping region 102 and the plurality of second initial doping regions 204 have a second conductivity type, such as N-type. In some embodiments, the first preliminary doping region 102 and the plurality of second preliminary doping regions 204 are both located in the central region CR. A plurality of second preliminary doping regions 204 are located between the top surface of the semiconductor substrate W and the first preliminary doping regions 102 . Furthermore, in some embodiments, a plurality of second preliminary doped regions 204 may be in contact with the first preliminary doped regions 102 . In other embodiments, the plurality of second initial doping regions 204 may also be higher than the first initial doping regions 102 and not in contact with the first initial doping regions 102 .

Referring to FIG. 6 and FIG. 7B , step S104 is then performed to form an epitaxial layer EP on the semiconductor substrate W. As shown in FIG. During the process of forming the epitaxial layer EP, the semiconductor substrate W is heated so that the first preliminary doping region 102 and the plurality of second preliminary doping regions 204 are diffused upward to extend into the epitaxial layer EP. In this way, the first doped region 102a and the plurality of second doped regions 204a can be formed. The top surfaces of the plurality of second doped regions 204a are higher than the top surfaces of the first doped regions 102a, and the bottom surfaces of the plurality of second doped regions 204a are located in the first doped regions 102a. In some embodiments, the plurality of second doped regions 204a may be viewed as extending longitudinally into the first doped regions 102a. In some embodiments, the depth D8 of the second doped region 204a is in the range of 2 μm to 4 μm. In addition, in some embodiments, the thickness T5 of the second doped region 204a may be 1 μm to 4 μm.

Referring to FIG. 6 and FIG. 7C , steps S106 to S118 are sequentially performed to complete the fabrication of the semiconductor device 20 . The difference between the semiconductor device 20 and the semiconductor device 10 shown in FIG. 2F mainly lies in the location and formation method of the second doped region. The semiconductor device 20 may also reduce crosstalk between adjacent sub-pixels. In addition, the long-wavelength incident light can also enter the absorption region AR with a larger absorption depth DA, and improve the quantum efficiency of the long-wavelength sub-pixels. In the embodiment shown in FIG. 7C , the upper spacer region UI of the epitaxial layer EP located between two adjacent second doping regions 204a may overlap with color filters capable of transmitting wavelengths in the range of 620nm to 1000nm The patterns are, for example, a red color filter pattern CFR and an infrared color filter pattern CFI.

8 is a schematic cross-sectional view of the central region CR of the semiconductor device 20a according to some embodiments of the present invention. The semiconductor device 20a shown in FIG. 8 is similar to the semiconductor device 20 shown in FIG. 7C. Specifically, the semiconductor device 20a shown in FIG. 8 can be regarded as the deep trench isolation structure ISa-1 and the field doped region FI-1 shown in FIG. 3 respectively replacing the shallow surface of the semiconductor device 20 shown in FIG. 7C . The trench isolation structure ISa and the field doped region FI.

9 is a schematic cross-sectional view of the central region CR of the semiconductor device 20b according to some embodiments of the present invention. The semiconductor device 20b shown in FIG. 9 is similar to the semiconductor device 20 shown in FIG. 7C. Specifically, the semiconductor device 20b shown in FIG. 9 can be regarded as replacing the single first doped region 102a of the semiconductor device 20 shown in FIG. 7C with a plurality of first doped regions 102a separated from each other shown in FIG. 4 . . In addition, the upper spacer UI and the lower spacer LI of the epitaxial layer EP that communicate with each other are longitudinally overlapped with the infrared color filter pattern CFI, and the upper spacer UI that is not connected downward to the lower spacer LI is longitudinally overlapped with the infrared color filter pattern CFI. Red color filter pattern CFR.

10 is a schematic cross-sectional view of the central region CR of the semiconductor device 20c according to some embodiments of the present invention. The semiconductor device 20c shown in FIG. 10 is similar to the semiconductor device 20 shown in FIG. 7C. Specifically, the semiconductor device 20c shown in FIG. 10 can be regarded as the deep trench isolation structure ISa-1 and the field doped region FI-1 shown in FIG. 3 respectively replacing the shallow surface of the semiconductor device 20 shown in FIG. 7C The trench isolation structure ISa and the field doped region FI.

To sum up, the semiconductor device of the embodiment of the present invention can be used as an image sensor, and includes a first doped region and a plurality of second doped regions buried in the substrate and electrically connected to each other. By biasing the first doped region and the second doped region, the carriers formed inside the substrate can be guided to leave the substrate through the first doped region and the second doped region. In this way, crosstalk between adjacent sub-pixels can be reduced. In addition, the plurality of second doped regions located above the first doped regions are separated from each other, and a portion of the substrate extending between two adjacent second doped regions longitudinally overlaps the long-wavelength sub-pixels. In this way, the absorption depth of the absorption region through which the long-wavelength incident light passes can be increased. Therefore, the quantum efficiency of the long-wavelength subpixel can be improved.

Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The scope of protection of the present invention should be defined by the appended claims.

Claims (16)

1. A semiconductor component, characterized in that, comprising: a substrate having a first conductivity type; a plurality of photodiodes extending from the top of the substrate to the interior of the substrate; a plurality of color filter patterns, disposed on the substrate, and respectively vertically overlapping the plurality of photodiodes; a first doped region disposed in the substrate and having a second conductivity type; and a plurality of second doped regions disposed in the substrate and having the second conductivity type, wherein the plurality of second doped regions are in contact with the first doped regions and located at the plurality of photodiodes Between the first doped regions and the adjacent second doped regions, there are upper spacers, and a plurality of the upper spacers are vertically overlapped in the plurality of color filter patterns with Several of the penetration wavelengths are in the range of 620 nm to 1000 nm. 2. The semiconductor assembly of claim 1, wherein the base comprises a semiconductor substrate and an epitaxial layer, the epitaxial layer is disposed on the semiconductor substrate, and the first doped region extends from the semiconductor substrate to in the bottom of the epitaxial layer, and the plurality of second doped regions are located in the epitaxial layer. 3. The semiconductor device of claim 1, wherein the first doped region extends continuously and vertically overlaps the plurality of second doped regions and the plurality of photodiodes. 4. The semiconductor device of claim 3, wherein a top surface of the first doped region defines a bottom surface of the plurality of upper spacers. 5 . The semiconductor device of claim 1 , wherein the number of the first doping regions is plural, and there are lower spacers between two adjacent first doping regions, and a plurality of the lower spacers are longitudinally respectively grounded in communication with some of the plurality of upper spacers. 6. The semiconductor device of claim 5, wherein the plurality of lower spacers vertically overlap a plurality of the plurality of color filter patterns in the range of transmission wavelengths from 760 nm to 1000 nm. 7. The semiconductor assembly of claim 1, wherein the plurality of second doped regions extend into the first doped regions. 8. The semiconductor device of claim 1, further comprising a third doped region disposed in the substrate and having the second conductivity type, wherein the third doped region is electrically connected to the plurality of second doped regions a doped region and the first doped region. 9 . The semiconductor device of claim 1 , further comprising a plurality of isolation structures extending from the top surface of the substrate to the interior of the substrate and located between two adjacent photodiodes, respectively. 10 . 10. The semiconductor assembly of claim 9, wherein a depth of the plurality of isolation structures is less than a depth of the plurality of photodiodes. 11. The semiconductor assembly of claim 9, wherein a depth of the plurality of isolation structures is greater than a depth of the plurality of photodiodes. 12. The semiconductor device of claim 9, further comprising a plurality of field doped regions disposed in the substrate and having a first conductivity type, wherein the plurality of isolation structures are located in the plurality of field doped regions middle. 13. A method of manufacturing a semiconductor component, comprising: forming a first initial doped region in a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type, and the first initial doped region has a second conductivity type; An epitaxial layer is formed on the semiconductor substrate, and the first initial doped region is diffused upward to extend into the epitaxial layer to form a first doped region, wherein the epitaxial layer has the first conductivity type; A plurality of second doping regions having the second conductivity type are formed in the epitaxial layer, wherein the plurality of second doping regions are in contact with the first doping region and are located on the epitaxial layer between the top surface and the first doped region; forming a plurality of photodiodes in the epitaxial layer, wherein the plurality of second doped regions are located between the plurality of photodiodes and the first doped regions; forming a plurality of color filter patterns on the epitaxial layer, wherein the plurality of color filter patterns respectively overlap the plurality of photodiodes, There are upper spacers between two adjacent second doped regions, and a plurality of the upper spacers vertically overlap a plurality of color filter patterns and have a plurality of transmission wavelengths in the range of 620nm to 1000nm . 14. The method of manufacturing a semiconductor device according to claim 13, wherein the plurality of second doped regions are located in the epitaxial layer and the semiconductor substrate, and the method of forming the plurality of second doped regions include: After forming the first initial doping region, a plurality of second initial doping regions are formed in the semiconductor substrate, wherein the plurality of second initial doping regions are located between the top surface of the semiconductor substrate and the first initial doping region. The plurality of second doped regions are formed between an initial doped region and wherein the plurality of second initial doped regions are diffused upward to extend into the epitaxial layer when the epitaxial layer is formed. 15. The method for manufacturing a semiconductor device as claimed in claim 13, wherein the number of the first initial doping region and the first doping region are respectively a majority, and wherein the first doping regions are adjacent to each other in pairs There are lower spacers therebetween, and a plurality of the lower spacers vertically overlap some of the plurality of upper spacers, and vertically overlap the plurality of color filter patterns with a penetrating wavelength at Several in the range of 760nm to 1000nm. 16. The method of manufacturing a semiconductor device of claim 13, further comprising: A third doped region having the second conductivity type is formed in the epitaxial layer, wherein the third doped region is electrically connected to the plurality of second doped regions and the first doped region.

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