CN111490058A

CN111490058A - Semiconductor assembly and its manufacturing method

Info

Publication number: CN111490058A
Application number: CN201910110960.6A
Authority: CN
Inventors: 钟志平; 苏俊铭; 何明祐; 毕嘉慧
Original assignee: Powerchip Technology Corp
Current assignee: Powerchip Technology Corp
Priority date: 2019-01-28
Filing date: 2019-02-12
Publication date: 2020-08-04
Anticipated expiration: 2039-02-12
Also published as: TWI691096B; TW202029518A; CN111490058B

Abstract

The invention discloses a semiconductor assembly and a manufacturing method thereof. The semiconductor component comprises a substrate, a first doping area, a plurality of second doping areas and a plurality of photodiodes, wherein the first doping area, the plurality of second doping areas and the plurality of photodiodes are positioned in the substrate, and the semiconductor component comprises a plurality of color filter patterns arranged on the substrate. The substrate has a first conductivity type, and the first doped region and the second doped region have a second conductivity type. The photodiode extends from the top surface of the substrate to the inside. The color filter patterns are longitudinally overlapped with the photodiodes respectively. The plurality of second doped regions are in contact with the first doped regions and are located between the plurality of photodiodes and the first doped regions. The upper spacing regions are arranged between every two adjacent second doping regions, and the upper spacing regions are longitudinally overlapped with a plurality of color filtering patterns with the penetration wavelength of 620nm to 1000 nm.

Description

Semiconductor assembly and its manufacturing method

Technical Field

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an image sensor (imager) and a method of manufacturing the same.

Background

An image sensor (image sensor) fabricated by a semiconductor fabrication process may be used to sense light incident to a substrate. The image sensor receives light energy and converts the light energy into a digital signal by using the sensing unit array. However, due to different absorption depths of the substrate for different wavelengths of light, crosstalk (crosstalk) may occur between the sensing units to different extents. Specifically, the substrate needs to have a larger absorption depth for incident light with a longer wavelength to increase the absorption efficiency of photons. The carriers generated by the incident light in the deep substrate are far away from the electric field range of the sensing unit and can be diffused to the sensing units adjacent to other colors. As a result, the sensing units of different colors cannot absorb the carriers generated by the corresponding color lights, and sensing errors occur.

Disclosure of Invention

The invention provides a semiconductor assembly and a manufacturing method thereof. The semiconductor device can be used as an image sensor and can reduce crosstalk between adjacent sensing units.

The semiconductor component comprises a substrate, a plurality of photodiodes, a plurality of color filter patterns, a first doping area and a plurality of second doping areas. The substrate has a first conductivity type. The plurality of photodiodes extend from the top surface of the substrate toward the interior of the substrate. The color filter patterns are arranged on the substrate and longitudinally overlapped with the photodiodes respectively. The first doped region is disposed in the substrate and has a second conductivity type. The plurality of second doped regions are disposed in the substrate and have the second conductivity type. The plurality of second doped regions are in contact with the first doped regions and are located between the plurality of photodiodes and the first doped regions. The upper spacing regions are arranged between every two adjacent second doping regions, and the upper spacing regions are longitudinally overlapped with a plurality of color filtering patterns with the penetration wavelength of 620nm to 1000 nm.

In some embodiments, the base includes a semiconductor substrate and an epitaxial layer. The epitaxial layer is disposed on the semiconductor substrate. The first doped region extends from the inside of the semiconductor substrate to the bottom of the epitaxial layer, and the plurality of second doped regions are located in the epitaxial layer.

In some embodiments, the first doped region extends continuously and vertically overlaps the plurality of second doped regions and the plurality of photodiodes.

In some embodiments, the top surface of the first doped region defines a bottom surface of the plurality of upper spacer regions.

In some embodiments, the number of the first doped regions is a majority. And a plurality of lower spacing regions are longitudinally communicated with a plurality of upper spacing regions respectively.

In some embodiments, the plurality of lower spacers vertically overlap one of the plurality of color filter patterns having a transmission wavelength in a range of 760nm to 1000 nm.

In some embodiments, the plurality of second doped regions extend into the first doped region.

In some embodiments, the semiconductor device further comprises a third doped region. The third doped region is disposed in the substrate and has a second conductivity type. The third doped region is electrically connected to the plurality of second doped regions and the first doped region.

In some embodiments, the semiconductor device further includes a plurality of isolation structures extending from the top surface of the substrate to the inside of the substrate and respectively located between two adjacent photodiodes.

In some embodiments, the depth of the plurality of isolation structures is less than the depth of the plurality of photodiodes.

In some embodiments, the depth of the plurality of isolation structures is greater than the depth of the plurality of photodiodes.

In some embodiments, the semiconductor device further includes a plurality of field doping regions disposed in the substrate and having the first conductivity type. A plurality of isolation structures are located in the plurality of field doping regions.

The manufacturing method of the semiconductor component comprises the following steps: forming a first initial doped region in a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type, and the first initial doped region has a second conductivity type; forming an epitaxial layer on the semiconductor substrate, and diffusing the first initial doped region upwards to extend into the epitaxial layer to form a first doped region, wherein the epitaxial layer has a first conductivity type; forming a plurality of second doped regions of a second conductivity type in the epitaxial layer, wherein the plurality of second doped regions are in contact with the first doped region and are located between the top surface of the epitaxial layer and the first doped region; forming a plurality of photodiodes in the epitaxial layer, wherein a plurality of second doped regions are located between the plurality of photodiodes and the first doped region; and forming a plurality of color filter patterns on the epitaxial layer, wherein the plurality of color filter patterns are respectively overlapped with the plurality of photodiodes. Upper spacing regions are arranged between every two adjacent second doping regions, and the upper spacing regions vertically overlap a plurality of color filter patterns with the penetration wavelength in the range of 620-1000 nm.

In some embodiments, a plurality of second doped regions are located in the epitaxial layer and the semiconductor substrate. The method for forming a plurality of second doping regions comprises the following steps: a plurality of second preliminary doped regions are formed in the semiconductor substrate after the first preliminary doped regions are formed. The plurality of second initial doping regions are positioned between the top surface of the semiconductor substrate and the first initial doping regions. The plurality of second preliminary doping regions are diffused upwards to extend into the epitaxial layer when the epitaxial layer is formed, so that a plurality of second doping regions are formed.

In some embodiments, the number of the first initial doping region and the number of the first doping region are respectively the majority. Lower spacing regions are arranged between every two adjacent first doping regions, and the lower spacing regions vertically overlap with a plurality of upper spacing regions and vertically overlap with a plurality of color filter patterns with the transmission wavelength in the range of 760nm to 1000 nm.

In some embodiments, the method of manufacturing a semiconductor assembly further comprises: a third doped region of the second conductivity type is formed in the epitaxial layer. The third doped region is electrically connected to the plurality of second doped regions and the first doped region.

Based on the above, the semiconductor device of the embodiment of the invention can be used as an image sensor, and includes a first doped region and a plurality of second doped regions embedded in a substrate and electrically connected to each other. By making the first doped region and the second doped region receive a bias voltage, carriers formed inside the substrate can be guided to leave the substrate through the first doped region and the second doped region. Thus, the crosstalk between adjacent sub-pixels (or sensing units) can be reduced. In addition, the plurality of second doped regions above the first doped region are separated from each other, and a portion of the substrate extending between two adjacent second doped regions longitudinally overlaps the sub-pixel with the long wavelength. Therefore, the absorption depth of the absorption region through which the long-wavelength incident light passes can be increased. Therefore, the quantum efficiency of the long wavelength sub-pixel can be improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a flow chart of a method of fabricating a semiconductor device in accordance with some embodiments of the present invention;

FIGS. 2A-2F are schematic cross-sectional views of structures at various stages in a method of fabricating the semiconductor assembly shown in FIG. 1;

fig. 3-5 are schematic cross-sectional views of a central region of a semiconductor assembly in accordance with some embodiments of the present invention;

FIG. 6 is a flow chart of a method of fabricating a semiconductor assembly in accordance with some embodiments of the present invention;

FIGS. 7A-7C are schematic cross-sectional views of structures at various stages in the method of fabricating the semiconductor assembly shown in FIG. 6;

fig. 8-10 are cross-sectional schematic views of a central region of a semiconductor assembly in accordance with some embodiments of the present invention.

Description of the symbols

10. 10a, 10b, 10c, 20a, 20b, 20 c: semiconductor assembly

102: a first initial doped region

102 a: first doped region

104. 204 a: second doped region

106. 106a, 106 b: a third doped region

108. 108a, 108 b: a fourth doped region

110a, 110 b: contact zone

204: second initial doped region

AD: active (active) component

AR, AR-1: absorption zone

CF: color filter layer

CFB: blue light color filter pattern

CFG: green light color filter pattern

CFI: infrared light color filtering pattern

CFR: red light color filter pattern

CR: central zone

D1, D2, D3, D4, D5, D6, D7, D8: depth of field

DA. DA-1: depth of absorption

DE: drain electrode

D L dielectric layer

E1: a first electrode

E2: second electrode

EP: epitaxial layer

FI. FI-1: field doping region

GD: gate dielectric layer

GE: grid electrode

GS: grid structure

IS, ISa-1, ISb: isolation structure

L I lower spacer region

M: internal connection structure

M L microlens

PD: photodiode

PR: edge zone

R: region(s)

S100, S102a, S104, S106, S108, S110, S112, S114, S116, S118: step (ii) of

SB: substrate

And SE: source electrode

SP: spacer wall

T1, T2, T3, T4, T5: thickness of

UI (user interface): upper spacer region

W: semiconductor substrate

W1: width of

Detailed Description

Fig. 1 is a flow chart of a method of fabricating a semiconductor device according to some embodiments of the present invention. Fig. 2A to 2F are schematic cross-sectional views of structures at various stages in the method of manufacturing the semiconductor device shown in fig. 1.

Referring to fig. 1 and fig. 2A, step S100 is performed to provide a semiconductor substrate W. In some embodiments, the semiconductor substrate W is a semiconductor wafer. In other embodiments, the semiconductor substrate W is a semiconductor-on-insulator (SOI) wafer including a buried insulator layer. The semiconductor material in the semiconductor substrate W may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. The elemental semiconductor may comprise Si or Ge, for example. The alloy semiconductor may include SiGe, SiGeC, or the like. The compound semiconductor may include SiC, a III-V semiconductor material, or a II-VI semiconductor material. Further, the semiconductor material may be doped to the first conductivity type. In some embodiments, the first conductive type is P-type, but the embodiments of the invention are not limited thereto.

In some embodiments, the finally formed semiconductor device (e.g., the semiconductor device 10 shown in fig. 2F) has a central region CR and an edge region PR surrounding the central region CR. A plurality of photodiodes (such as photodiode PD shown in fig. 2F) are disposed in the central region CR, and no photodiode is disposed in the edge region PR. In such embodiments, the semiconductor substrate W and the material layers subsequently formed thereon may also be divided into a central region CR and an edge region PR.

Step S102 is performed to form a first preliminary doped region 102 in the semiconductor substrate W. The first initially doped region 102 has a second conductivity type complementary to the first conductivity type, for example, N-type. For example, the doping concentration of the first preliminary doping region 102 may be 10¹³cm^-2To 10¹⁶cm^-2Within the range of (1). In some embodiments, the first initially doped region 102 extends continuously within the central region CR without extending into the edge regions PR. In addition, the first initially doped region 102 is a shallow doped region. In some embodiments, the depth D1 from the top surface of the semiconductor substrate W to the top surface of the first initially doped region 102 is in the range of 0 μm to 1 μm. On the other hand, the thickness T1 of the first preliminary doped region 102 may be in the range of 10nm to 1 μm.

Referring to fig. 1 and 2B, step S104 is performed to form an epitaxial layer EP on the semiconductor substrate W. The semiconductor substrate W and the epitaxial layer EP may be collectively referred to as a base SB. In some embodiments, the epitaxial layer EP substantially entirely covers the semiconductor substrate W and extends in the central region CR and the edge region PR. In some embodiments, the thickness T2 of the epitaxial layer EP ranges from 4 μm to 8 μm. In addition, the epitaxial layer EP and the semiconductor substrate W both have a first conductivity type, for example, P-type. In some embodiments, the doping may be performed simultaneously in the epitaxial fabrication process used to form the epitaxial layer EP. In other embodiments, doping may also be performed after the epitaxial fabrication process, for example, by ion implantation (ion implantation). On the other hand, since the epitaxial process is performed at a high temperature (for example, 1000 ℃ to 1200 ℃), the semiconductor substrate W adjacent to the epitaxial layer EP is also heated. In this way, the first preliminary doped region 102 located in the semiconductor substrate W diffuses upward to extend into the epitaxial layer EP, thereby forming the first doped region 102 a. In other words, the first doped region 102a longitudinally crosses the interface of the semiconductor substrate W and the epitaxial layer EP. The first doped region 102a formed by this method may be located at the bottom of the epitaxial layer EP. In other words, the first doped region 102a of the present embodiment may have a relatively large depth D2 compared to the manner in which the doped region is formed directly in the epitaxial layer by ion implantation. In some embodiments, the depth D2 of the first doped region 102a is in the range of 3 μm to 6 μm. Furthermore, in some embodiments, the first initially doped region 102 may also slightly diffuse in other directions. In some embodiments, the thickness T3 of the first doped region 102a may be 0.5 μm to 4 μm.

Referring to fig. 1 and fig. 2C, step S106 is performed to form a plurality of second doped regions 104 in the epitaxial layer EP. The second doped region 104 and the first doped region 102a have a second conductivity type, such as N-type. In some embodiments, the doping concentration of the second doped region 104 is 10¹²cm^-2To 10¹⁴cm^-2Within the range of (1). In addition, the second doped region 104 is located near the bottom of the epitaxial layer EP and above the first doped region 102 a. For example, the depth D3 from the top surface of the epitaxial layer EP to the top surface of the second doped region 104 may be in the range of 1.5 μm to 3 μm, and the thickness T4 of the second doped region 104 may be in the range of 0.5 μm to 3 μm.

A plurality of second doped regions 104 are located in the central region CR and the edge region PR. A plurality of second doped regions 104 located within the central region CR are located between the top surface of the epitaxial layer EP and the first doped regions 102 a. Furthermore, the bottom surface of the second doped region 104 in the central region CR may contact the top surface of the first doped region 102 a. In some embodiments, the second doped region 104 located in the central region CR may further extend longitudinally into the first doped region 102 a. In such embodiments, the bottom surface of the second doped region 104 in the central region CR is lower than the top surface of the first doped region 102 a. In addition, the plurality of second doping regions 104 in the central region CR are separated from each other. The portion of the epitaxial layer EP located between adjacent second doped regions 104 may be referred to as an upper spacer region UI. The sidewalls of adjacent second doped regions 104 facing each other define the sides of the upper spacer area UI, while the top surface of the underlying first doped region 102a defines the bottom surface of the upper spacer area UI. In some embodiments, the width of the upper spacer UI is about the width of a single sub-pixel or a single sensing unit in the finally formed image sensor (e.g., the semiconductor device 10 of fig. 2F). For example, the width W1 of the upper spacer UI may be in the range of 1 μm to 6 μm. From another perspective, the upper spacer UI may also be regarded as an extension of the epitaxial layer EP extending to between two adjacent second doping regions 104. In addition, the upper spacer UI vertically overlaps some color filter patterns subsequently formed on the epitaxial layer EP. For example, the upper spacer UI vertically overlaps some color filter patterns (e.g., the red color filter pattern CFR shown in fig. 2F or the infrared color filter pattern CFI shown in fig. 4) having an absorption wavelength in the range of 620nm to 1000 nm. On the other hand, the edge region PR may have one or more second doped regions 104.

In some embodiments, the plurality of second doped regions 104 located in the central region CR and the edge region PR may be formed by an ion implantation process. In addition, the positions of the second doping regions 104 in the central region CR can be defined by a photoresist pattern (not shown) formed on the epitaxial layer EP during the ion implantation process.

Referring to fig. 1 and fig. 2D, step S108 is performed to form a plurality of field doping regions FI in the epitaxial layer EP. The field doping region FI and the epitaxial layer EP are both provided with a first conductivityType (for example P-type) and the doping concentration of the field doping region FI is higher than the doping concentration of the epitaxial layer EP. For example, the doping concentration of the field doping region FI is 10¹²cm^-2To 10¹⁴cm^-2Within the range of (1). In some embodiments, a plurality of field doping regions FI are disposed within the central region CR and separated from each other. The portion of the epitaxial layer EP located between two adjacent field doping regions FI may be used to form a plurality of photodiodes (e.g., the photodiode PD shown in fig. 2F) in a subsequent step. In some embodiments, field doping layer FI extends downward from the surface of epitaxial layer EP. In some embodiments, the depth D4 of field doping layer FI is in the range of 0 μm to 3 μm.

In some embodiments, a third doped region 106 may also be formed in the epitaxial layer EP, either before or after step S108. The first doped region 102a, the second doped region 104 and the third doped region 106 all have the second conductivity type, such as N-type. In some embodiments, the third doped region 106 has a doping concentration of 10¹²cm^-2To 10¹⁴cm^-2Within the range of (1). The third doped region 106 may be located within the central region CR and may be located outside the plurality of field doped regions FI. In some embodiments, the third doped region 106 may include a third doped region 106a and a third doped region 106 b. The third doped region 106a extends downward from the top surface of the epitaxial layer EP, and the third doped region 106b is connected between the third doped region 106a and the second doped region 104. In addition, the second doped region 104 is electrically connected to the first doped region 102 a. As such, the third doped region 106a, the third doped region 106b, the second doped region 104, and the first doped region 102a are electrically connected to each other and may be configured to receive a bias voltage, such as a positive bias voltage. In some embodiments, the top of the third doped region 106b may extend upward into the third doped region 106a, while the bottom of the third doped region 106b may extend downward into the second doped region 104.

In some embodiments, a fourth doped region 108 may also be formed in the epitaxial layer EP before or after step S108. The epitaxial layer EP and the fourth doped region 108 have the first conductivity type, such as P-type. For example, the doping concentration of the fourth doping region 108 is 10¹²cm^-2To 10¹⁴cm^-2Within the range of (1). In some embodiments, the fourth doped region 108 may include a fourth doped region 108a and a fourth doped region 108 b. The fourth doped region 108a is located within the central region CR and may be located between the third doped region 106a and the plurality of field doped regions FI. In some embodiments, the fourth doping region 108a may also extend laterally into the outermost field doping region FI. Since the epitaxial layer EP and the fourth doped region 108 have the same conductivity type, they can be electrically connected to each other and can be configured to receive a reference voltage or a negative bias voltage. On the other hand, the fourth doped region 108b is located in the edge region PR. In some embodiments, the fourth doped region 108b may laterally extend in a portion of the epitaxial layer EP located in the edge region PR, and may serve as a well region for an active device (e.g., the active device AD of fig. 2F) to be subsequently formed in the edge region PR.

Step S110 IS performed to form an isolation structure IS in the epitaxial layer EP. In some embodiments, isolation structure IS may include a plurality of isolation structures ISa and a plurality of isolation structures ISb. The isolation structures ISa are disposed in the central region CR and respectively located in the field doping regions FI. The isolation structures ISa may extend from the top surface of the epitaxial layer EP toward the inside of the epitaxial layer EP. In addition, the bottom surface of the isolation structure ISa is higher than the bottom surface of the field doping region FI. In other words, the depth D5 of the isolation structure ISa may be less than the depth D4 of the field doping region FI. For example, the depth D5 of the isolation structure ISa may be in a range of 250nm to 400 nm. The isolation structures ISa and the field doping regions FI may be combined to reduce crosstalk (crosstalk) between photodiodes (e.g., the photodiodes PD shown in fig. 2F) subsequently formed at two opposite sides of the isolation structures ISa. On the other hand, some of the isolation structures ISb are located in the central region CR, while other of the isolation structures ISb are located in the edge region PR. In some embodiments, the isolation structure ISb located within the central region CR may be disposed near an interface between the third doped region 106a and the fourth doped region 108 a. In such embodiments, the isolation structures ISb located within the central region CR may also extend laterally into the third doped region 106a and the fourth doped region 108 a. Furthermore, the isolation structures ISb located in the edge region PR may be disposed in the fourth doped region 108b separately from each other. In a subsequent manufacturing process, an active device (e.g., the active device AD shown in fig. 2F) may be formed between the adjacent isolation structures ISb. In some embodiments, the isolation structure IS (e.g., including the isolation structure ISa and the isolation structure ISb) IS a Shallow Trench Isolation (STI) structure. Furthermore, in some embodiments, the depth of the isolation structures ISb may be substantially equal to the depth of the isolation structures ISa.

In some embodiments, the method for forming the isolation structure IS may include forming a trench (not shown) on the surface of the epitaxial layer EP. Next, an insulating material IS formed in the trench by a method such as a chemical vapor deposition process to form an isolation structure IS.

Referring to fig. 1 and fig. 2E, step S112 is performed to form a plurality of photodiodes PD in the epitaxial layer EP. A plurality of photodiodes PD are disposed in the central region CR. In some embodiments, the photodiode PD is disposed on top of the epitaxial layer EP. In other words, the second doped region 104 may be located between the photodiode PD and the first doped region 102 a. In addition, the photodiode PD longitudinally overlaps the second doped region 104 and the first doped region 102 a. In some embodiments, a plurality of photodiodes PD may be respectively disposed between two adjacent field doping regions FI (i.e., between two isolation structures ISa). The photodiode PD may include a first electrode E1 and a second electrode E2. In some embodiments, the first electrode E1 and the second electrode E2 are both doped regions formed in the epitaxial layer EP. The first electrode E1 has a first conductivity type (e.g., P-type), and the second electrode E2 has a second conductivity type (e.g., N-type). In some embodiments, the doping concentration of the first electrode E1 is 10¹²cm^-2To 10¹⁵cm^-2And the doping concentration of the second electrode E2 is in the range of 10¹²cm^-2To 10¹⁴cm^-2Within the range of (1). In some embodiments, the first electrode E1 is disposed over the second electrode E2. In such embodiments, the first electrode E1 may extend from the top surface of the epitaxial layer EP to the interior of the epitaxial layer EP, and the second electrode E2 extends from the bottom surface of the first electrode E1. In some embodiments, the bottom surface of the first electrode E1 is higher than the bottom surface of the isolation structure ISa. In addition, the bottom surface of the second electrode E2 may be higher than the bottom surface of the field doping region FI and may be lower than the bottom surface of the isolation structure ISa.

In some embodiments, before or after step S112, a contact region 110a may be formed on top of the third doped region 106 a. In some embodiments, the contact region 110a is a doped region and extends downward from the top surface of the epitaxial layer EP. In some embodiments, the bottom surface of the contact region 110a is higher than the bottom surface of the isolation structure ISb and higher than the bottom surface of the third doped region 106 a. In addition, the contact region 110a has a second conductivity type (e.g., N-type) and is electrically connected to the third doped region 106, the second doped region 104 and the first doped region 102 a. In some embodiments, the contact region 110a is a heavily doped region. In such embodiments, the doping concentration of the contact region 110a is higher than the doping concentration of the third doping region 106. In this way, by providing the contact region 110a, the contact resistance between the third doped region 106 and the interconnect structure (e.g., the interconnect structure M shown in fig. 2F) subsequently formed on the epitaxial layer EP can be reduced. On the other hand, a contact region 110b may be formed on top of the fourth doped region 108 a. Similar to the contact region 110a, the contact region 110b may also be a doped region and extend downward from the top surface of the epitaxial layer EP. In some embodiments, the bottom surface of the contact region 110b is higher than the bottom surface of the isolation structure ISb (or the isolation structure ISa) and higher than the bottom surface of the fourth doped region 108 a. The contact region 110b has a first conductivity type (e.g., P-type) and is electrically connected to the fourth doped region 108a and the epitaxial layer EP. In some embodiments, the contact region 110b is a heavily doped region. In such embodiments, the doping concentration of the contact region 110b is higher than the doping concentration of the fourth doped region 108 a. In this way, by providing the contact region 110b, the contact resistance between the fourth doped region 108a and the interconnect structure (e.g., the interconnect structure M shown in fig. 2F) subsequently formed on the epitaxial layer EP can be reduced.

In some embodiments, the active device AD may be formed in the edge region PR before or after step S112. Each active device AD may be located between adjacent isolation structures ISb. For example, the active device AD may be a field effect transistor. In some embodiments, the active device AD may include a gate structure GS, a drain DE, and a source SE. The gate structure GS may be located on the epitaxial layer EP and includes a gate GE, a gate dielectric layer GD, and a spacer SP. Gate dielectric layer GD is located between gate GE and the top surface of epitaxial layer EP, and spacer SP surrounds gate GE and gate dielectric layer GD. On the other hand, the drain DE and the source SE may be disposed in the epitaxial layer EP and located at two opposite sides of the gate structure GS. In some embodiments, the drain DE and the source SE are disposed in the fourth doped region 108 b. The drain DE and the source SE have the same conductivity type, and the conductivity type may be complementary to the conductivity type of the fourth doped region 108 b. For example, the drain DE and the source SE have the second conductivity type (e.g., N-type), and the fourth doped region 108b has the first conductivity type (e.g., P-type). In other embodiments, the active device AD may further include a diode, a Bipolar Junction Transistor (BJT), the like, or a combination thereof. One skilled in the art can select the type and configuration of the active devices AD according to the design requirement, and the embodiments of the invention are not limited thereto.

Referring to fig. 1 and 2F, step S114 is performed to form a plurality of dielectric layers D L and an interconnection structure M on the epitaxial layer EP, fig. 2F schematically illustrates a plurality of dielectric layers D L and an interconnection structure M, a dielectric layer D L and an interconnection structure M formed in the central region CR and the edge region PR, a plurality of dielectric layers D L may be stacked on the epitaxial layer EP, and an interconnection structure M may be formed in the plurality of dielectric layers D L, a plurality of photodiodes PD may be electrically connected to a logic circuit (not shown) through the interconnection structure M, furthermore, the interconnection structure M may be electrically connected to the contact region 110a, the contact region 110b and the active element AD., in some embodiments, a portion of the dielectric layer D L vertically overlapping the photodiodes PD (e.g., the region R shown in fig. 2F) may not have an interconnection structure.

Proceeding to step S116, a color filter layer CF is formed on the uppermost dielectric layer D L, the color filter layer CF is formed in the central region CR and overlaps the photodiodes PD.. in some embodiments, the color filter layer CF may include a plurality of color filter patterns, including, for example, a blue color filter pattern CFB, a green color filter pattern CFG, and a red color filter pattern CFR. in some embodiments, the blue color filter pattern CFB has a transmission band of 476nm to 495nm, the green color filter pattern CFG has a transmission band of 495nm to 570nm, the red color filter pattern CFR has a transmission band of 620nm to 750nm, the plurality of color filter patterns respectively longitudinally overlap the photodiodes PD. such that only incident light of a specific band can transmit the color filter pattern of a specific color, then pass through the region R of the dielectric layer D L and enter the photodiodes PD.. each photodiode PD is configured to receive light of a specific band and convert it into an electrical signal.

Step S118 is performed to form a plurality of microlenses M L on the color filter layer CF. the plurality of microlenses M L may longitudinally overlap the plurality of color filter patterns and longitudinally overlap the plurality of photodiodes PD.

Thus, the semiconductor device 10 according to some embodiments of the present invention has been completed. The semiconductor device 10 may be used as an image sensor. The semiconductor device 10 includes a first doped region 102a and a second doped region 104 disposed in the epitaxial layer EP. By subjecting the first and second

doped regions

102a and 104 to a positive bias, electrons generated deep in the epitaxial layer EP by incident light of a long wavelength can be guided and exit the epitaxial layer EP. In this way, the crosstalk between adjacent sub-pixels can be further reduced. On the other hand, by making the fourth doping region 108a disposed in the epitaxial layer EP receive a reference voltage or a negative voltage, holes generated deep in the epitaxial layer EP by long wavelength incident light can be guided away from the epitaxial layer EP. In addition, for incident light of a long wavelength (e.g., red light passing through the red color filter pattern CFR), a large absorption depth is required to achieve a sufficient quantum efficiency (quantum efficiency) of the corresponding photodiode PD. The absorption depth described herein refers to the thickness of the portion of the epitaxial layer EP longitudinally overlapping the photodiode PD, and this portion does not include the first doped region 102a and the second doped region 104. The second doped regions 104 of the embodiment of the invention are separately disposed in the epitaxial layer EP, and a gap between adjacent second doped regions 104 longitudinally overlaps with the color filter pattern capable of transmitting long-wavelength light. Therefore, the incident light with long wavelength can enter the absorption region with larger absorption depth. For example, the upper spacer UI of the epitaxial layer EP between the adjacent second doped regions 104 longitudinally overlaps the red color filter pattern CFR to allow the red light to enter the absorption region AR having the larger absorption depth DA. Therefore, the quantum efficiency of the corresponding photodiode PD can be improved.

Fig. 3 is a schematic cross-sectional view of the central region CR of the semiconductor assembly 10a according to some embodiments of the present invention. The semiconductor device 10a shown in fig. 3 is similar to the semiconductor device 10 shown in fig. 2F, and only the differences between the two will be described below, and the same or similar parts will not be repeated. Further, the same or similar reference numerals denote the same or similar components.

Referring to fig. 3, the isolation structure ISa-1 of the semiconductor device 10a is a Deep Trench Isolation (DTI) structure. The depth D6 of the isolation structure ISa-1 may be greater than the depth of the photodiode PD. In some embodiments, the isolation structure ISa-1 may extend longitudinally to contact the top surface of the second doped region 104. In other embodiments, the bottom surface of the isolation structure ISa-1 is higher than the top surface of the second doped region 104. In other embodiments, the isolation structure ISa-1 may also extend into the second doped region 104, or may also extend into the first doped region 102 a. For example, the depth D6 of the isolation structure ISa-1 may be in the range of 1 μm to 8 μm. In the embodiment shown in fig. 3, the field doping region FI-1 also has a larger depth. In some embodiments, the field doping region FI-1 may extend into the second doping region 104, or may also extend into the first doping region 102 a. In other embodiments, the bottom surface of the field doping region FI-1 may also be higher than or contact the top surface of the second doping region 104, or may be higher than or contact the top surface of the first doping region 102 a. For example, the depth D7 of the field doping region FI-1 may be in the range of 1.2 μm to 8.5 μm.

By increasing the depth of the isolation structure and the field doping region between adjacent photodiodes PD, the crosstalk between adjacent photodiodes PD or adjacent sub-pixels can be further reduced.

Fig. 4 is a schematic cross-sectional view of the central region CR of the semiconductor assembly 10b in accordance with some embodiments of the present invention. The semiconductor device 10b shown in fig. 4 is similar to the semiconductor device 10 shown in fig. 2F, and only the differences between the two will be described below, and the same or similar parts will not be repeated. Further, the same or similar reference numerals denote the same or similar components.

Referring to fig. 4, the color filter layer CF-1 of the semiconductor device 10b further includes an infrared light color filter pattern CFI, in some embodiments, a transmission wavelength band of the infrared light color filter pattern CFI is 760nm to 1000nm, and in addition, the semiconductor device 10b includes a plurality of first doped regions 102a, a plurality of first doped regions 102a are separated from each other, a portion of the epitaxial layer EP and the semiconductor substrate W between the adjacent first doped regions 102a may be referred to as lower spacers L I, some upper spacers UI respectively between two adjacent second doped regions 104 are longitudinally connected to the lower spacers L I, and other upper spacers UI do not longitudinally overlap the lower spacers L I, in some embodiments, some upper spacers UI and lower spacers L I longitudinally overlapping each other longitudinally overlap the color filter pattern CFI, and other some upper spacers not longitudinally overlapping the lower infrared light spacers L I are longitudinally overlapped the red light color filter pattern CFR.

In the embodiment shown in FIG. 4, the infrared light enters the absorption region AR-1 having a greater absorption depth DA-1. Thus, the quantum efficiency of the photodiode PD longitudinally overlapped with the infrared light color filter pattern CFI can be further improved.

Fig. 5 is a schematic cross-sectional view of the central region CR of the semiconductor assembly 10c in accordance with some embodiments of the present invention. The semiconductor device 10c shown in fig. 5 is similar to the semiconductor device 10b shown in fig. 4. Specifically, the semiconductor device 10c shown in fig. 5 can be regarded as a semiconductor device 10b shown in fig. 4, in which the deep trench isolation structure ISa-1 and the field doping region FI-1 shown in fig. 3 are respectively substituted for the shallow trench isolation structure ISa and the field doping region FI.

Fig. 6 is a flow chart of a method of manufacturing a semiconductor device 20 according to some embodiments of the present invention.

Fig. 7A to 7C are schematic cross-sectional views of the structure at various stages in the method of manufacturing the semiconductor assembly 20 shown in fig. 6. The semiconductor device 20 shown in fig. 6 and 7A to 7C and the manufacturing method thereof are similar to the semiconductor device 10 shown in fig. 1 and 2A to 2F and the manufacturing method thereof, and only the differences therebetween will be described below, and the same or similar parts will not be repeated. Further, the same or similar reference numerals denote the same or similar components.

Referring to fig. 6 and 7A, after the step S100, a step S102a is performed to form a first preliminary doped region 102 and a plurality of second preliminary doped regions 204 in the semiconductor substrate W. The first preliminary doped regions 102 and the plurality of second preliminary doped regions 204 have a second conductivity type, such as N-type. In some embodiments, the first initially doped region 102 and the plurality of second initially doped regions 204 are located in the central region CR. A plurality of second preliminary doped regions 204 are located between the top surface of the semiconductor substrate W and the first preliminary doped regions 102. Furthermore, in some embodiments, the plurality of second preliminary doped regions 204 may contact the first preliminary doped region 102. In other embodiments, the plurality of second preliminary doping regions 204 may also be higher than the first preliminary doping region 102 and do not contact the first preliminary doping region 102.

Referring to fig. 6 and 7B, step S104 is performed to form an epitaxial layer EP on the semiconductor substrate W. During the formation of the epitaxial layer EP, the semiconductor substrate W is heated to diffuse the first preliminary doping region 102 and the plurality of second preliminary doping regions 204 upward to extend into the epitaxial layer EP. In this way, the first doped region 102a and the plurality of second doped regions 204a can be formed. The top surfaces of the second doped regions 204a are higher than the top surfaces of the first doped regions 102a, and the bottom surfaces of the second doped regions 204a are located in the first doped regions 102 a. In some embodiments, the plurality of second doped regions 204a may be considered to extend longitudinally into the first doped region 102 a. In some embodiments, the depth D8 of the second doped region 204a is in the range of 2 μm to 4 μm. Furthermore, in some embodiments, the thickness T5 of the second doped region 204a may be 1 μm to 4 μm.

Referring to fig. 6 and 7C, steps S106 to S118 are sequentially performed to complete the fabrication of the semiconductor device 20. The difference between the semiconductor device 20 and the semiconductor device 10 shown in fig. 2F mainly lies in the location and the formation method of the second doped region. The semiconductor device 20 may also reduce cross-talk between adjacent sub-pixels. In addition, the incident light with long wavelength can enter the absorption region AR with larger absorption depth DA, and the quantum efficiency of the sub-pixel with long wavelength is improved. In the embodiment shown in fig. 7C, the upper spacer UI of the epitaxial layer EP between two adjacent second doped regions 204a may overlap color filter patterns capable of transmitting wavelengths in the range of 620nm to 1000nm, such as a red color filter pattern CFR and an infrared color filter pattern CFI.

Fig. 8 is a schematic cross-sectional view of the central region CR of the semiconductor assembly 20a according to some embodiments of the present invention. The semiconductor device 20a shown in fig. 8 is similar to the semiconductor device 20 shown in fig. 7C. Specifically, the semiconductor device 20a shown in fig. 8 can be regarded as a semiconductor device 20 shown in fig. 7C, in which the deep trench isolation structure ISa-1 and the field doping region FI-1 shown in fig. 3 are respectively substituted for the shallow trench isolation structure ISa and the field doping region FI.

Fig. 9 is a schematic cross-sectional view of a central region CR of a semiconductor device 20b according to some embodiments of the invention, the semiconductor device 20b shown in fig. 9 is similar to the semiconductor device 20 shown in fig. 7C, specifically, the semiconductor device 20b shown in fig. 9 can be regarded as replacing the single first doped region 102a of the semiconductor device 20 shown in fig. 7C with the plurality of first doped regions 102a shown in fig. 4, and further, the upper and lower spacer regions UI and L I of the epitaxial layer EP, which are communicated with each other, longitudinally overlap the infrared light color filter pattern CFI, and the upper spacer region UI, which is not communicated with the lower spacer region L I downwards, longitudinally overlaps the red light color filter pattern CFR.

Fig. 10 is a schematic cross-sectional view of the central region CR of the semiconductor assembly 20c in accordance with some embodiments of the present invention. The semiconductor device 20C shown in fig. 10 is similar to the semiconductor device 20 shown in fig. 7C. Specifically, the semiconductor device 20C shown in fig. 10 can be regarded as a semiconductor device 20 shown in fig. 7C, in which the deep trench isolation structure ISa-1 and the field doping region FI-1 shown in fig. 3 are respectively substituted for the shallow trench isolation structure ISa and the field doping region FI.

In summary, the semiconductor device of the embodiment of the invention can be used as an image sensor and includes a first doped region and a plurality of second doped regions embedded in a substrate and electrically connected to each other. By making the first doped region and the second doped region receive a bias voltage, carriers formed inside the substrate can be guided to leave the substrate through the first doped region and the second doped region. Thus, crosstalk between adjacent sub-pixels can be reduced. In addition, the plurality of second doped regions above the first doped region are separated from each other, and a portion of the substrate extending between two adjacent second doped regions longitudinally overlaps the sub-pixel with the long wavelength. Therefore, the absorption depth of the absorption region through which the long-wavelength incident light passes can be increased. Therefore, the quantum efficiency of the long wavelength sub-pixel can be improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A semiconductor assembly, comprising:

a substrate having a first conductivity type;

a plurality of photodiodes extending from a top surface of the substrate to an interior of the substrate;

a plurality of color filter patterns disposed on the substrate and longitudinally overlapped with the plurality of photodiodes, respectively;

a first doped region disposed in the substrate and having a second conductivity type; and

a plurality of second doped regions disposed in the substrate and having the second conductivity type, wherein the second doped regions are in contact with the first doped regions and located between the photodiodes and the first doped regions, an upper spacer region is disposed between every two adjacent second doped regions, and the upper spacer regions longitudinally overlap several of the color filter patterns having a transmission wavelength in a range of 620nm to 1000 nm.

2. The semiconductor device of claim 1, wherein the substrate comprises a semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate, the first doped region extends from within the semiconductor substrate into a bottom of the epitaxial layer, and the plurality of second doped regions are located within the epitaxial layer.

3. The semiconductor device of claim 1, wherein the first doped region extends continuously and vertically overlaps the plurality of second doped regions and the plurality of photodiodes.

4. The semiconductor assembly of claim 3, wherein a top surface of the first doped region defines a bottom surface of the plurality of upper spacer regions.

5. The semiconductor device as claimed in claim 1, wherein the number of the first doped regions is a plurality, a lower spacer region is disposed between every two adjacent first doped regions, and the plurality of lower spacer regions are respectively longitudinally connected to a plurality of the plurality of upper spacer regions.

6. The semiconductor device according to claim 5, wherein the plurality of lower spacers vertically overlap ones of the plurality of color filter patterns having a transmission wavelength in a range of 760nm to 1000 nm.

7. The semiconductor assembly of claim 1, wherein the plurality of second doped regions extend into the first doped region.

8. The semiconductor device of claim 1, further comprising a third doped region disposed in the substrate and having the second conductivity type, wherein the third doped region is electrically connected to the plurality of second doped regions and the first doped region.

9. The semiconductor device of claim 1, further comprising a plurality of isolation structures extending from the top surface of the substrate to the interior of the substrate and respectively located between two adjacent photodiodes.

10. The semiconductor assembly of claim 9, wherein a depth of the plurality of isolation structures is less than a depth of the plurality of photodiodes.

11. The semiconductor assembly of claim 9, wherein a depth of the plurality of isolation structures is greater than a depth of the plurality of photodiodes.

12. The semiconductor device of claim 9, further comprising a plurality of field doping regions disposed in the substrate and having the first conductivity type, wherein the plurality of isolation structures are located in the plurality of field doping regions.

13. A method of manufacturing a semiconductor assembly, comprising:

forming a first initial doped region within a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type and the first initial doped region has a second conductivity type;

forming an epitaxial layer on the semiconductor substrate and diffusing the first preliminary doped region upward to extend into the epitaxial layer to form a first doped region, wherein the epitaxial layer has the first conductivity type;

forming a plurality of second doped regions of the second conductivity type in the epitaxial layer, wherein the plurality of second doped regions contact the first doped region and are located between the top surface of the epitaxial layer and the first doped region;

forming a plurality of photodiodes in the epitaxial layer, wherein the plurality of second doped regions are located between the plurality of photodiodes and the first doped region;

forming a plurality of color filter patterns on the epitaxial layer, wherein the plurality of color filter patterns overlap the plurality of photodiodes, respectively,

wherein, an upper spacing region is arranged between every two adjacent second doping regions, and a plurality of the upper spacing regions vertically overlap a plurality of color filter patterns with several ones having the transmission wavelength in the range of 620nm to 1000 nm.

14. The method of claim 13, wherein the plurality of second doped regions are in the epitaxial layer and the semiconductor substrate, and the method of forming the plurality of second doped regions comprises:

forming a plurality of second initially doped regions in the semiconductor substrate after forming the first initially doped regions, wherein the plurality of second initially doped regions are located between the top surface of the semiconductor substrate and the first initially doped regions, and wherein the plurality of second initially doped regions diffuse upward to extend into the epitaxial layer while forming the epitaxial layer to form the plurality of second doped regions.

15. The method according to claim 13, wherein the first initial doping regions and the first doping regions are respectively plural in number, and wherein a lower spacer is provided between two adjacent first doping regions, and a plurality of the lower spacers vertically overlap with some of the plurality of upper spacers and vertically overlap with some of the plurality of color filter patterns having a transmission wavelength in a range of 760nm to 1000 nm.

16. The method of manufacturing a semiconductor assembly according to claim 13, further comprising:

forming a third doped region of the second conductivity type in the epitaxial layer, wherein the third doped region is electrically connected to the plurality of second doped regions and the first doped region.