TW202029518A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device and manufacturing method thereof are provided. The semiconductor device includes a substrate, a first and second doped regions, photodiodes and color filter patterns. The first doped region, the second doped regions and the photodiodes are formed in the substrate, and the color filter patterns are formed over the substrate. The substrate has a first conductive type, and the first and second doped regions have a second conductive type. The photodiodes extends from a top surface of the substrate into the substrate. The color filter patterns vertically overlap with the photodiodes, respectively. The second doped regions are contacted with the first doped region, and located between the photodiodes and the first doped region. Upper intermediate regions of the substrate are respectively located between two adjacent second doped regions, and the upper intermediate regions vertically overlap with some of the color filter patterns of which a transmittance wavelength ranges from 620 nm to 1000 nm.

Description

Semiconductor element and its manufacturing method

The present invention relates to a semiconductor device and its manufacturing method, and more particularly to an image sensor and its manufacturing method.

An image sensor made by a semiconductor process can be used to sense light incident on the substrate. The image sensor uses an array of sensing units to receive light energy and convert it into a digital signal. However, because the substrate has different absorption depths for light of different wavelengths, there will be different degrees of crosstalk between the sensing units. Specifically, the substrate needs to have a larger absorption depth for incident light with a longer wavelength to increase the absorption efficiency of photons. The carriers generated by incident light deep in the substrate are far away from the electric field range of the sensing unit, and can diffuse to the neighboring sensing units of other colors. As a result, the sensing units of various colors cannot absorb the carriers generated only by the corresponding colored light, resulting in sensing errors.

The invention provides a semiconductor element and a manufacturing method thereof. The semiconductor device can be used as an image sensor, and can reduce crosstalk between adjacent sensing units.

The semiconductor device of the present invention includes a substrate, a plurality of photodiodes, a plurality of color filter patterns, a first doped region and a plurality of second doped regions. The substrate has a first conductivity type. A plurality of photodiodes extend from the top surface of the substrate to the inside of the substrate. A plurality of color filter patterns are arranged on the substrate, and are respectively longitudinally overlapped on the plurality of photodiodes. The first doped region is disposed in the substrate and has a second conductivity type. A plurality of second doped regions are arranged in the substrate and have the second conductivity type. The plurality of second doped regions are in contact with the first doped region and are located between the plurality of photodiodes and the first doped region. There is an upper spacer region between two adjacent second doped regions, and the plurality of upper spacer regions are longitudinally overlapped with a plurality of color filter patterns having a transmission wavelength in the range of 620 nm to 1000 nm.

In some embodiments, the base includes a semiconductor substrate and an epitaxial layer. The epitaxial layer is arranged on the semiconductor substrate. The first doped region extends from the semiconductor substrate to the bottom of the epitaxial layer, and a plurality of second doped regions are located in the epitaxial layer.

In some embodiments, the first doped region extends continuously and vertically overlaps the plurality of second doped regions and the plurality of photodiodes.

In some embodiments, the top surface of the first doped region defines the bottom surface of a plurality of upper spacer regions.

In some embodiments, the number of the first doped regions is a majority. There is a lower spacer between the two adjacent first doped regions, and the plurality of lower spacers are respectively longitudinally connected to some of the plurality of upper spacers.

In some embodiments, the plurality of lower spacers vertically overlap one of the plurality of color filter patterns with a transmission wavelength in the range of 760 nm to 1000 nm.

In some embodiments, the plurality of second doped regions extend into the first doped regions.

In some embodiments, the semiconductor device further includes a third doped region. The third doped region is disposed in the substrate and has the second conductivity type. The third doped region is electrically connected to the plurality of second doped regions and the first doped region.

In some embodiments, the semiconductor device further includes a plurality of isolation structures, which extend from the top surface of the substrate to the inside of the substrate, and are respectively located between two adjacent photodiodes.

In some embodiments, the depth of the plurality of isolation structures is less than the depth of the plurality of photodiodes.

In some embodiments, the depth of the plurality of isolation structures is greater than the depth of the plurality of photodiodes.

In some embodiments, the semiconductor device further includes a plurality of field doped regions, which are disposed in the substrate and have the first conductivity type. Multiple isolation structures are located in multiple field doping regions.

The manufacturing method of the semiconductor element of the embodiment of the present invention includes: forming a first initial doping region in a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type, and the first initial doping region has a second conductivity type; on the semiconductor substrate An epitaxial layer is formed, and the first initial doped region is diffused upward to extend into the epitaxial layer to form a first doped region, wherein the epitaxial layer has a first conductivity type; and the epitaxial layer is formed with a second A plurality of second doped regions of conductivity type, wherein the plurality of second doped regions are in contact with the first doped region and are located between the top surface of the epitaxial layer and the first doped region; formed in the epitaxial layer A plurality of photodiodes, wherein a plurality of second doped regions are located between the plurality of photodiodes and the first doped region; a plurality of color filter patterns are formed on the epitaxial layer, wherein a plurality of color filters The patterns overlap multiple photodiodes respectively. There is an upper spacer region between two adjacent second doped regions, and the plurality of upper spacer regions are vertically overlapped in the plurality of color filter patterns and have a transmission wavelength in the range of 620 to 1000 nm.

In some embodiments, the plurality of second doped regions are located in the epitaxial layer and the semiconductor substrate. The method of forming a plurality of second doped regions includes forming a plurality of second preliminary doped regions in a semiconductor substrate after forming the first preliminary doped regions. The plurality of second initial doping regions are located between the top surface of the semiconductor substrate and the first initial doping region. When the epitaxial layer is formed, the plurality of second initial doped regions diffuse upward to extend into the epitaxial layer to form a plurality of second doped regions.

In some embodiments, the numbers of the first initial doping region and the first doping region are respectively a majority. There is a lower spacer between two adjacent first doped regions, and a plurality of lower spacers vertically overlaps some of the plurality of upper spacers, and vertically overlaps a plurality of color filter patterns The transmission wavelength is in the range of 760 nm to 1000 nm.

In some embodiments, the manufacturing method of the semiconductor device further includes: forming a third doped region having the second conductivity type in the epitaxial layer. The third doped region is electrically connected to the plurality of second doped regions and the first doped region.

Based on the above, the semiconductor device of the embodiment of the present invention can be used as an image sensor, and includes a first doped region and a plurality of second doped regions that are embedded in a substrate and electrically connected to each other. By making the first doped region and the second doped region receive a bias voltage, the carriers formed inside the substrate can be guided to leave the substrate through the first doped region and the second doped region. In this way, the crosstalk between adjacent sub-pixels (or sensing units) can be reduced. In addition, the plurality of second doped regions located above the first doped region are separated from each other, and the part of the substrate extending between two adjacent second doped regions longitudinally overlaps the long-wavelength sub-pixels. In this way, the absorption depth of the absorption region through which long-wavelength incident light passes can be increased. Therefore, the quantum efficiency of the long-wavelength sub-pixel can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

FIG. 1 is a flowchart of a method of manufacturing a semiconductor device according to some embodiments of the present invention. 2A to 2F are schematic cross-sectional views of the structure at each stage in the method of manufacturing the semiconductor device shown in FIG. 1.

1 and 2A, step S100 is performed to provide a semiconductor substrate W. In some embodiments, the semiconductor substrate W is a semiconductor wafer. In other embodiments, the semiconductor substrate W is a semiconductor-on-insulator (SOI) wafer including a buried insulating layer. The semiconductor material in the semiconductor substrate W may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, and the like. The compound semiconductor may include SiC, a group III-V semiconductor material, or a group II-VI semiconductor material. In addition, the semiconductor material may be doped into the first conductivity type. In some embodiments, the first conductivity type is P-type, but the embodiments of the present invention are not limited to this.

In some embodiments, the final semiconductor element (the semiconductor element 10 shown in FIG. 2F) has a central region CR and an edge region PR surrounding the central region CR. A plurality of photodiodes (photodiodes PD as shown in FIG. 2F) are arranged in the central region CR, while no photodiodes are arranged in the edge region PR. In these embodiments, the semiconductor substrate W and the material layer subsequently formed thereon can also be divided into a central region CR and an edge region PR.

Step S102 is performed to form a first initial doped region 102 in the semiconductor substrate W. The first initial doped region 102 has a second conductivity type complementary to the first conductivity type, for example, an N type. For example, the doping concentration of the first initial doping region 102 may be in the range of 10 ¹³ cm ^-2 to 10 ¹⁶ cm ^-2 . In some embodiments, the first initial doping region 102 continuously extends in the central region CR, but does not extend into the edge region PR. In addition, the first initial doped region 102 is a shallow doped region. In some embodiments, the depth D1 from the top surface of the semiconductor substrate W to the top surface of the first initial doping region 102 is in the range of 0 μm to 1 μm. On the other hand, the thickness T1 of the first initial doping region 102 may be in the range of 10 nm to 1 μm.

1 and FIG. 2B, step S104 is performed to form an epitaxial layer EP on the semiconductor substrate W. The semiconductor substrate W and the epitaxial layer EP may be collectively labeled as the base SB. In some embodiments, the epitaxial layer EP substantially completely covers the semiconductor substrate W, and extends in the central region CR and the edge region PR. In some embodiments, the thickness T2 of the epitaxial layer EP ranges from 4 μm to 8 μm. In addition, both the epitaxial layer EP and the semiconductor substrate W have the first conductivity type, for example, the P type. In some embodiments, the doping can be performed simultaneously during the epitaxial process for forming the epitaxial layer EP. In other embodiments, the doping may be performed after the epitaxial process, for example, by ion implantation. On the other hand, since the epitaxial process is performed at a high temperature (for example, 1000° C. to 1200° C.), the semiconductor substrate W adjacent to the epitaxial layer EP will also be heated. In this way, the first initial doped region 102 located in the semiconductor substrate W will diffuse upward to extend into the epitaxial layer EP to form the first doped region 102a. In other words, the first doped region 102a longitudinally crosses the interface between the semiconductor substrate W and the epitaxial layer EP. The first doped region 102a formed by this method may be located at the bottom of the epitaxial layer EP. In other words, compared to the method of directly forming the doped region in the epitaxial layer by ion implantation, the first doped region 102a of the embodiment of the present invention may have a considerable depth D2. In some embodiments, the depth D2 of the first doped region 102a is in the range of 3 μm to 6 μm. In addition, in some embodiments, the first initial doped region 102 also slightly diffuses in other directions. In some embodiments, the thickness T3 of the formed first doped region 102a may be 0.5 μm to 4 μm.

1 and 2C, step S106 is performed to form a plurality of second doped regions 104 in the epitaxial layer EP. Both the second doped region 104 and the first doped region 102a have a second conductivity type, for example, an N-type. In some embodiments, the doping concentration of the second doping region 104 is in the range of 10 ¹² cm ^-2 to 10 ¹⁴ cm ^-2 . In addition, the second doped region 104 is located close to the bottom of the epitaxial layer EP and above the first doped region 102a. For example, the depth D3 from the top surface of the epitaxial layer EP to the top surface of the second doped region 104 may be in the range of 1.5 μm to 3 μm, and the thickness T4 of the second doped region 104 may be 0.5 μm To 3 μm.

The plurality of second doped regions 104 are located in the central region CR and the edge region PR. The plurality of second doped regions 104 in the central region CR are located between the top surface of the epitaxial layer EP and the first doped region 102a. Furthermore, the bottom surface of the second doped region 104 located in the central region CR may be in contact with the top surface of the first doped region 102a. In some embodiments, the second doped region 104 located in the central region CR may further extend longitudinally into the first doped region 102a. In these embodiments, the bottom surface of the second doped region 104 located in the central region CR is lower than the top surface of the first doped region 102a. In addition, the plurality of second doped regions 104 in the central region CR are separated from each other. The part of the epitaxial layer EP located between the adjacent second doped regions 104 may be referred to as an upper spacer region UI. The sidewalls of the adjacent second doped regions 104 facing each other define the side surfaces of the upper spacer region UI, and the top surface of the underlying first doped region 102a defines the bottom surface of the upper spacer region UI. In some embodiments, the width of the upper spacer UI is approximately the width of a single sub-pixel or a single sensing unit in the finally formed image sensor (for example, the semiconductor device 10 of FIG. 2F). For example, the width W1 of the upper spacer UI may be in the range of 1 μm to 6 μm. From another perspective, the upper spacer UI can also be regarded as an extension of the epitaxial layer EP extending between two adjacent second doped regions 104. In addition, the upper spacer UI vertically overlaps certain color filter patterns subsequently formed on the epitaxial layer EP. For example, the upper spacer UI vertically overlaps some color filter patterns with absorption wavelengths in the range of 620 nm to 1000 nm (for example, the red color filter pattern CFR shown in FIG. 2F or the color filter pattern shown in FIG. 4 Infrared color filter pattern CFI). On the other hand, the edge region PR may have one or more second doped regions 104.

In some embodiments, a plurality of second doped regions 104 in the central region CR and the edge region PR may be formed by an ion implantation process. In addition, during the ion implantation process, the positions of the plurality of second doped regions 104 in the central region CR can be defined by the photoresist pattern (not shown) formed on the epitaxial layer EP.

1 and 2D, step S108 is performed to form a plurality of field doped regions FI in the epitaxial layer EP. Both the field doping region FI and the epitaxial layer EP have the first conductivity type (for example, P type), and the doping concentration of the field doping region FI is higher than the doping concentration of the epitaxial layer EP. For example, the doping concentration of the field doping region FI is in the range of 10 ¹² cm ^-2 to 10 ¹⁴ cm ^-2 . In some embodiments, a plurality of field doping regions FI are disposed in the central region CR and separated from each other. The part of the epitaxial layer EP located between the two adjacent field doped regions FI can be used to form a plurality of photodiodes (for example, the photodiode PD shown in FIG. 2F) in a subsequent step. In some embodiments, the field doping layer FI extends downward from the surface of the epitaxial layer EP. In some embodiments, the depth D4 of the field doping layer FI is in the range of 0 μm to 3 μm.

In some embodiments, before or after step S108, a third doped region 106 may be formed in the epitaxial layer EP. The first doped region 102a, the second doped region 104, and the third doped region 106 all have the second conductivity type, for example, the N-type. In some embodiments, the doping concentration of the third doping region 106 is in the range of 10 ¹² cm ^-2 to 10 ¹⁴ cm ^-2 . The third doped region 106 may be located in the central region CR, and may be located outside the plurality of field doped regions FI. In some embodiments, the third doped region 106 may include a third doped region 106a and a third doped region 106b. The third doped region 106a extends downward from the top surface of the epitaxial layer EP, and the third doped region 106b is connected between the third doped region 106a and the second doped region 104. In addition, the second doped region 104 is electrically connected to the first doped region 102a. In this way, the third doped region 106a, the third doped region 106b, the second doped region 104, and the first doped region 102a are electrically connected to each other, and can be configured to receive a bias voltage, such as a positive bias voltage . In some embodiments, the top of the third doped region 106b may extend upward into the third doped region 106a, and the bottom of the third doped region 106b may extend downward into the second doped region 104.

In some embodiments, before or after step S108, a fourth doped region 108 may be formed in the epitaxial layer EP. Both the epitaxial layer EP and the fourth doped region 108 have the first conductivity type, for example, the P type. For example, the doping concentration of the fourth doping region 108 is in the range of 10 ¹² cm ^-2 to 10 ¹⁴ cm ^-2 . In some embodiments, the fourth doped region 108 may include a fourth doped region 108a and a fourth doped region 108b. The fourth doped region 108a is located in the central region CR, and may be located between the third doped region 106a and the plurality of field doped regions FI. In some embodiments, the fourth doped region 108a may further extend laterally into the outermost field doped region FI. Since the epitaxial layer EP and the fourth doped region 108 have the same conductivity type, they can be electrically connected to each other, and can be configured to receive a reference voltage or a negative bias voltage. On the other hand, the fourth doped region 108b is located in the edge region PR. In some embodiments, the fourth doped region 108b can extend laterally in the portion of the epitaxial layer EP located in the edge region PR, and can be used as an active element subsequently formed in the edge region PR (for example, as shown in FIG. 2F Active component AD) well area.

Step S110 is performed to form an isolation structure IS in the epitaxial layer EP. In some embodiments, the isolation structure IS may include a plurality of isolation structures ISa and a plurality of isolation structures ISb. The plurality of isolation structures ISa are disposed in the central region CR, and are respectively located in the plurality of field doping regions FI. The isolation structure ISa may extend from the top surface of the epitaxial layer EP to the inside of the epitaxial layer EP. In addition, the bottom surface of the isolation structure ISa is higher than the bottom surface of the field doping region FI. In other words, the depth D5 of the isolation structure ISa may be smaller than the depth D4 of the field doping region FI. For example, the depth D5 of the isolation structure ISa may be in the range of 250 nm to 400 nm. The isolation structure ISa and the field doped region FI can jointly reduce crosstalk between photodiodes (for example, the photodiodes PD shown in FIG. 2F) formed on opposite sides of the isolation structure ISa. On the other hand, some isolation structures ISb are located in the central region CR, while other isolation structures ISb are located in the edge region PR. In some embodiments, the isolation structure ISb located in the central region CR may be disposed near the interface between the third doped region 106a and the fourth doped region 108a. In these embodiments, the isolation structure ISb located in the central region CR may further extend laterally into the third doped region 106a and the fourth doped region 108a. In addition, the isolation structures ISb located in the edge region PR may be separately disposed in the fourth doped region 108b. In the subsequent manufacturing process, an active device (for example, the active device AD shown in FIG. 2F) may be formed between adjacent isolation structures ISb. In some embodiments, the isolation structure IS (for example, including the isolation structure ISa and the isolation structure ISb) is a shallow trench isolation (STI) structure. In addition, in some embodiments, the depth of the isolation structure ISb may be substantially equal to the depth of the isolation structure ISa.

In some embodiments, the method for forming the isolation structure IS may include forming a trench (not shown) on the surface of the epitaxial layer EP. Then, an insulating material is formed in the trench by a method such as a chemical vapor deposition process to form the isolation structure IS.

1 and 2E, step S112 is performed to form a plurality of photodiodes PD in the epitaxial layer EP. A plurality of photodiodes PD are arranged in the central region CR. In some embodiments, the photodiode PD is disposed on top of the epitaxial layer EP. In other words, the second doped region 104 may be located between the photodiode PD and the first doped region 102a. In addition, the photodiode PD vertically overlaps the second doped region 104 and the first doped region 102a. In some embodiments, a plurality of photodiodes PD may be respectively disposed between two adjacent field doping regions FI (that is, between two isolation structures ISa). The photodiode PD may include a first electrode E1 and a second electrode E2. In some embodiments, both the first electrode E1 and the second electrode E2 are doped regions formed in the epitaxial layer EP. The first electrode E1 has a first conductivity type (for example, P type), and the second electrode E2 has a second conductivity type (for example, N type). In some embodiments, the doping concentration of the first electrode E1 is in the range of 10 ¹² cm ^-2 to 10 ¹⁵ cm ^-2 , and the doping concentration of the second electrode E2 is in the range of 10 ¹² cm ^-2 to 10 ¹⁴ cm ⁻ Within the range of ² . In some embodiments, the first electrode E1 is disposed above the second electrode E2. In these embodiments, the first electrode E1 may extend from the top surface of the epitaxial layer EP to the inside of the epitaxial layer EP, and the second electrode E2 extends downward from the bottom surface of the first electrode E1. In some embodiments, the bottom surface of the first electrode E1 is higher than the bottom surface of the isolation structure ISa. In addition, the bottom surface of the second electrode E2 may be higher than the bottom surface of the field doping region FI, but may be lower than the bottom surface of the isolation structure ISa.

In some embodiments, before or after step S112, a contact region 110a may be formed on the top of the third doped region 106a. In some embodiments, the contact region 110a is a doped region and extends downward from the top surface of the epitaxial layer EP. In some embodiments, the bottom surface of the contact region 110a is higher than the bottom surface of the isolation structure ISb and higher than the bottom surface of the third doped region 106a. In addition, the contact region 110a has a second conductivity type (for example, N-type), and can be electrically connected to the third doped region 106, the second doped region 104, and the first doped region 102a. In some embodiments, the contact region 110a is a heavily doped region. In these embodiments, the doping concentration of the contact region 110 a is higher than the doping concentration of the third doping region 106. In this way, by providing the contact region 110a, the gap between the third doped region 106 and the interconnection structure subsequently formed on the epitaxial layer EP (for example, the interconnection structure M shown in FIG. 2F) can be reduced. Contact resistance. On the other hand, a contact region 110b may be formed on the top of the fourth doped region 108a. Similar to the contact region 110a, the contact region 110b can also be a doped region and extends downward from the top surface of the epitaxial layer EP. In some embodiments, the bottom surface of the contact region 110b is higher than the bottom surface of the isolation structure ISb (or the isolation structure ISa), and is higher than the bottom surface of the fourth doped region 108a. The contact region 110b has a first conductivity type (for example, a P-type), and can be electrically connected to the fourth doped region 108a and the epitaxial layer EP. In some embodiments, the contact region 110b is a heavily doped region. In these embodiments, the doping concentration of the contact region 110b is higher than the doping concentration of the fourth doping region 108a. In this way, by providing the contact region 110b, the gap between the fourth doped region 108a and the interconnection structure subsequently formed on the epitaxial layer EP (for example, the interconnection structure M shown in FIG. 2F) can be reduced. Contact resistance.

In some embodiments, before or after step S112, active devices AD may be formed in the edge region PR. Each active device AD can be located between adjacent isolation structures ISb. For example, the active device AD can be a field effect transistor. In some embodiments, the active device AD may include a gate structure GS, a drain DE, and a source SE. The gate structure GS may be located on the epitaxial layer EP, and includes a gate GE, a gate dielectric layer GD, and a spacer SP. The gate dielectric layer GD is located between the top surface of the gate electrode GE and the epitaxial layer EP, and the spacer SP surrounds the gate electrode GE and the gate dielectric layer GD. On the other hand, the drain electrode DE and the source electrode SE may be disposed in the epitaxial layer EP and located on opposite sides of the gate structure GS. In some embodiments, the drain electrode DE and the source electrode SE are disposed in the fourth doped region 108b. The drain electrode DE and the source electrode SE have the same conductivity type, and this conductivity type can be complementary to that of the fourth doped region 108b. For example, the drain electrode DE and the source electrode SE have the second conductivity type (for example, N-type), and the fourth doped region 108b has the first conductivity type (for example, the P-type). In other embodiments, the active device AD may further include a diode, a bipolar junction transistor (BJT), the like or a combination thereof. Those with ordinary knowledge in the field can select the type and configuration of the active device AD according to design requirements, and the embodiment of the present invention is not limited thereto.

1 and 2F, step S114 is performed to form a plurality of dielectric layers DL and interconnection structures M on the epitaxial layer EP. FIG. 2F only schematically illustrates the multiple dielectric layers DL and the interconnection structure M. The dielectric layer DL and the interconnect structure M are formed in the central region CR and the edge region PR. A plurality of dielectric layers DL may be stacked on the epitaxial layer EP, and the interconnect structure M may be formed in the plurality of dielectric layers DL. A plurality of photodiodes PD can be electrically connected to a logic circuit (not shown) through the interconnection structure M. In addition, the interconnect structure M can be electrically connected to the contact area 110a, the contact area 110b, and the active device AD, respectively. In some embodiments, the portion of the dielectric layer DL that overlaps the plurality of photodiodes PD in the longitudinal direction (for example, the region R shown in FIG. 2F) may not have an interconnect structure. In this way, light incident from the outside can smoothly pass through these regions R and enter the photodiode PD, thereby reducing the chance of being reflected by the interconnection structure M.

Step S116 is performed to form a color filter layer CF on the uppermost dielectric layer DL. The color filter layer CF is formed in the central region CR, and overlaps a plurality of photodiodes PD. In some embodiments, the color filter layer CF may include a plurality of color filter patterns, such as a blue color filter pattern CFB, a green color filter pattern CFG, and a red color filter pattern CFR. In some embodiments, the transmission band of the blue color filter pattern CFB is 476 nm to 495 nm. The penetration wavelength of the green color filter pattern CFG can be 495 nm to 570 nm. The transmission band of the red color filter pattern CFR may be 620 nm to 750 nm. The multiple color filter patterns are longitudinally overlapped on the multiple photodiodes PD, respectively. Only incident light of a specific wavelength band can penetrate the color filter pattern of a specific color, and then pass through the region R of the dielectric layer DL and enter the photodiode PD. In this way, each photodiode PD is configured to receive light of a specific wavelength band and convert it into an electrical signal. Each photodiode PD and its longitudinally overlapping structure can be regarded as a sub-pixel or a sensing unit.

Step S118 is performed to form a plurality of microlenses ML on the color filter layer CF. The plurality of microlenses ML may longitudinally overlap the plurality of color filter patterns, and longitudinally overlap the plurality of photodiodes PD.

So far, the semiconductor device 10 of some embodiments of the present invention has been completed. The semiconductor device 10 can be used as an image sensor. The semiconductor device 10 includes a first doped region 102a and a second doped region 104 disposed in the epitaxial layer EP. By allowing the first doped region 102a and the second doped region 104 to receive a positive bias, the electrons generated in the depth of the epitaxial layer EP by the incident light of long wavelength can be guided, and these electrons can leave the epitaxial layer. EP. In this way, the crosstalk between adjacent sub-pixels can be further reduced. On the other hand, by making the fourth doped region 108a disposed in the epitaxial layer EP receive a reference voltage or a negative voltage, the holes generated in the depth of the epitaxial layer EP by long-wavelength incident light can be guided to leave the epitaxial layer. EP. In addition, for long-wavelength incident light (for example, red light passing through the red color filter pattern CFR), a larger absorption depth is required to enable the corresponding photodiode PD to achieve sufficient quantum efficiency. The absorption depth described herein refers to the thickness of the portion of the epitaxial layer EP that vertically overlaps the photodiode PD, and this portion does not include the first doped region 102a and the second doped region 104. In the embodiment of the present invention, the second doped regions 104 are separately arranged in the epitaxial layer EP, and the gaps between adjacent second doped regions 104 are longitudinally overlapped with the color filter pattern that can transmit long wavelength light. In this way, long-wavelength incident light can be allowed to enter the absorption region with a large absorption depth. For example, the upper spacer region UI of the epitaxial layer EP located between the adjacent second doped regions 104 longitudinally overlaps the red light color filter pattern CFR, so that the red light enters to have a larger absorption depth DA The absorption area AR. Therefore, the quantum efficiency of the corresponding photodiode PD can be improved.

3 is a schematic cross-sectional view of the central region CR of the semiconductor device 10a according to some embodiments of the present invention. The semiconductor element 10a shown in FIG. 3 is similar to the semiconductor element 10 shown in FIG. 2F, and only the differences between the two are described below, and the same or similar parts will not be repeated. In addition, the same or similar element symbols represent the same or similar components.

3, the isolation structure ISa-1 of the semiconductor device 10a is a deep trench isolation (DTI) structure. The depth D6 of the isolation structure ISa-1 may be greater than the depth of the photodiode PD. In some embodiments, the isolation structure ISa-1 may extend longitudinally to contact the top surface of the second doped region 104. In other embodiments, the bottom surface of the isolation structure ISa-1 is higher than the top surface of the second doped region 104. In other embodiments, the isolation structure ISa-1 may further extend into the second doped region 104, or may extend into the first doped region 102a. For example, the depth D6 of the isolation structure ISa-1 may be in the range of 1 μm to 8 μm. In the embodiment shown in FIG. 3, the field doped region FI-1 also has a larger depth. In some embodiments, the field doped region FI-1 may extend into the second doped region 104, or may extend into the first doped region 102a. In other embodiments, the bottom surface of the field doped region FI-1 may also be higher than or in contact with the top surface of the second doped region 104, or may be higher than or in contact with the top surface of the first doped region 102a. For example, the depth D7 of the field doping region FI-1 may be in the range of 1.2 μm to 8.5 μm.

By increasing the depth of the isolation structure and the field doping region between adjacent photodiodes PD, the crosstalk between adjacent photodiodes PD or adjacent sub-pixels can be further reduced.

4 is a schematic cross-sectional view of the central region CR of the semiconductor device 10b according to some embodiments of the present invention. The semiconductor element 10b shown in FIG. 4 is similar to the semiconductor element 10 shown in FIG. 2F, and only the differences between the two are described below, and the same or similar parts will not be repeated. In addition, the same or similar element symbols represent the same or similar components.

Referring to FIG. 4, the color filter layer CF-1 of the semiconductor device 10b further includes an infrared color filter pattern CFI. In some embodiments, the transmission band of the infrared color filter pattern CFI is 760 nm to 1000 nm. In addition, the semiconductor element 10b includes a plurality of first doped regions 102a. The plurality of first doped regions 102a are separated from each other. The part of the epitaxial layer EP and the semiconductor substrate W between the adjacent first doped regions 102a may be referred to as a lower spacer region LI. Some upper spacers UI respectively located between two adjacent second doped regions 104 are longitudinally connected to the lower spacer LI, while other upper spacers UI do not longitudinally overlap the lower spacer LI. In some embodiments, the upper spacer UI and the lower spacer LI longitudinally overlapping each other longitudinally overlap the infrared color filter pattern CFI. On the other hand, some upper spacers UI that do not longitudinally overlap the lower spacer LI are longitudinally overlapped with the red color filter pattern CFR.

In the embodiment shown in FIG. 4, infrared light enters the absorption area AR-1 having a greater absorption depth DA-1. In this way, the quantum efficiency of the photodiode PD vertically overlapping the infrared color filter pattern CFI can be further improved.

5 is a schematic cross-sectional view of the central region CR of the semiconductor device 10c according to some embodiments of the present invention. The semiconductor element 10c shown in FIG. 5 is similar to the semiconductor element 10b shown in FIG. Specifically, the semiconductor device 10c shown in FIG. 5 can be regarded as replacing the shallow trench isolation of the semiconductor device 10b shown in FIG. 4 with the deep trench isolation structure ISa-1 and the field doped region FI-1 shown in FIG. Structure ISa and field doped region FI.

FIG. 6 is a flowchart of a method of manufacturing a semiconductor device 20 according to some embodiments of the present invention. 7A to 7C are schematic cross-sectional views of the structure at each stage in the method of manufacturing the semiconductor device 20 shown in FIG. 6. The semiconductor device 20 and its manufacturing method shown in FIGS. 6 and 7A to 7C are similar to the semiconductor device 10 and its manufacturing method shown in FIGS. 1 and 2A to 2F. The following describes only the differences between the two, the same or The similarities are not repeated here. In addition, the same or similar element symbols represent the same or similar components.

6 and 7A, after step S100, step S102a is performed to form a first initial doped region 102 and a plurality of second initial doped regions 204 in the semiconductor substrate W. Both the first initial doping region 102 and the plurality of second initial doping regions 204 have the second conductivity type, for example, the N type. In some embodiments, the first initial doping region 102 and the plurality of second initial doping regions 204 are both located in the central region CR. The plurality of second initial doping regions 204 are located between the top surface of the semiconductor substrate W and the first initial doping region 102. In addition, in some embodiments, the plurality of second initial doping regions 204 may be in contact with the first initial doping region 102. In other embodiments, the plurality of second initial doping regions 204 may also be higher than the first initial doping region 102 and not in contact with the first initial doping region 102.

Please refer to FIG. 6 and FIG. 7B, and then proceed to step S104 to form an epitaxial layer EP on the semiconductor substrate W. In the process of forming the epitaxial layer EP, the semiconductor substrate W is heated to cause the first initial doped region 102 and the plurality of second initial doped regions 204 to diffuse upward to extend into the epitaxial layer EP. In this way, a first doped region 102a and a plurality of second doped regions 204a can be formed. The top surface of the plurality of second doped regions 204a is higher than the top surface of the first doped region 102a, and the bottom surface of the plurality of second doped regions 204a is located in the first doped region 102a. In some embodiments, the plurality of second doped regions 204a can be regarded as extending longitudinally into the first doped region 102a. In some embodiments, the depth D8 of the second doped region 204a is in the range of 2 μm to 4 μm. In addition, in some embodiments, the thickness T5 of the second doped region 204a may be 1 μm to 4 μm.

Please refer to FIG. 6 and FIG. 7C, and then step S106 to step S118 are sequentially performed to complete the manufacturing of the semiconductor device 20. The difference between the semiconductor element 20 and the semiconductor element 10 shown in FIG. 2F mainly lies in the location and formation method of the second doped region. The semiconductor device 20 can also reduce crosstalk between adjacent sub-pixels. In addition, long-wavelength incident light can also enter the absorption region AR with a larger absorption depth DA, and the quantum efficiency of the long-wavelength sub-pixel can be improved. In the embodiment shown in FIG. 7C, the upper spacer region UI of the epitaxial layer EP located between two adjacent second doped regions 204a may overlap with a transmission wavelength in the range of 620 nm to 1000 nm. The color filter patterns are, for example, red light color filter patterns CFR and infrared light color filter patterns CFI.

FIG. 8 is a schematic cross-sectional view of the central region CR of the semiconductor device 20a according to some embodiments of the present invention. The semiconductor element 20a shown in FIG. 8 is similar to the semiconductor element 20 shown in FIG. 7C. Specifically, the semiconductor device 20a shown in FIG. 8 can be regarded as replacing the shallow trench isolation of the semiconductor device 20 shown in FIG. 7C with the deep trench isolation structure ISa-1 and the field doped region FI-1 shown in FIG. Structure ISa and field doped region FI.

9 is a schematic cross-sectional view of the central area CR of the semiconductor device 20b according to some embodiments of the present invention. The semiconductor element 20b shown in FIG. 9 is similar to the semiconductor element 20 shown in FIG. 7C. Specifically, the semiconductor device 20b shown in FIG. 9 can be regarded as replacing the single first doped region 102a of the semiconductor device 20 shown in FIG. 7C with a plurality of separated first doped regions 102a shown in FIG. 4. In addition, the upper spacer UI and the lower spacer LI of the epitaxial layer EP that are connected to each other longitudinally overlap the infrared color filter pattern CFI, while the upper spacer UI that is not connected downwardly to the lower spacer LI overlaps longitudinally. In the red color filter pattern CFR.

FIG. 10 is a schematic cross-sectional view of the central region CR of the semiconductor device 20c according to some embodiments of the present invention. The semiconductor element 20c shown in FIG. 10 is similar to the semiconductor element 20 shown in FIG. 7C. Specifically, the semiconductor device 20c shown in FIG. 10 can be regarded as replacing the shallow trench isolation of the semiconductor device 20 shown in FIG. 7C with the deep trench isolation structure ISa-1 and the field doped region FI-1 shown in FIG. Structure ISa and field doped region FI.

To sum up, the semiconductor device of the embodiment of the present invention can be used as an image sensor, and includes a first doped region and a plurality of second doped regions that are embedded in a substrate and electrically connected to each other. By making the first doped region and the second doped region receive a bias voltage, the carriers formed inside the substrate can be guided to leave the substrate through the first doped region and the second doped region. In this way, the crosstalk between adjacent sub-pixels can be reduced. In addition, the plurality of second doped regions located above the first doped region are separated from each other, and the part of the substrate extending between two adjacent second doped regions longitudinally overlaps the long-wavelength sub-pixels. In this way, the absorption depth of the absorption region through which long-wavelength incident light passes can be increased. Therefore, the quantum efficiency of the long-wavelength sub-pixel can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10, 10a, 10b, 10c, 20, 20a, 20b, 20c: semiconductor components 102: The first initial doping zone 102a: the first doped region 104, 204a: second doped region 106, 106a, 106b: third doped region 108, 108a, 108b: fourth doped region 110a, 110b: contact area 204: second initial doping zone AD: Active component AR, AR-1: absorption zone CF: Color filter layer CFB: Blue light color filter pattern CFG: Green color filter pattern CFI: Infrared color filter pattern CFR: Red light color filter pattern CR: Central District D1, D2, D3, D4, D5, D6, D7, D8: depth DA, DA-1: Absorption depth DE: Dip pole DL: Dielectric layer E1: first electrode E2: second electrode EP: epitaxial layer FI, FI-1: Field doped area GD: gate dielectric layer GE: Gate GS: Gate structure IS, ISa, ISa-1, ISb: isolation structure LI: Lower compartment M: Internal connection structure ML: Micro lens PD: photodiode PR: marginal zone R: area S100, S102, S102a, S104, S106, S108, S110, S112, S114, S116, S118: steps SB: Base SE: Source SP: Spacer T1, T2, T3, T4, T5: thickness UI: Upper compartment W: Semiconductor substrate W1: width

FIG. 1 is a flowchart of a method of manufacturing a semiconductor device according to some embodiments of the present invention. 2A to 2F are schematic cross-sectional views of the structure at each stage in the method of manufacturing the semiconductor device shown in FIG. 1. 3 to 5 are schematic cross-sectional views of the central area of a semiconductor device according to some embodiments of the invention. FIG. 6 is a flowchart of a method of manufacturing a semiconductor device according to some embodiments of the present invention. 7A to 7C are schematic cross-sectional views of the structure at each stage in the method of manufacturing the semiconductor device shown in FIG. 6. 8 to 10 are schematic cross-sectional views of the central area of a semiconductor device according to some embodiments of the invention.

10: Semiconductor components

102a: the first doped region

104: second doped region

106, 106a, 106b: third doped region

108, 108a, 108b: fourth doped region

AD: Active component

AR: absorption zone

CF: Color filter layer

CFB: Blue light color filter pattern

CFG: Green color filter pattern

CFR: Red light color filter pattern

CR: Central District

DA: Absorption depth

DL: Dielectric layer

EP: epitaxial layer

FI: Field doped region

IS, ISa, ISb: isolation structure

M: Internal connection structure

ML: Micro lens

PD: photodiode

PR: marginal zone

R: area

SB: Base

UI: Upper compartment

W: Semiconductor substrate

Claims (16)

A semiconductor component, including: The substrate has a first conductivity type; A plurality of photodiodes extending from the top surface of the substrate to the inside of the substrate; A plurality of color filter patterns are arranged on the substrate, and are respectively longitudinally overlapped on the plurality of photodiodes; The first doped region is disposed in the substrate and has a second conductivity type; and A plurality of second doped regions are disposed in the substrate and have the second conductivity type, wherein the plurality of second doped regions are in contact with the first doped regions and are located in the plurality of photoelectric second Between the pole body and the first doped region, there is an upper spacer region between two adjacent second doped regions, and a plurality of the upper spacer regions longitudinally overlap the plurality of color filter patterns There are several transmission wavelengths in the range of 620 nm to 1000 nm. The semiconductor device according to claim 1, wherein the base includes a semiconductor substrate and an epitaxial layer, the epitaxial layer is disposed on the semiconductor substrate, and the first doped region is formed by the semiconductor substrate The inner portion extends into the bottom of the epitaxial layer, and the plurality of second doped regions are located in the epitaxial layer. The semiconductor device according to claim 1, wherein the first doped region extends continuously and vertically overlaps the plurality of second doped regions and the plurality of photodiodes. The semiconductor device according to item 3 of the scope of patent application, wherein the top surface of the first doped region defines the bottom surface of the plurality of upper spacer regions. As for the semiconductor device described in item 1 of the scope of patent application, the number of the first doped regions is a majority, there are lower spacers between two adjacent first doped regions, and a plurality of the lower spacers are respectively It is longitudinally connected to some of the upper compartments. The semiconductor element according to claim 5, wherein the plurality of lower spacers vertically overlap with the plurality of color filter patterns having a transmission wavelength in the range of 760 nm to 1000 nm . The semiconductor device according to claim 1, wherein the plurality of second doped regions extend into the first doped regions. The semiconductor device described in item 1 of the scope of the patent application further includes a third doped region disposed in the substrate and having the second conductivity type, wherein the third doped region is electrically connected to the plurality of The second doped region and the first doped region. The semiconductor device described in item 1 of the scope of the patent application further includes a plurality of isolation structures, which extend from the top surface of the substrate to the inside of the substrate, and are respectively located between two adjacent photodiodes between. The semiconductor device according to the ninth patent application, wherein the depth of the plurality of isolation structures is smaller than the depth of the plurality of photodiodes. The semiconductor element according to the ninth patent application, wherein the depth of the plurality of isolation structures is greater than the depth of the plurality of photodiodes. The semiconductor device described in item 9 of the scope of patent application further includes a plurality of field doped regions, which are disposed in the substrate and have a first conductivity type, wherein the plurality of isolation structures are located in the plurality of field doped regions. District. A method for manufacturing a semiconductor element includes: Forming a first initial doped region in the semiconductor substrate, wherein the semiconductor substrate has a first conductivity type, and the first initial doped region has a second conductivity type; An epitaxial layer is formed on the semiconductor substrate, and the first initial doped region is diffused upward to extend into the epitaxial layer to form a first doped region, wherein the epitaxial layer has the First conductivity type A plurality of second doped regions having the second conductivity type are formed in the epitaxial layer, wherein the plurality of second doped regions are in contact with the first doped region and are located in the epitaxial layer Between the top surface of the layer and the first doped region; Forming a plurality of photodiodes in the epitaxial layer, wherein the plurality of second doped regions are located between the plurality of photodiodes and the first doped region; Forming a plurality of color filter patterns on the epitaxial layer, wherein the plurality of color filter patterns overlap the plurality of photodiodes, respectively, Wherein there are upper spacers between two adjacent second doped regions, and a plurality of the upper spacers are vertically overlapped in a plurality of color filter patterns with a transmission wavelength in the range of 620 nm to 1000 nm Several persons. The method for manufacturing a semiconductor device as described in the scope of patent application, wherein the plurality of second doped regions are located in the epitaxial layer and the semiconductor substrate, and the plurality of second doped regions are formed The methods include: After forming the first initial doping region, a plurality of second initial doping regions are formed in the semiconductor substrate, wherein the plurality of second initial doping regions are located on the top surface of the semiconductor substrate and the first doping region. Between an initial doped region, and wherein when the epitaxial layer is formed, the plurality of second initial doped regions diffuse upward to extend into the epitaxial layer to form the plurality of second doped regions Area. According to the method for manufacturing a semiconductor device described in the scope of the patent application, the number of the first initial doping region and the number of the first doping region are respectively a large number, and two adjacent first doping regions There are lower spacers between the regions, and a plurality of the lower spacers vertically overlaps some of the plurality of upper spacers, and vertically overlaps the transmission wavelength in the plurality of color filter patterns Several in the range of 760 nm to 1000 nm. The manufacturing method of semiconductor components as described in item 13 of the scope of patent application further includes: A third doped region having the second conductivity type is formed in the epitaxial layer, wherein the third doped region is electrically connected to the plurality of second doped regions and the first doped region Area.

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