CN111490000A - Electrostatic chuck and semiconductor processing equipment - Google Patents

Electrostatic chuck and semiconductor processing equipment Download PDF

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Publication number
CN111490000A
CN111490000A CN202010305242.7A CN202010305242A CN111490000A CN 111490000 A CN111490000 A CN 111490000A CN 202010305242 A CN202010305242 A CN 202010305242A CN 111490000 A CN111490000 A CN 111490000A
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CN
China
Prior art keywords
semiconductor
electrostatic chuck
temperature control
wafer
control assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010305242.7A
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Chinese (zh)
Inventor
吴东煜
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Beijing Naura Microelectronics Equipment Co Ltd
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Beijing Naura Microelectronics Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Beijing Naura Microelectronics Equipment Co Ltd filed Critical Beijing Naura Microelectronics Equipment Co Ltd
Priority to CN202010305242.7A priority Critical patent/CN111490000A/en
Publication of CN111490000A publication Critical patent/CN111490000A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833Details of electrostatic chucks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • H01L21/67103Apparatus for thermal treatment mainly by conduction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67248Temperature monitoring
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/17Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N19/00Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
    • H10N19/101Multiple thermocouples connected in a cascade arrangement

Abstract

The embodiment of the application provides an electrostatic chuck and semiconductor processing equipment. This electrostatic chuck sets up in the technology chamber of semiconductor processing equipment, and electrostatic chuck includes: the base, the temperature control assembly and the adsorption module are stacked from bottom to top; the base is fixedly arranged in the process chamber and used for bearing the temperature control assembly and the adsorption module; the adsorption module is used for bearing and adsorbing the wafer; the temperature control assembly comprises a plurality of semiconductor refrigerators for regulating and controlling the temperature of the wafer. According to the embodiment of the application, the wafer is heated or cooled, and the thermal inertia is very small, so that the requirements of the electrostatic chuck on the temperature rise and the temperature reduction of the wafer are fed back quickly; because a plurality of semiconductor refrigerators are arranged and respectively controlled, the heating or cooling control of the subareas is realized, and the heating uniformity can be effectively improved.

Description

Electrostatic chuck and semiconductor processing equipment
Technical Field
The application relates to the technical field of semiconductor processing, in particular to an electrostatic chuck and semiconductor processing equipment.
Background
Currently, a carrier for carrying a wafer in a semiconductor processing apparatus is generally an Electrostatic Chuck (ESC). An electrostatic chuck is a device that holds a Wafer (Wafer) by electrostatic attraction, controls the temperature of the Wafer surface, and provides a dc bias to the Wafer. Compared with a mechanical chuck, the electrostatic chuck reduces the probability of damage of the wafer due to pressure, collision and the like, increases the effective processing area of the wafer, and reduces the deposition of particles and byproducts on the surface of the wafer; electrostatic chucks can operate in a vacuum environment as compared to vacuum chucks. Due to the above advantages, the electrostatic chuck is widely used in Integrated Circuit (IC) manufacturing, especially in plasma Etching (ETCH), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and other processes.
When the semiconductor processing equipment performs the plasma etching process, the temperature is very sensitive, the etching result is not uniform due to the non-uniform wafer temperature, and therefore, the surface temperature (+/-1 ℃) of the wafer needs to be accurately controlled. However, harmful temperature gradients are likely to occur on the wafer surface during the process. For example, the difference in plasma energy across the wafer surface can cause non-uniform wafer surface temperature; the uneven adsorption force between the electrostatic chuck and the wafer can directly influence the contact state between the wafer and the surface of the electrostatic chuck, so that the thermal conductivity is influenced, and the temperature on the surface of the wafer is uneven; non-uniformity of the electric field strength and the rf energy also causes non-uniform temperature across the wafer surface. Under certain process conditions, the temperature difference across the wafer surface may reach 5-10 ℃. To counteract the wafer temperature gradient, the original temperature gradient effect may be neutralized by providing different temperatures in different regions of the electrostatic chuck. Of course, by using this method, it is also possible to control the temperature distribution on different areas of the wafer surface to be regular according to the specific process requirements.
As known from the electrostatic chuck structure, the temperature of the wafer surface during the process can be controlled by a heating layer and a cooling system in the susceptor. But since the cooling liquid is usually set to a constant temperature, the temperature of the wafer surface can be practically controlled only by the heating layer. The range and rate of temperature change of the heating layer is therefore of great importance to the process. During the process, the wafer absorbs energy in the plasma and heats up, causing a portion of the area to exceed the temperature required by the process. The existing heater can only heat up but can not cool down, and the cooling down of the wafer can only depend on the cooling liquid in the base. Because the wafer and the base are separated by the ceramic layer (the component of the electrostatic module), the heating layer, and the thermal insulation layer (located between the heating layer and the base to improve the heating effect), the cooling speed of the wafer is very slow. This may cause the etching rates in different areas to be in an uneven state for a long time, resulting in a reduction in product yield; in addition, the existing heater is a ring-shaped resistive heater. The existing cooling channels in the susceptor are also distributed annularly. Thus, existing electrostatic chucks may produce different temperatures in different annular regions, but may not produce significant temperature gradients in different regions of the same annular shape. However, a number of process results show that during plasma etching, the etch non-uniformity does not exhibit a circular profile (which means that the wafer surface temperature does not step circularly during etching). The ring heater does not provide good control over the uniformity of the wafer surface temperature.
Disclosure of Invention
The application aims at the defects of the prior art and provides an electrostatic chuck and semiconductor processing equipment, which are used for solving the technical problems that the heating or cooling feedback of the electrostatic chuck is slow and the heating uniformity is poor in the prior art.
In a first aspect, embodiments of the present application provide an electrostatic chuck disposed in a process chamber of a semiconductor processing apparatus, the electrostatic chuck comprising: the base, the temperature control assembly and the adsorption module are stacked from bottom to top; the base is fixedly arranged in the process chamber and used for bearing the temperature control assembly and the adsorption module; the adsorption module is used for bearing and adsorbing the wafer; the temperature control assembly comprises a plurality of semiconductor refrigerators, and the semiconductor refrigerators are used for regulating and controlling the temperature of the wafer.
In an embodiment of the present application, the temperature control assembly further includes a temperature control layer, and the semiconductor refrigerators are uniformly and alternately distributed in the temperature control layer.
In an embodiment of the present application, the semiconductor refrigerators are distributed in a linear array or in a circumferential array.
In an embodiment of the present application, the semiconductor refrigerator includes an N-type semiconductor, a P-type semiconductor, and a current carrier, and ends of the N-type semiconductor and the P-type semiconductor are electrically connected in series through the current carrier.
In an embodiment of the present application, the N-type semiconductor and the P-type semiconductor are disposed in pairs, and a plurality of pairs of the N-type semiconductor and the P-type semiconductor are alternately disposed and electrically connected in series through the current carrier.
In an embodiment of the present application, the temperature control assembly further includes an insulator, and the insulators are respectively attached to the outer surfaces of the flow conductors.
In an embodiment of the present application, the insulator is an alumina ceramic plate with a surface sintered with a metallization pattern, and the current carrier is a metal current carrier.
In an embodiment of the present application, a plurality of the semiconductor refrigerators are electrically connected in series, or a plurality of the semiconductor refrigerators are electrically connected in parallel.
In an embodiment of the present application, each of the semiconductor refrigerators includes a pair of N-type semiconductor and P-type semiconductor; the electrostatic chuck is provided with not less than 6500 semiconductor refrigerators with refrigerating power not less than 2000W and heating power not less than 5000W.
In a second aspect, embodiments of the present application provide a semiconductor processing apparatus comprising a process chamber having disposed therein the electrostatic chuck of the first aspect.
The technical scheme provided by the embodiment of the application has the following beneficial technical effects:
according to the electrostatic chuck, the temperature control assembly is arranged between the base and the adsorption module and comprises the plurality of semiconductor refrigerators, and the semiconductor refrigerators can absorb and release heat according to different current directions, so that wafers can be heated or cooled, and the thermal inertia is very small, so that the electrostatic chuck can quickly feed back the requirements of heating and cooling the wafers; and the plurality of semiconductor refrigerators can realize high-precision control through the change of input current so as to form an automatic control system to realize automatic control. Furthermore, a plurality of semiconductor refrigerators are arranged and are respectively controlled, so that heating or cooling control in different areas is realized, and heating uniformity can be effectively improved.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic front view of an electrostatic chuck according to an embodiment of the present disclosure;
FIG. 2A is a schematic top view of a temperature control assembly according to an embodiment of the present disclosure;
FIG. 2B is a schematic top view of another example temperature control assembly of the present application;
fig. 3 is a schematic cross-sectional view of a semiconductor refrigerator according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.
An embodiment of the present invention provides an electrostatic chuck disposed in a process chamber (not shown) of a semiconductor processing apparatus, the electrostatic chuck having a schematic structural diagram as shown in fig. 1, including: the base 1, the temperature control assembly 2 and the adsorption module 3 are stacked from bottom to top; the base 1 is fixedly arranged in the process chamber and is used for bearing the temperature control assembly 2 and the adsorption module 3; the adsorption module 3 is used for bearing and adsorbing the wafer; the temperature control assembly 2 comprises a plurality of semiconductor refrigerators 21, and the plurality of semiconductor refrigerators 21 are used for regulating and controlling the temperature of the wafer.
As shown in fig. 1 to 2B, the susceptor 1 is generally a circular plate-shaped structure made of an alloy aluminum. The susceptor 1 introduces a Radio Frequency (RF) power source to the wafer to form an RF bias; secondly, the base 1 comprises a cooling liquid channel (not shown in the figure), and the temperature of the electrostatic chuck can be controlled by controlling the temperature of the cooling liquid, so that the temperature of the wafer is controlled; thirdly, the base 1 blows the heat conducting medium (such as helium) uniformly to the back of the wafer, so that the wafer is heated more uniformly. The temperature control assembly 2 is stacked on the base 1, and the temperature control assembly 2 is located between the base 1 and the electrostatic adsorption module 3. The temperature control assembly 2 mainly comprises a plurality of semiconductor refrigerators 21, and the plurality of semiconductor refrigerators 21 can be used for heating or refrigerating the wafer. The adsorption module 3 is stacked on the temperature control assembly 2, and is generally a circular plate-shaped structure manufactured in a ceramic material sintering or ceramic spraying manner, and the direct current electrode is buried in the circular plate-shaped structure in a sintering or spraying manner. When the wafer needs to be adsorbed, a fixed electric potential is applied to the direct current electrode, so that induced charges are generated on the back surface of the wafer and are adsorbed by the electrostatic chuck.
The semiconductor refrigerator is a semiconductor element which can heat and cool by using the Peltier effect. The peltier effect means that when current passes through a loop formed by different conductors, in addition to irreversible joule heat, heat absorption and heat release phenomena occur at joints of the different conductors respectively along with the difference of current directions. The specific principle is as follows: the movement of charge carriers in the conductor forms a current which, due to the different energy levels of the charge carriers in the different materials, releases excess heat (expressed as heat) as it moves from a high level to a low level; whereas heat from the outside (in the form of refrigeration) needs to be absorbed.
According to the electrostatic chuck, the temperature control assembly is arranged between the base and the adsorption module and comprises the plurality of semiconductor refrigerators, and the semiconductor refrigerators can absorb and release heat according to different current directions, so that wafers can be heated or cooled, and the thermal inertia is very small, so that the electrostatic chuck can quickly feed back the requirements of heating and cooling the wafers; and the plurality of semiconductor refrigerators can realize high-precision control through the change of input current so as to form an automatic control system to realize automatic control. Furthermore, a plurality of semiconductor refrigerators are arranged and are respectively controlled, so that heating or cooling control in different areas is realized, and heating uniformity can be effectively improved.
It should be noted that the embodiment of the present application is not limited to the specific implementation of the base 1, for example, the base 1 may not include a cooling liquid channel, and the electrostatic chuck is cooled only by the temperature control assembly 2; in addition, the embodiment of the present application is not limited to the specific structure of the adsorption module 3, as long as the adsorption module adopts an electrostatic mode to realize the function of adsorbing the wafer. Therefore, the embodiments of the present application are not limited thereto, and those skilled in the art can adjust the settings according to the actual situation.
In an embodiment of the present application, the temperature control assembly 2 further includes a temperature control layer 22, and the plurality of semiconductor refrigerators 21 are uniformly and alternately distributed in the temperature control layer 22. Alternatively, a plurality of semiconductor refrigerators 21 are distributed in a linear array or a plurality of semiconductor refrigerators 21 are distributed in a circumferential array.
As shown in fig. 1 and fig. 2B, the temperature control assembly 2 may specifically include a temperature control layer 22, the temperature control layer 22 may specifically adopt a circular plate-shaped structure made of a heat conductive and insulating material, and the plurality of semiconductor refrigerators 21 may be uniformly and intermittently distributed in the temperature control layer 22. Further, the plurality of semiconductor refrigerators 21 may be distributed in a linear array, as shown in fig. 2A; and the plurality of semiconductor refrigerators 21 may be distributed in a circumferential array, as shown in fig. 2B. By adopting the design, the arrangement mode of the temperature control group can be flexible, so that the processing and manufacturing cost is further reduced, and the application range is effectively improved to correspond to different wafers and processing technologies. Therefore, the embodiment of the present application is not limited to the distribution manner of the plurality of semiconductor refrigerators 21, and those skilled in the art can adjust the setting according to actual situations.
In an embodiment of the present application, the semiconductor refrigerator 21 includes an N-type semiconductor 211, a P-type semiconductor 212, and a current carrier 213, wherein ends of the N-type semiconductor 211 and the P-type semiconductor 212 are electrically connected in series through the current carrier 213.
As shown in fig. 3, the principle of the semiconductor refrigerator 21 is that when an N-type semiconductor 211 and a P-type semiconductor 212 are connected to form a semiconductor couple pair, energy transfer can be generated after a direct current is switched on in the circuit, and the current absorbs heat from the junction where the N-type semiconductor 211 flows to the P-type semiconductor 212 to become a cold end; the junction from P-type semiconductor 212 to N-type semiconductor 211 releases heat as a hot side. By arranging a plurality of semiconductor refrigerators 21 in the same order and connecting the cold ends and the hot ends respectively, the capacities of the plurality of semiconductor refrigerators 21 can be superposed to obtain a larger refrigerating capacity or heating capacity.
In an embodiment of the present application, the N-type semiconductors 211 and the P-type semiconductors 212 are disposed in pairs, and a plurality of pairs of the N-type semiconductors 211 and the P-type semiconductors 212 are disposed alternately and electrically connected in series through the current carriers 213.
Fig. 3 is a schematic cross-sectional view of the semiconductor refrigerator 21, and as shown in fig. 3, core components of the semiconductor refrigerator 21 are an N-type semiconductor 211 and a P-type semiconductor 212 whose main components are bismuth telluride, and the N-type semiconductor 211 and the P-type semiconductor 212 are present in pairs and distributed at intervals, and at least one pair is provided. The N-type semiconductor 211 and the P-type semiconductor 212 are located at the innermost portion of the semiconductor refrigerator 21 and are connected in series only through the current carrier 213; the current carriers 213 are located at upper and lower sides of the semiconductor device. The current carrier is generally composed of oxygen-free copper, thereby performing electric and thermal conduction, but the current carrier 213 may be aluminum or silver, or other metal having excellent heat and electrical conductivity. The current carrier 213 is connected to the N-type semiconductor 211 and the P-type semiconductor 212 by soldering. When the semiconductor refrigerator 21 is operated, the junction with the current direction of N-type flowing to P-type absorbs heat to become the cold end, and vice versa to become the hot end. Because the NP type joint and the PN type joint are positioned on different sides, namely the N type semiconductor and the P type semiconductor are electrically connected in series through the flow guiding body, the heating quantity and the cooling quantity are mutually superposed but not offset, so that larger temperature difference is obtained on two sides. By adopting the design, the structure of the embodiment of the application is simple, the manufacturing cost can be effectively reduced, and the economic benefit of the embodiment of the application is effectively improved.
It should be noted that the embodiment of the present application is not limited to the structure of the semiconductor refrigerator 21 and the manufacturing material of the semiconductor, and the semiconductor refrigerator 21 made of other materials may be used. Therefore, the embodiments of the present application are not limited thereto, and those skilled in the art can adjust the settings according to the actual situation.
In an embodiment of the present application, the temperature control assembly 2 further includes an insulator 214, and the insulator 214 is respectively attached to the outer surfaces of the current carriers 213. Alternatively, the insulator 214 is an alumina ceramic plate with a metallized pattern sintered on the surface, and the current carrier 213 is a current carrier 213 made of a metal material.
As shown in fig. 3, the insulator 214 is specifically an alumina ceramic plate with a surface sintered with a metallization pattern, and the insulator 214 plays roles of electrical insulation, heat conduction, support and the like. Specifically, the insulators 214 may be two and stacked one above the other, the N-type semiconductors 211 and the P-type semiconductors 212 in the plurality of pairs are located between the insulators 214, and the current carriers 213 and the insulators 214 located between the N-type semiconductors 211 and the P-type semiconductors 212 in each pair are connected by soldering. The current carrier 213 mainly plays a role of electrical and thermal conduction, and its composition is usually oxygen-free copper, but may be other metals with excellent thermal and electrical conductivity, such as aluminum or silver. By adopting the design, the insulating property of the semiconductor refrigerator 21 can be improved, the heat conducting property can be improved, and the application and maintenance cost can be effectively reduced by adopting the materials. However, the embodiments of the present application are not limited thereto, and those skilled in the art can adjust the settings according to the actual situation.
In an embodiment of the present application, the semiconductor refrigerators 21 are electrically connected in series, or the semiconductor refrigerators 21 are electrically connected in parallel. As shown in fig. 2A and 2B, the semiconductor refrigerators 21 are electrically connected in series, and the temperature of the semiconductor refrigerators 21 can be controlled simultaneously by using the design, so as to control the temperature of the whole region of the electrostatic chuck; and a plurality of semiconductor refrigerators 21 can also adopt the parallelly connected setting of electricity, adopt this design can realize realizing temperature control respectively to each semiconductor refrigerator 21, and then realize carrying out nimble control to the temperature of certain region of electrostatic chuck. By adopting the above design, different temperature control modes can be realized by adopting different setting modes among the plurality of semiconductor refrigerators 21, so that the control mode of the embodiment of the application is more flexible, and the application range of the embodiment of the application is effectively improved.
In an embodiment of the present application, each semiconductor refrigerator 21 includes a pair of N-type semiconductor and P-type semiconductor, and the cooling power of 6500 semiconductor refrigerators 21 is 2000w and the heating power is 5000 w.
As shown in fig. 2A and 2B, each of the semiconductor refrigerators 21 employs a single semiconductor couple pair, i.e., a semiconductor couple pair composed of an N-type semiconductor 211 and a P-type semiconductor 212. The semiconductor refrigerator 21 formed by a single semiconductor couple pair has very small volume and power, the area is about 10 square millimeters, the thickness (the distance between the outer surfaces of the two insulators 214) is about 4 millimeters, the refrigerating power is 0.4-1.2W (watt), and the heating power is 0.6-3W. By connecting the semiconductor couple pairs of the same type in series, the refrigerating sheets with different sizes, shapes and powers can be obtained. The area of the heat control layer of the heat control assembly is about 68000 square millimeters, more than 6500 groups of semiconductor couple pairs can be arranged, the refrigerating power reaches 2000W, the heating power reaches 5000W, and the temperature control range is-20-90 ℃ during no-load. According to the embodiments, the cooling and heating of the wafer can be rapidly realized, the temperature adjusting range is large, the application range of the embodiments is greatly improved, and the embodiments are small in size and convenient to install and apply. It should be noted that fig. 2A and 2B only show the arrangement of the semiconductor refrigerators, and do not show the specific number of semiconductor refrigerators.
In an embodiment of the present application, the semiconductor refrigerator 21 is any one or a combination of a triangle or a rectangle. As shown in fig. 2A and 2B, the semiconductor cooler 21 may be packaged in various shapes so as to be arranged on the base 1, and since the base 1 generally has a circular plate-shaped structure, the semiconductor cooler 21 may have a triangular or rectangular structure so as to be arranged on the circular base 1. However, the embodiment of the present application does not limit the specific shape of the semiconductor refrigerator 21, and for example, the shape and the arrangement density of the semiconductor refrigerator 21 are adjusted according to the shape of the susceptor 1 and the wafer specification. Therefore, the embodiments of the present application are not limited thereto, and those skilled in the art can adjust the settings according to actual situations.
Based on the same inventive concept, the embodiment of the application provides semiconductor processing equipment which comprises a process chamber, wherein the electrostatic chuck provided by the above embodiments is arranged in the process chamber.
By applying the embodiment of the application, at least the following beneficial effects can be realized:
according to the electrostatic chuck, the temperature control assembly is arranged between the base and the adsorption module and comprises the plurality of semiconductor refrigerators, and the semiconductor refrigerators can absorb and release heat according to different current directions, so that wafers can be heated or cooled, and the thermal inertia is very small, so that the electrostatic chuck can quickly feed back the requirements of heating and cooling the wafers; and the plurality of semiconductor refrigerators can realize high-precision control through the change of input current so as to form an automatic control system to realize automatic control. Furthermore, a plurality of semiconductor refrigerators are arranged and are respectively controlled, so that heating or cooling control in different areas is realized, and heating uniformity can be effectively improved.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims (10)

1. An electrostatic chuck for placement in a process chamber of a semiconductor processing apparatus, comprising: the base, the temperature control assembly and the adsorption module are stacked from bottom to top;
the base is fixedly arranged in the process chamber and used for bearing the temperature control assembly and the adsorption module; the adsorption module is used for bearing and adsorbing the wafer;
the temperature control assembly comprises a plurality of semiconductor refrigerators, and the semiconductor refrigerators are used for regulating and controlling the temperature of the wafer.
2. The electrostatic chuck of claim 1, wherein said temperature control assembly further comprises a temperature control layer, and a plurality of said semiconductor cryostats are uniformly and intermittently distributed within said temperature control layer.
3. The electrostatic chuck of claim 2, wherein a plurality of said semiconductor cryostats are distributed in a linear array or a plurality of said semiconductor cryostats are distributed in a circumferential array.
4. The electrostatic chuck of claim 1, wherein the semiconductor refrigerator comprises an N-type semiconductor, a P-type semiconductor, and a current carrier, wherein ends of the N-type semiconductor and the P-type semiconductor are electrically connected in series through the current carrier.
5. The electrostatic chuck of claim 4, wherein the N-type semiconductor and the P-type semiconductor are arranged in pairs, pairs of N-type semiconductor and P-type semiconductor are arranged alternately and electrically in series through the current carrier.
6. The electrostatic chuck of claim 5, wherein the temperature control assembly further comprises insulators respectively attached to the outer surfaces of the current carriers.
7. The electrostatic chuck of claim 6, wherein the insulator is an alumina ceramic plate with a metallized pattern sintered on the surface, and the current carrier is a metal current carrier.
8. The electrostatic chuck of any of claims 1 to 7, wherein a plurality of said semiconductor cryostats are arranged electrically in series or a plurality of said semiconductor cryostats are arranged electrically in parallel.
9. The electrostatic chuck of any of claims 1 to 7, wherein each said semiconductor refrigerator comprises a pair of N-type and P-type semiconductors; the electrostatic chuck is provided with not less than 6500 semiconductor refrigerators with refrigerating power not less than 2000W and heating power not less than 5000W.
10. A semiconductor processing apparatus comprising a process chamber, wherein the electrostatic chuck of any of claims 1 to 9 is disposed within the process chamber.
CN202010305242.7A 2020-04-17 2020-04-17 Electrostatic chuck and semiconductor processing equipment Pending CN111490000A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023138489A1 (en) * 2022-01-21 2023-07-27 北京北方华创微电子装备有限公司 Electrostatic chuck device and temperature control method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1098354A2 (en) * 1999-11-08 2001-05-09 Applied Materials, Inc. Apparatus for controlling temperature in a semiconductor processing system
KR20020070668A (en) * 2001-03-02 2002-09-11 동부전자 주식회사 Unified electric chiller and composited electro static chuck by using it
US20040107704A1 (en) * 2002-07-11 2004-06-10 Hudson Douglas E. Workpiece chuck with temperature control assembly having spacers between layers providing clearance for thermoelectric modules
US20040248430A1 (en) * 2003-06-09 2004-12-09 Rennie Barber Wafer cooling chuck with direct coupled peltier unit
CN103137517A (en) * 2011-11-25 2013-06-05 中芯国际集成电路制造(北京)有限公司 Reaction device for treating wafer, electrostatic chuck and wafer temperature control method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1098354A2 (en) * 1999-11-08 2001-05-09 Applied Materials, Inc. Apparatus for controlling temperature in a semiconductor processing system
KR20020070668A (en) * 2001-03-02 2002-09-11 동부전자 주식회사 Unified electric chiller and composited electro static chuck by using it
US20040107704A1 (en) * 2002-07-11 2004-06-10 Hudson Douglas E. Workpiece chuck with temperature control assembly having spacers between layers providing clearance for thermoelectric modules
US20040248430A1 (en) * 2003-06-09 2004-12-09 Rennie Barber Wafer cooling chuck with direct coupled peltier unit
CN103137517A (en) * 2011-11-25 2013-06-05 中芯国际集成电路制造(北京)有限公司 Reaction device for treating wafer, electrostatic chuck and wafer temperature control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023138489A1 (en) * 2022-01-21 2023-07-27 北京北方华创微电子装备有限公司 Electrostatic chuck device and temperature control method

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