CN111477187A - Time schedule controller, signal calibration method thereof and display device - Google Patents
Time schedule controller, signal calibration method thereof and display device Download PDFInfo
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The application discloses a time schedule controller, a signal calibration method thereof and a display device. The method comprises the following steps: decompressing and generating a clock signal and a DE signal according to the VBO signal; acquiring the total number of lines and the total number of fields according to the DE signal; dividing the frequency of the clock signal to obtain the number of clocks when the frequency-divided signal is at a high level; acquiring clock frequency according to the frequency division number and the number of the clocks; and when the clock frequency is judged to be within a preset frequency range, acquiring the image display frame rate of the VBO signal. According to the method and the device, the calculation precision of the clock frequency is improved, so that the frame rate can be accurately calculated, the TCON can normally work, and misoperation is avoided.
Description
Technical Field
The application relates to the technical field of display, in particular to a time schedule controller, a signal calibration method thereof and a display device.
Background
VBO receiver uses differential line to transmit video image signal, a group of differential line corresponds to L ane (channel), the highest data transmission rate reaches 4Gbps, the bandwidth problem in the video image signal transmission process is solved, the number of pairs of differential lines of the transmitted video image signal is reduced, therefore, the number of connecting lines and interfaces for transmitting the video image signal is also reduced correspondingly, and the purpose of reducing the cost in the video image signal transmission process is achieved.
H_total×V_total×Frame_Rate＝pixel clock frequency
The total number of lines comprises effective pixels in one line, the width of a line synchronization front edge, the number of VC L K between the end of one line of effective data and the start of the next horizontal synchronization signal and the number of VC L between the start of the horizontal synchronization signal and the start of one line of effective data, and the total number of fields comprises the effective pixels in one field (column), the width of the field synchronization front edge, the number of invalid lines before the vertical synchronization signal after the end of one frame of image and the number of invalid lines after the vertical synchronization signal when one frame of image starts.
Tcon (timer Control register), a timing controller, also called a logic board, a screen driving board or a central Control board. Current TCONs support a fixed pixel clock frequency (pixel clock frequency) by adjusting the blanking (V-blanking) time to support a varying frame rate (frame rate). The pixel clock frequency is very important in practical applications. However, in practice, the total number of rows (H _ total) and the total number of fields (V _ total) can be accurately detected by counting, and it is difficult to increase the accuracy of the pixel clock frequency.
Therefore, it is desirable to provide a signal calibration method for a timing controller to overcome the above-mentioned drawbacks.
Disclosure of Invention
In view of the above-mentioned problems, the present application provides a timing controller, a signal calibration method thereof, and a display device, which are used to improve the calculation accuracy of the clock frequency.
According to a first aspect of the present application, there is provided a signal calibration method of a timing controller, including: s1, generating a first clock signal and a DE signal according to the VBO signal; s2, acquiring the total number of lines and the total number of fields according to the DE signal; s3, dividing the frequency of the first clock signal by a preset frequency dividing number to obtain a frequency dividing signal, and obtaining the number of the first clocks when the frequency dividing signal is at a high level under a system clock; s4, acquiring a first clock frequency according to the frequency division number and the first clock number; s5, judging whether the first clock frequency is in a preset frequency range, if so, executing a step S6, otherwise, sending an interrupt request; s6, acquiring the image display frame rate of the VBO signal according to the total number of the lines, the total number of the fields and the first clock frequency.
According to a second aspect of the present application, there is provided a timing controller comprising: the RX module is used for generating a first clock signal and a DE signal according to the VBO signal; the resolution detection module is used for acquiring the total number of lines and the total number of fields according to the DE signal; the clock detection module is used for carrying out frequency division on the first clock signal by using a preset frequency division number to obtain a frequency division signal and obtaining the number of the first clocks when the frequency division signal is at a high level under a system clock; the frequency obtaining module is used for obtaining the frequency of the first clock according to the frequency dividing number and the number of the first clock; the frequency judging module is used for judging whether the first clock frequency is within a preset frequency range, if so, the frame rate obtaining module is called, and otherwise, an interrupt request is sent; and the frame rate acquisition module is used for acquiring the image display frame rate of the VBO signal according to the total number of the lines, the total number of the fields and the first clock frequency.
According to a third aspect of the present application, there is provided a display device comprising: at least one processor; and at least one memory for storing one or more computer-executable instructions; wherein the executable instructions, when executed by the processor, cause any of the signal calibration methods in the embodiments of the present application to be performed.
Compared with the prior art, the positive effect of this application lies in:
the calculation precision of the clock frequency is improved so as to accurately calculate the frame rate, thereby ensuring that the TCON can normally work and misoperation cannot be carried out.
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The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a flowchart of a signal calibration method of a timing controller according to the present application.
Fig. 2 is a detailed flowchart of an embodiment of a signal calibration method of a timing controller according to the present application.
Fig. 3 is a block diagram of a timing controller according to the present application.
Fig. 4 is a schematic structural diagram of a display device according to an embodiment of the present application
Detailed Description
The technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments should not be construed as limiting the present application unless it is specifically stated otherwise.
The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1 to 2, fig. 1 is a flowchart illustrating a signal calibration method of a timing controller according to the present application, and fig. 2 is a detailed flowchart illustrating an embodiment of the signal calibration method of the timing controller according to the present application.
As shown in fig. 1, the present application provides a method for calibrating a signal by using a timing controller, which includes the following specific steps:
s1, generating a first clock signal and a DE signal according to the VBO signal; s2, acquiring the total number of lines and the total number of fields according to the DE signal; s3, dividing the frequency of the first clock signal by a preset frequency dividing number to obtain a frequency dividing signal, and obtaining the number of the first clocks when the frequency dividing signal is at a high level under a system clock; s4, acquiring a first clock frequency according to the frequency division number and the first clock number; s5, judging whether the first clock frequency is in a preset frequency range, if so, executing a step S6, otherwise, sending an interrupt request; s6, acquiring the image display frame rate of the VBO signal according to the total number of the lines, the total number of the fields and the first clock frequency.
The above method is explained in detail below with reference to fig. 2:
the first clock signal and the DE signal are generated from the VBO signal decompression with respect to step S1.
Preferably, the first clock signal may be subjected to a certain amplification process. The DE signal is effective data strobe signal, also called data enable signal, and there are many kinds of symbols in the LCD circuit, such as DSP, DSPTMG, DEN, DE, etc.; the first clock signal is a pixel clock signal.
With respect to step S2, from the DE signal, the total number of lines and the total number of fields are acquired.
Specifically, as shown in fig. 2, step S2 further includes:
s21, acquiring the number of second clocks when the DE signal is at a high level under the system clock;
s22, judging whether the DE signal is at a high-level falling edge or not, if so, executing a step S23, otherwise, returning to execute the step S21;
s23, judging whether the number of the second clocks is within a preset numerical range; and if so, outputting the total number of lines (H _ total) and the total number of fields (V _ total). The upper limit of the preset numerical range is the sum of the length len of the DE signal and a preset offset buf, and the lower limit of the preset numerical range is the difference between the length len of the DE signal and the preset offset buf.
And when the second clock number is judged not to be in the preset numerical range, sending an interrupt request to a Micro Control Unit (MCU), and starting a built-in self test (BIST) mode and restarting to carry out signal calibration according to the interrupt request by the MCU.
The step S22 further includes: and if the second clock number is within the preset numerical range, cutting the DE signal into the length value len according to the length value.
Illustratively, in the 4K sequence, the length value len of the DE signal is a fixed value 3840, and the high level of the DE signal is counted to be the second clock number, and if the second clock number is greater than 3840+ buf or less than 3840-buf at the time of the falling edge, the DE signal is judged to be unsatisfactory. If not, sending an interrupt to inform the MCU to make the MCU perform VBO training (training) again. As long as the number of 3840-BUF is less than or equal to the second clock number is less than or equal to 3840+ BUF, the MCU is not notified, but the clipping operation is performed to make the number equal to 3840. The DE signal is mainly counted by a system clock, whether the high level meets the requirement or not is judged on the falling edge of the DE signal, and zero clearing operation is carried out at the low level.
In step S3, the first clock signal is divided by a preset frequency division number to obtain a frequency division signal, and the number of the first clocks at the high level of the frequency division signal in the system clock is obtained.
Specifically, the acquiring the first number of clocks when the frequency-divided signal is at a high level in the system clock in step S3 further includes:
s31, determining whether the frequency-divided signal (C L K _ ODD) is at a high level, if the frequency-divided signal (C L K _ ODD) is at a high level, controlling the first clock number (H _ CNT) to self-increment according to a system clock, otherwise, setting the first clock number (H _ CNT) to 0;
s32, determining whether the frequency-divided signal (C L K _ ODD) is at a falling edge, if the frequency-divided signal (C L K _ ODD) is at the falling edge, acquiring a current first clock number (H _ CNT), otherwise, returning to the step S31.
Besides, the application of other frequency division operations can be understood by those skilled in the art, and the relevant selection of the frequency division operation cannot be understood as a limitation of the present application.
In step S4, a first clock frequency is obtained according to the frequency division number and the first clock number. Specifically, the first clock frequency is calculated based on the following formula (1):
(1÷Freqrx)*N＝(1÷FreqSYS)*M (1)
wherein M is the first number of clocks, N is the frequency division number, FreqrxFor said first clock frequency, FreqSYSIs a fixed system frequency. This part can be done by a Micro Control Unit (MCU), which saves a divider. The first clock frequency is the pixel clock frequency.
Regarding step S5, it is determined whether the first clock frequency is within a predetermined frequency range, if yes, step S6 is executed, otherwise, an interrupt request is issued.
In particular, the first clock frequency Freq is determinedrxAnd when the frequency is not within the preset frequency range, sending the interrupt request to the Micro Control Unit (MCU), and starting a built-in self-test mode and carrying out VBO training again by the MCU according to the interrupt request, namely restarting to carry out signal calibration.
With respect to step S6, an image display frame rate of the VBO signal is acquired according to the total number of lines, the total number of fields, and the first clock frequency. Specifically, the frame rate is calculated based on the following formula (2):
H_total×V_total×Frame_Rate＝Freqrx(2)
wherein H _ total is the total number of rows, and V _ total is the total number of columns.
The method improves the calculation precision of the clock frequency, and can accurately calculate the frame rate, thereby ensuring that the TCON can normally work without misoperation.
Referring to fig. 3, fig. 3 is a block diagram of a timing controller according to the present application. As shown in fig. 3, the present application provides a timing controller 3, including: the RX module 31, the resolution detection module 32, the clock detection module 33, the frequency acquisition module 34, the frequency determination module 35, and the frame rate acquisition module 36.
The RX module 31 is configured to generate a first clock signal and a DE signal according to the VBO signal; the resolution detection module 32 is configured to obtain a total number of lines and a total number of fields according to the DE signal; the clock detection module 33 is configured to divide the frequency of the first clock signal by a preset frequency division number to obtain a frequency division signal, and obtain the number of first clocks when the frequency division signal is at a high level in the system clock; the frequency obtaining module 34 is configured to obtain a first clock frequency according to the frequency division number and the first clock number; the frequency determining module 35 is configured to determine whether the first clock frequency is within a preset frequency range, if so, invoke the frame rate obtaining module 36, and otherwise, send an interrupt request; the frame rate obtaining module 36 is configured to obtain an image display frame rate of the VBO signal according to the total number of lines, the total number of fields, and the first clock frequency.
Through the time sequence controller, high-precision calculation of clock frequency can be realized, and accordingly, an accurate frame rate is obtained, so that normal work of the TCON is guaranteed, and misoperation is avoided.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 4, the display device 4 includes: at least one processor 41; and at least one memory 42 for storing one or more computer-executable instructions; wherein the executable instructions, when executed by the processor, cause any of the signal calibration methods in the embodiments of the present application to be performed. The memory 42 stores a plurality of instructions adapted to be loaded by the processor 41 and to perform the steps of:
decompressing according to the VBO signal to generate a first clock signal and a DE signal; acquiring the total number of lines and the total number of fields according to the DE signal; dividing the frequency of the first clock signal by a preset frequency division number to obtain a frequency division signal, and obtaining the number of the first clocks when the frequency division signal is at a high level under a system clock; acquiring a first clock frequency according to the frequency division number and the first clock number; and judging whether the first clock frequency is within a preset frequency range, if so, acquiring the image display frame rate of the VBO signal according to the total number of the lines, the total number of the fields and the first clock frequency, and otherwise, sending an interrupt request.
In fig. 4, one processor 41 is taken as an example; the processor 41 and the memory 42 in the display device may be connected by a bus or other means, and the connection by the bus is exemplified in fig. 4.
The memory 42 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as program instructions/modules (for example, the respective modules shown in fig. 3) corresponding to the signal calibration method of the timing controller in the embodiment of the present application. The processor 41 executes various functional applications of the server and data processing by running software programs, instructions, and modules stored in the memory 42, that is, implements the signal calibration method of the timing controller described above.
The memory 42 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system and an application program required by at least one function; the storage data area may store data created according to the use of the server, and the like.
Further, the memory 42 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, memory 42 may further include memory located remotely from processor 41, which may be connected to a server over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The server provided by the present embodiment and the signal calibration method of the timing controller provided by the above embodiment belong to the same inventive concept, and the technical details that are not described in detail in the present embodiment can be referred to the above embodiment, and the present embodiment has the same advantageous effects as the signal calibration method of the timing controller.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The timing controller, the signal calibration method thereof, and the display device provided in the embodiments of the present application are described in detail above, and specific examples are applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Claims (10)
1. A method for calibrating a signal of a timing controller, comprising:
s1, generating a first clock signal and a DE signal according to the VBO signal;
s2, acquiring the total number of lines and the total number of fields according to the DE signal;
s3, dividing the frequency of the first clock signal by a preset frequency dividing number to obtain a frequency dividing signal, and obtaining the number of the first clocks when the frequency dividing signal is at a high level under a system clock;
s4, acquiring a first clock frequency according to the frequency division number and the first clock number;
s5, judging whether the first clock frequency is in a preset frequency range, if so, executing a step S6, otherwise, sending an interrupt request;
s6, acquiring the image display frame rate of the VBO signal according to the total number of the lines, the total number of the fields and the first clock frequency.
2. The method of claim 1, wherein the method further comprises: and amplifying the first clock signal.
3. The method of claim 1, wherein the step S2 further comprises:
s21, acquiring the number of second clocks when the DE signal is at a high level under the system clock;
s22, judging whether the DE signal is at a high-level falling edge or not, if so, executing a step S23, otherwise, returning to execute the step S21;
s23, judging whether the number of the second clocks is within a preset numerical range; if yes, outputting the total number of lines and the total number of fields; otherwise, an interrupt request is issued.
4. The method of claim 3, wherein an upper limit of the predetermined range of values is a sum of a length value of the DE signal and a predetermined offset value, and a lower limit of the predetermined range of values is a difference between the length value of the DE signal and the predetermined offset value.
5. The method according to claim 4, wherein the step S22 further comprises: and if the second clock number is within the preset numerical range, cutting the DE signal according to the length value.
6. The method of claim 1, wherein said obtaining the first number of clocks at which the divided signal is high in the system clock of step S3 further comprises:
s31, judging whether the frequency division signal is in high level, if so, controlling the number of the first clocks to increase automatically according to a system clock, otherwise, setting the number of the first clocks to 0;
and S32, judging whether the frequency division signal is at a falling edge, if so, acquiring the current number of the first clocks, otherwise, returning to execute the step S31.
7. The method according to claim 1, wherein in the step S4, the first clock frequency is calculated based on the following formula:
(1÷Freqrx)*N＝(1÷FreqSYS)*M (1)
wherein M is the first number of clocks, N is the frequency division number, FreqrxFor said first clock frequency, FreqSYSIs a fixed system frequency.
8. The method of claim 1 or 3, wherein the method further comprises: and judging and sending the interrupt request to a micro control unit, and starting a built-in self test mode by the micro control unit according to the interrupt request and restarting signal calibration.
9. A timing controller, comprising:
the RX module is used for generating a first clock signal and a DE signal according to the VBO signal;
the resolution detection module is used for acquiring the total number of lines and the total number of fields according to the DE signal;
the clock detection module is used for carrying out frequency division on the first clock signal by using a preset frequency division number to obtain a frequency division signal and obtaining the first clock number when the frequency division signal is at a high level under a system clock;
the frequency obtaining module is used for obtaining the frequency of the first clock according to the frequency dividing number and the number of the first clock;
the frequency judging module is used for judging whether the first clock frequency is within a preset frequency range, if so, the frame rate obtaining module is called, and otherwise, an interrupt request is sent;
and the frame rate acquisition module is used for acquiring the image display frame rate of the VBO signal according to the total number of the lines, the total number of the fields and the first clock frequency.
10. A display device, characterized in that the display device comprises:
at least one processor; and
at least one memory for storing one or more computer-executable instructions;
wherein the executable instructions, when executed by the processor, cause the method of any of claims 1 to 8 to be performed.
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| CN114339107A (en) * | 2022-03-14 | 2022-04-12 | 武汉精立电子技术有限公司 | Method and device for reducing VBO signal rate and test equipment |
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| CN110895918A (en) * | 2019-06-11 | 2020-03-20 | 研祥智能科技股份有限公司 | Resolution adjustment method and system |
| CN110223657A (en) * | 2019-07-11 | 2019-09-10 | 深圳市华星光电技术有限公司 | Sequence controller and its control method |
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