CN110597744B - Data synchronous transmission method, system and computer equipment - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The invention provides a data synchronous transmission method, a system and computer equipment, wherein the method comprises the following steps: dividing a data receiving buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration; the time division multiplexing interface sends first data to the direct memory access controller; the direct memory access controller receives first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor; and the digital signal processor acquires the first data corresponding to a linked list of preset numerical values according to the first interrupt signal. The preset value is the ratio of the packing time length to the interrupt time length, the time for acquiring the first data is determined by receiving the interrupt signal times, the first data of the data quantity corresponding to the packing time length is read by the preset packing time length, the time for reading the first data and the data quantity of the first data are not influenced by a system clock, and the defect of asynchronous read-write data caused by inconsistent precision of the system clock and the clock for transmitting the data of the time division multiplexing interface is avoided.
Description
Technical Field
The present invention relates to the field of data transmission in communications, and in particular, to a method, a system, and a computer device for synchronous data transmission.
Background
Currently, in the existing voice over IP (Voice over Internet Protocol, VOIP) system, a Digital Signal Processor (DSP) reads and writes TDM data once every other packet duration, where the packet duration is obtained according to a system clock, and may be configured for 10ms, 20ms or 30ms, in order to improve transmission efficiency, a DMA controller is added between the DSP and the TDM interface, and the DMA controller stores the data to be transmitted in a buffer area. For data writing, in order to prevent the DMA controller from moving the data which is outdated in the memory to the TDM interface, mute data of 10-30 ms needs to be reserved, that is, the current frame in the sending direction is moved backward for a certain safety distance, called txGap, whereas for data reading, in order to avoid moving the data which is outdated in the memory to the DSP, the current frame in the receiving direction needs to be moved forward for a certain safety distance, called rxGap, and in theory, the reserved Gap should be consistent with the clock calculated every time, but due to the fact that the clock for determining the interruption of the TDM interface is different from the precision of the system clock for determining the packing duration, the Gap is larger and larger along with the time, and the accumulated data signal is discarded or covered.
Accordingly, there is a need for further improvements in the art.
Disclosure of Invention
In view of the shortcomings of the prior art, the invention provides a data synchronous transmission method, a system and computer equipment, which aim to solve the technical problem that data transmission cannot be synchronous due to inconsistent clock input of a TDM interface and a system clock.
In a first aspect, an embodiment of the present invention provides a method for synchronously transmitting data; the method comprises the following steps:
dividing a data receiving buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration;
the time division multiplexing interface sends first data to the direct memory access controller;
the direct memory access controller receives first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor;
and the digital signal processor acquires the first data corresponding to a linked list of preset numerical values according to the first interrupt signal.
As a further improvement, the data receiving buffer area includes a plurality of linked lists, and the direct memory access controller receives the first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor, including:
And for each linked list, the linked list receives first data corresponding to one interrupt duration sent by the time division multiplexing interface, and then sends a first interrupt signal to the digital signal processor.
As a further improved technical solution, the obtaining, by the digital signal processor, the first data corresponding to the linked list of the preset number according to the first interrupt signal includes:
each time the digital signal processor receives a first interrupt signal sent by the direct memory access controller, the digital signal processor controls the value of the first counter to be increased by 1;
the digital signal processor judges whether the value of the first counter is equal to a preset value;
and if the numerical value of the first counter is equal to a preset numerical value, the digital signal processor acquires first data corresponding to the linked list of the preset numerical value from the direct memory access controller and controls the first counter to be cleared.
As a further improvement, the method further comprises:
presetting the interrupt duration of the time division multiplexing interface;
presetting the packing time length of the digital signal processor;
calculating the ratio of the packing time length to the interrupt time length, and taking the ratio as a preset value.
In a second aspect, an embodiment of the present invention provides a method for synchronously transmitting data, where the method includes:
dividing a data transmission buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration;
the digital signal processor sends second data to the direct memory access controller;
the direct memory access controller receives second data sent by the digital signal processor and sends a second interrupt signal to the digital signal processor;
and the time division multiplexing interface receives the second data transmitted through a linked list.
As a further improvement, the data transmission buffer area includes a plurality of linked lists, and the direct memory access controller receives the second data transmitted by the digital signal processor and transmits a second interrupt signal to the digital signal processor, including:
and for each linked list, the linked list receives second data corresponding to one interrupt duration sent by the digital signal processor, and then sends a second interrupt signal to the digital signal processor.
As a further improvement, after the sending the second interrupt signal to the digital signal processor, the method further includes:
Each time the digital signal processor receives a second interrupt signal sent by the direct memory access controller, the digital signal processor controls the value of the second counter to be increased by 1;
the digital signal processor judges whether the value of the second counter is equal to a preset value;
and if the numerical value of the second counter is equal to a preset numerical value, the digital signal processor sends second data to the direct memory access controller and controls the second counter to be cleared, wherein the data quantity of the second data corresponds to the packing time length.
In a third aspect, an embodiment of the present invention provides a data synchronous transmission system, including: a direct memory access controller, a time division multiplexing interface and a digital signal processor;
the direct memory access controller includes a data receiving buffer;
the direct memory access controller is used for dividing a data receiving buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration;
the time division multiplexing interface is used for sending first data to the direct memory access controller;
The direct memory access controller is further configured to receive the first data sent by the time division multiplexing interface, and send a first interrupt signal to the digital signal processor;
the digital signal processor is used for acquiring the first data corresponding to a preset numerical value linked list according to the first interrupt signal;
the direct memory access controller also comprises a data transmission buffer area;
the direct memory access controller is further configured to divide a data transmission buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, where one linked list stores a data amount corresponding to the preset interrupt duration;
the digital signal processor is used for sending second data to the direct memory access controller;
the direct memory access controller is further configured to receive the second data sent by the digital signal processor, and send a second interrupt signal to the digital signal processor;
the time division multiplexing interface is further configured to receive the second data transmitted through the linked list.
In a fourth aspect, an embodiment of the present invention provides a computer device, including a memory and a processor, where the memory stores a computer program, and the processor implements the following steps when executing the computer program:
Dividing a data receiving buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration;
the time division multiplexing interface sends first data to the direct memory access controller;
the direct memory access controller receives first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor;
the digital signal processor acquires the first data corresponding to a linked list of preset numerical values according to the first interrupt signal;
or dividing the data transmission buffer area of the direct memory access controller into a plurality of linked lists in advance according to the preset interrupt duration, wherein one linked list stores the data quantity corresponding to the preset interrupt duration;
the digital signal processor sends second data to the direct memory access controller;
the direct memory access controller receives second data sent by the digital signal processor and sends a second interrupt signal to the digital signal processor;
and the time division multiplexing interface receives the second data transmitted through a linked list.
In a fifth aspect, embodiments of the present invention provide a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:
Dividing a data receiving buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration;
the time division multiplexing interface sends first data to the direct memory access controller;
the direct memory access controller receives first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor;
the digital signal processor acquires the first data corresponding to a linked list of preset numerical values according to the first interrupt signal;
or dividing the data transmission buffer area of the direct memory access controller into a plurality of linked lists in advance according to the preset interrupt duration, wherein one linked list stores the data quantity corresponding to the preset interrupt duration;
the digital signal processor sends second data to the direct memory access controller;
the direct memory access controller receives second data sent by the digital signal processor and sends a second interrupt signal to the digital signal processor;
and the time division multiplexing interface receives the second data transmitted through a linked list.
Compared with the prior art, the embodiment of the invention has the following advantages:
The method provided by the embodiment of the invention comprises the following steps: dividing a data receiving buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration; the time division multiplexing interface sends first data to the direct memory access controller; the direct memory access controller receives first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor; and the digital signal processor acquires the first data corresponding to a linked list of preset numerical values according to the first interrupt signal. In the invention, when the direct memory access controller finishes the transmission of one linked list, a first interrupt signal is sent to the digital signal processor, the digital signal processor determines the time for acquiring the first data by receiving the interrupt signal, and reads the first data of the data quantity corresponding to the packaging time length by the preset packaging time length, the time for reading the first data and the data quantity of the first data are not influenced by a system clock, and the defect of asynchronous read-write data caused by inconsistent precision of the system clock and the clock for transmitting the data of the time division multiplexing interface is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
Fig. 1 is a flowchart of a data synchronous transmission method according to a first embodiment of the present invention;
fig. 2 is a flowchart of a data synchronous transmission method according to a second embodiment of the present invention;
FIG. 3 is a flow chart illustrating data transmission during data reading according to a first embodiment of the present invention;
FIG. 4 is a flow chart of data transmission during data writing according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a data synchronous transmission system according to a third embodiment of the present invention;
fig. 6 is an internal structural view of a computer device according to a fourth embodiment of the present invention.
Detailed Description
In order to make the present invention better understood by those skilled in the art, the following description will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Various non-limiting embodiments of the present invention are described in detail below with reference to the attached drawing figures.
Referring to fig. 1, a data synchronous transmission method provided by a first embodiment of the present invention is applied to a data synchronous transmission system, where the data synchronous transmission system includes: a Direct Memory Access (DMA) controller, a Time Division Multiplexing (TDM) interface, and a Digital Signal Processor (DSP); the method comprises the following steps:
s1, dividing a data receiving buffer area of a direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data volume corresponding to the preset interrupt duration.
In a first embodiment, the DMA controller includes a data receiving buffer and a data transmitting buffer, and the first embodiment of the present invention provides a data reading method, wherein a data reading path is to move data from the TDM interface to the DSP, the DMA controller receives data transmitted by the TDM interface, and the received data is stored in the data receiving buffer. The data receiving buffer is used for buffering the data of the TDM interface so that the DSP can acquire the data from the data receiving buffer.
The method further comprises the following steps before the step S1:
s01, presetting the interrupt duration of the time division multiplexing interface.
In the first embodiment, the interrupt duration of the TDM interface is determined by the clock of the FPGA, and preferably, the interrupt duration is 5ms.
S02, presetting the packing time length of the digital signal processor.
In the prior art, the packing time length is determined according to the system clock, and 10ms, 20ms or 30ms can be configured, but the data transmission is asynchronous due to the fact that the clock precision of the system clock and the clock precision of the FPGA are different, and the difference of the asynchronous data transmission is larger and larger along with the accumulation of time. In the embodiment of the invention, the packing time length is not determined according to the system clock, but the packing time length is set, for example, the packing time length can be set to be 10ms or 20ms, and in one implementation manner, the packing time length is set to be 10ms.
S03, calculating the ratio of the packing time length to the interrupt time length, and taking the ratio as a preset value.
In the first embodiment, the ratio of the packing duration to the interrupt duration is taken as a preset value, for example, when the interrupt duration is 5ms and the packing duration is 20ms, the preset value is 4, for example, when the interrupt duration is 5ms and the packing duration is 10ms, the preset value is 2.
In the first embodiment, before the start of reading and writing, a data receiving buffer of the DMA controller is applied in advance, and it is assumed that a frame corresponds to 125us,1ms is 8 frames, the interrupt duration is 40 frames, each frame has 32 slots, and when a channel is used, the data amount corresponding to 5ms is 5×8×32, that is, the data amount transmitted by one interrupt duration is 5×8×32. The data receiving buffer of 500ms can store 500 x 8 x 32 data.
In the first embodiment, it is assumed that a 500ms data receiving buffer is applied, and the data receiving buffer is divided into 100 linked lists according to an interrupt duration of 5ms, where the linked list is a storage structure in the buffer, and one linked list can store a data amount corresponding to 5 ms.
S2, the time division multiplexing interface sends the first data to the direct memory access controller.
In the first embodiment, there is continuous data transfer from the TDM interface to the DMA controller as long as the TDM interface is enabled.
S3, the direct memory access controller receives the first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor.
In a first embodiment, where the TDM interface is enabled first, the first embodiment of the present invention provides a data reading method, there is continuous data transfer from the TDM interface to the DMA controller as long as the TDM interface is enabled. Specifically, step S3 includes:
s31, for each linked list, the linked list receives first data corresponding to one interrupt duration sent by the time division multiplexing interface, and then sends a first interrupt signal to the digital signal processor.
In the first embodiment, the TDM interface sends first data to the DMA controller, where the first data is buffered in the data receiving buffer, and the data receiving buffer is divided into a plurality of linked lists, in the above example, the data receiving buffer is divided into 100 linked lists according to the interrupt duration of 5ms, and a first interrupt signal is generated by transmitting one data according to the linked lists. And when the data quantity stored in each linked list is the data quantity corresponding to one interrupt duration, and after one linked list receives the data quantity corresponding to one interrupt duration sent by the TDM interface, namely the transmission of one linked list is completed, a first interrupt signal is sent to the digital signal processor.
In the first embodiment, different linked list transmissions are distinguished by different controller descriptors, for example, in the data reading direction, for one channel of the DMA controller, in the above example, a data receiving buffer of 500ms is applied, 100 controller descriptors may be applied to divide the 500ms data into 100 small buffers (buffers) for transmission, the address of the first controller is set to the address of the first small buffer, the length is set to the length of the small buffer, the address of the second controller is set to the address of the second small buffer, the length device is set to the length of the small buffer, and so on, the address of the 100 th controller is set to the address of the 100 th small buffer, the length is set to the length of the small buffer, in order to implement the cyclic buffer, the address of the 101 th controller is set to the address of the first small buffer, and then the cyclic of the 100 linked lists is implemented. When the data of one linked list is interrupted and opened, the completion of the transmission of each linked list can be realized, and a first interrupt signal is sent to the processor.
S4, the digital signal processor acquires the first data corresponding to a linked list of preset numerical values according to the first interrupt signal.
Specifically, step S4 includes:
s41, the digital signal processor controls the value of the first counter to be increased by 1 when receiving the first interrupt signal sent by the direct memory access controller once.
In a first embodiment, the DMA controller sends an interrupt signal to the DSP to inform the DSP that the DSP has available the first data corresponding to an interrupt duration, and controls the first counter to increment by 1 each time the DSP receives the first interrupt signal.
S42, the digital signal processor judges whether the numerical value of the first counter is equal to a preset numerical value.
And S43, if the numerical value of the first counter is equal to a preset numerical value, the digital signal processor acquires first data corresponding to the linked list of the preset numerical value from the direct memory access controller, and controls the first counter to be cleared.
In the first embodiment, if the value of the first counter is equal to the preset value, it indicates that the DMA controller has received the first data of the data amount corresponding to the packing duration, for example, the interrupt duration is 5ms, the packing duration is 10ms, the preset value is 2, and when the value of the first counter is 2, it indicates that two linked lists in the DMA controller have been transmitted, that is, the DMA controller has received the first data corresponding to 10ms sent by the TDM interface. When the value of the first counter is 2, the DSP acquires first data corresponding to the 2 linked lists and clears the first counter.
Through the process, the DSP finishes reading the first data corresponding to one-time packing duration, the value of the first counter is 0 at the moment, when the DMA controller receives the first data corresponding to one interrupt duration again, the DSP controls the first counter to be increased by 1 according to the received first interrupt signal until the value of the first counter is equal to a preset value, and the DSP reads the first data corresponding to a plurality of linked lists with the preset value again, and the process is repeated.
In the prior art, when the system clock time reaches the packing time length, the DSP reads the first data once, and according to the process of the invention, the generation reality of the first interrupt signal is determined according to the data quantity corresponding to the interrupt time length, namely, the first interrupt signal is generated after the transmission of one linked list (the data quantity corresponding to the interrupt time length is one linked list) is completed, so that the interrupt corresponding to the accurate interrupt time length can be obtained, the DSP acquires the first data in the DMA controller according to the relation between the number of times of the received first interrupt signal and the preset value, when the data quantity of the first data stored in the DMA controller reaches the data quantity corresponding to the packing time length, the first data is read once, the time for reading the data is determined according to the data quantity, and the whole process is not influenced by the system clock, thereby avoiding the defect of asynchronous read and write data caused by inconsistent clock precision of the data transmission of the system clock and the time division multiplexing interface.
In the first embodiment, the first interrupt signal is generated on a channel where the DMA controller reads data, and the channel where the DMA controller writes data may perform data writing based on the first interrupt signal. I.e. at the same point of interruption, the DSP will handle the data transmission of the multiple channels.
Specifically, in the first embodiment, the DSP sends data to be written to the data sending buffer area of the DMA controller, where the data to be written is data transferred in the writing channel of the DMA controller. In the transmission of the data to be written, taking the first interrupt signal as the reference, controlling a second counter to be added with 1 when receiving one first interrupt signal, if the value of the second counter reaches a preset value, sending second data corresponding to a packing duration to the DMA controller by the DSP, and resetting the second counter; and sending the data to be written corresponding to the packing time to the DMA control register until the value of the second counter reaches the preset value again, and repeating the steps.
For example, assuming that the packing duration is 20ms, a linked list transmits the data amount corresponding to the interrupt duration of 5ms, and the preset value is 4; the DSP receives a first interrupt signal, controls the value of a second counter to be increased by 1 every time the interrupt signal is received, when the value of the second counter is 4, sends data to be written of a data quantity corresponding to a packing time length to the DMA controller, when the second data is written, the DSP reads a physical address of the current data to be written, and adds a reserved Gap on the basis of the physical address, namely a read-write position Pos where the DSP performs software operation, when the data to be written is transmitted to the DMA controller for the first time, the address of the first controller can be set as the address of a first small buffer, and the length of the first small buffer is the data quantity corresponding to the packing time length, namely the length of 4 small buffers.
Referring to fig. 2, a data synchronous transmission method according to a second embodiment of the present invention is applied to a data synchronous transmission system, where the data synchronous transmission system includes: a Direct Memory Access (DMA) controller, a Time Division Multiplexing (TDM) interface, and a Digital Signal Processor (DSP); the method comprises the following steps:
k1, dividing a data transmission buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data volume corresponding to the preset interrupt duration.
In a second embodiment of the present invention, a method for synchronously transmitting data in a data write path is provided, in which a DMA controller receives data transmitted by a DSP and stores the received data in a data transmission buffer.
Specifically, before step K1, the method further includes:
and K01, presetting the interrupt duration of the time division multiplexing interface.
In a second embodiment, the interrupt duration of the TDM interface is determined by the clock of the FPGA, preferably the interrupt duration is 5ms.
And K02, presetting the packing time length of the digital signal processor.
In the prior art, the packing time length is determined according to the system clock, and 10ms, 20ms or 30ms can be configured, but the data transmission is asynchronous due to the fact that the clock precision of the system clock and the clock precision of the FPGA are different, and the difference of the asynchronous data transmission is larger and larger along with the accumulation of time. In the embodiment of the invention, the packing time length is not determined according to the system clock, but the packing time length is set, for example, the packing time length can be set to be 10ms or 20ms, and preferably, the packing time length is set to be 10ms.
And K03, calculating the ratio of the packing time length to the interrupt time length, and taking the ratio as a preset value.
K2, the digital signal processor sends the second data to the direct memory access controller.
In the second embodiment, the DSP sends the second data with the data amount corresponding to one packing duration to the DMA controller at a time, for example, the preset packing duration is 10ms, the data amount corresponding to 10×8×32 is 10×8×32, and then sends the second data with the data amount of 10×8×32 to the DMA controller.
K3, the direct memory access controller receives the second data sent by the digital signal processor, sends the second data to a time division multiplexing interface, and sends a second interrupt signal to the digital signal processor.
The second embodiment differs from the first embodiment in that: the first embodiment is to generate an interrupt on a channel where data is read, and the second embodiment is to generate an interrupt on a channel where data is written, the second data being data transferred in a DMA channel where data is written.
In the second embodiment, for the DMA controller, the data size of the second data received once is 10×8×32, and two linked lists need to be stored.
Specifically, the data transmission buffer area includes a plurality of linked lists, and in step K3, the direct memory access controller receives the second data transmitted by the digital signal processor and transmits a second interrupt signal to the digital signal processor, including:
And K31, for each linked list, sending second data corresponding to the interrupt duration to a time division multiplexing interface by the linked list, and sending a second interrupt signal to the digital signal processor.
In a second embodiment, each linked list transmission is completed and a second interrupt signal is sent to the digital signal processor. In the above example, the preset packing duration is 10ms, the data amount corresponding to 10ms is 10×8×32, the data amount of the second data received once is 10×8×32, one linked list transmits the data amount corresponding to 5ms, the second data of the packing duration that is once sent to the DMA controller by the DSP needs to be stored in two linked lists, that is, the two linked lists transmit the second data corresponding to one packing duration only after completing, and each time one linked list is transmitted, the second interrupt signal is sent to the digital signal processor once.
And K4, the time division multiplexing interface receives the second data transmitted through the linked list.
In a second embodiment, the TDM interface receives second data; in the above example, for the second data corresponding to one packing duration, the TDM interface needs to receive the second data transmitted by two linked lists, for example, the interrupt duration is 5ms, the packing duration is 10ms, the preset value is 2, and the second data corresponding to 10ms needs to be acquired twice.
Steps K1 to K4 are a process of data writing. In the second embodiment, the DSP does not determine the time of transmitting the second data according to the time interval of the system clock, but determines the time point of transmitting the second data according to the data amount corresponding to the set packing period and the number of times of receiving the second interrupt signal.
In the second embodiment, after the DMA controller sends the second data corresponding to one linked list to the TDM interface, the DMA controller sends a second interrupt signal to the DSP, the DSP controls the counter to be incremented by 1 according to the received second interrupt signal, and when the value of the counter is equal to a preset value, the DSP sends the second data corresponding to the packing duration to the TDM interface again, and the counter is reset to zero. Specifically, step K3 includes:
m1: and the digital signal processor controls the value of the second counter to be increased by 1 every time the digital signal processor receives the second interrupt signal sent by the direct memory access controller.
And each time the DSP receives a second interrupt signal, the second counter is controlled to be increased by 1. For example, in the above example, after the TDM interface obtains the second data corresponding to one linked list, the DMA controller sends the second interrupt signal to the DSP, the DSP controls the counter to be added with 1, the counter is added with 1, and after the TDM interface obtains the second data corresponding to one linked list again, the DMA controller sends the second interrupt signal to the DSP, the DSP controls the counter to be added with 1, and at this time, the counter is added with 2.
M2: the digital signal processor judges whether the value of the second counter is equal to a preset value;
m3: and if the numerical value of the second counter is equal to a preset numerical value, the digital signal processor sends second data to the direct memory access controller and controls the second counter to be cleared, wherein the data quantity of the second data corresponds to the packing time length.
In the second embodiment, assuming that the packing duration is 10ms and the interrupt duration is 5ms, the preset value is 2. If the value of the second counter is equal to 2 and equal to the preset value, the DSP sends the second data corresponding to the packing time length to the TDM interface again, and the counter is set to zero. Through the steps, the DSP receives the second interrupt signals twice and then sends the second data once to the DMA controller, after sending the second data, the DSP controls the second counter to clear, and then waits for the second interrupt signals until receiving the second interrupt signals twice again, and then sends the second data once to the DMA controller, and the steps are repeated.
In the prior art, in the process of writing data, when the system clock reaches the packaging time length, the DSP sends primary data to the DMA controller, the data quantity sent at the moment corresponds to the packaging time length, and the packaging time length is determined by the system clock, so that the data quantity of the primary data sent is influenced by the system clock, and the data transmission is asynchronous due to the fact that the clock precision of the system clock is different from that of the TDM interface and accumulated along with time. In the fourth embodiment, the DSP transmits the second data according to the reception interrupt signal, and the data amount of the transmitted second data corresponds to the packing time length, that is, the second data of the data amount corresponding to the fixed transmission packing time length is not affected by the system clock. Therefore, the defect of asynchronous read-write data caused by inconsistent precision of a system clock and a clock for transmitting data of the time division multiplexing interface is avoided.
Referring to fig. 3, during data reading, that is, the process of the DMA controller moving data from the TDM interface to the DSP memory:
the TDM interface transmits the first data to the DMA controller;
b1. after receiving first data corresponding to a linked list, the DMA controller sends a first interrupt signal to the DSP;
c1. the DSP controls the first counter to be increased by 1 according to the received first interrupt signal;
d1. The DSP judges whether the value of the first counter is larger than a preset value, if so, the first counter is controlled to be cleared and the step e1 is carried out;
and e1. The DSP acquires first data corresponding to a plurality of linked lists with preset values, namely acquires first data of data quantity corresponding to the packing time length.
Referring to fig. 4, when data is written, i.e., the DMA controller moves the data from the DSP memory to the TDM interface:
a2, the DSP sends second data of the data quantity corresponding to the packing time length to the DMA controller;
b2. the DMA controller receives second data corresponding to a packing time length;
every time the DMA controller sends second data corresponding to one linked list to the TDM interface, a second interrupt signal is sent to the DSP;
d2. The DSP controls the second counter to be increased by 1 according to the received second interrupt signal;
step 2, the DSP judges whether the value of the second counter is larger than a preset value, if so, the second counter is controlled to be cleared, and the step a2 is carried out;
Based on the above-mentioned data synchronous transmission method, a third embodiment of the present invention further provides a data synchronous transmission system, referring to fig. 5, where the system includes:
the data synchronous transmission system comprises: a direct memory access controller 20, a time division multiplexing interface 10, and a digital signal processor 30;
the direct memory access controller 20 includes a data receiving buffer;
the direct memory access controller 20 is configured to divide the data receiving buffer of the direct memory access controller 20 into a plurality of linked lists in advance according to a preset interrupt duration, where one linked list stores a data amount corresponding to the preset interrupt duration;
the time division multiplexing interface 10 is configured to send first data to the direct memory access controller 20;
the direct memory access controller 20 is further configured to receive the first data sent by the time division multiplexing interface 10, and send a first interrupt signal to the digital signal processor 30;
the digital signal processor 30 is configured to obtain, according to the first interrupt signal, the first data corresponding to a linked list of preset values;
the direct memory access controller 20 further includes a data transmission buffer;
The direct memory access controller 20 is further configured to divide the data transmission buffer of the direct memory access controller 20 into a plurality of linked lists in advance according to a preset interrupt duration, where one linked list stores a data amount corresponding to the preset interrupt duration;
the digital signal processor 30 is configured to send second data to the direct memory access controller 20;
the direct memory access controller 20 is further configured to receive the second data sent by the digital signal processor 30, and send a second interrupt signal to the digital signal processor 30;
the time division multiplexing interface 10 is further configured to obtain the second data through linked list transmission.
Referring to fig. 6, there is shown a computer device, which may be a terminal, according to a fourth embodiment of the present invention, the internal structure of which is shown in fig. 6. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of data synchronous transmission. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those skilled in the art that the block diagram of fig. 6 is merely a partial structure related to the present application and does not constitute a limitation of the computer device to which the present application is applied, and that a specific computer device may include more or less components than those shown in the drawings, or may combine some components, or have a different arrangement of components.
A fourth embodiment of the invention provides a computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor when executing the computer program realizes the steps of:
dividing a data receiving buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration;
the time division multiplexing interface sends first data to the direct memory access controller;
the direct memory access controller receives first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor;
the digital signal processor acquires the first data corresponding to a linked list of preset numerical values according to the first interrupt signal;
Or dividing the data transmission buffer area of the direct memory access controller into a plurality of linked lists in advance according to the preset interrupt duration, wherein one linked list stores the data quantity corresponding to the preset interrupt duration;
the digital signal processor sends second data to the direct memory access controller;
the direct memory access controller receives second data sent by the digital signal processor and sends a second interrupt signal to the digital signal processor;
and the time division multiplexing interface transmits and receives the second data through a linked list.
The fifth embodiment of the present invention also provides a computer-readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor realizes the steps of:
dividing a data receiving buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration;
the time division multiplexing interface sends first data to the direct memory access controller;
the direct memory access controller receives first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor;
The digital signal processor acquires the first data corresponding to a linked list of preset numerical values according to the first interrupt signal;
or dividing the data transmission buffer area of the direct memory access controller into a plurality of linked lists in advance according to the preset interrupt duration, wherein one linked list stores the data quantity corresponding to the preset interrupt duration;
the digital signal processor sends second data to the direct memory access controller;
the direct memory access controller receives second data sent by the digital signal processor and sends a second interrupt signal to the digital signal processor;
and the time division multiplexing interface transmits and receives the second data through a linked list.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (7)
1. A data synchronous transmission method is characterized in that; the method comprises the following steps:
dividing a data receiving buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration;
the time division multiplexing interface sends first data to the direct memory access controller;
the direct memory access controller receives first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor;
the digital signal processor acquires the first data corresponding to a linked list of preset numerical values according to the first interrupt signal;
the data receiving buffer area comprises a plurality of linked lists, the direct memory access controller receives first data sent by the time division multiplexing interface and sends a first interrupt signal to the digital signal processor, and the method comprises the following steps:
For each linked list, the linked list receives first data corresponding to one interrupt duration sent by the time division multiplexing interface, and then sends a first interrupt signal to the digital signal processor;
the digital signal processor obtains the first data corresponding to a plurality of linked lists with preset values according to the first interrupt signal, and the method comprises the following steps:
each time the digital signal processor receives a first interrupt signal sent by the direct memory access controller, the digital signal processor controls the value of the first counter to be increased by 1;
the digital signal processor judges whether the value of the first counter is equal to a preset value;
if the value of the first counter is equal to a preset value, the digital signal processor acquires first data corresponding to a plurality of linked lists of the preset value from the direct memory access controller, and controls the first counter to be cleared;
the direct memory access controller writes the data channel in accordance with the first interrupt signal.
2. The method according to claim 1, wherein the method further comprises:
presetting the interrupt duration of the time division multiplexing interface;
presetting the packing time length of the digital signal processor;
Calculating the ratio of the packing time length to the interrupt time length, and taking the ratio as a preset value.
3. A method for synchronously transmitting data, the method further comprising:
dividing a data transmission buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration;
the digital signal processor sends second data to the direct memory access controller;
the direct memory access controller receives second data sent by the digital signal processor, sends the second data to a time division multiplexing interface, and sends a second interrupt signal to the digital signal processor;
the time division multiplexing interface receives the second data transmitted through a linked list;
the data transmission buffer zone comprises a plurality of linked lists, and the steps of transmitting the second data to a time division multiplexing interface and transmitting a second interrupt signal to a digital signal processor comprise:
for each linked list, the linked list sends second data corresponding to the interrupt duration to a time division multiplexing interface, and then sends a second interrupt signal to the digital signal processor;
The data signal processor determines a time point for transmitting the second data according to the data quantity corresponding to the set packing time length and the times for receiving the second interrupt signal.
4. The method of claim 3, further comprising, after the sending the second interrupt signal to the digital signal processor:
each time the digital signal processor receives a second interrupt signal sent by the direct memory access controller, the digital signal processor controls the value of the second counter to be increased by 1;
the digital signal processor judges whether the value of the second counter is equal to a preset value;
and if the numerical value of the second counter is equal to a preset numerical value, the digital signal processor sends second data to the direct memory access controller and controls the second counter to be cleared, wherein the data quantity of the second data corresponds to the packing time length.
5. A data synchronous transmission system, characterized in that the data synchronous transmission system comprises: a direct memory access controller, a time division multiplexing interface and a digital signal processor;
the direct memory access controller includes a data receiving buffer;
the direct memory access controller is used for dividing a data receiving buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, wherein one linked list stores a data amount corresponding to the preset interrupt duration;
The time division multiplexing interface is used for sending first data to the direct memory access controller;
the direct memory access controller is further configured to receive the first data sent by the time division multiplexing interface, and send a first interrupt signal to the digital signal processor;
the digital signal processor is used for acquiring the first data corresponding to a preset numerical value linked list according to the first interrupt signal;
the direct memory access controller also comprises a data transmission buffer area;
the direct memory access controller is further configured to divide a data transmission buffer area of the direct memory access controller into a plurality of linked lists in advance according to a preset interrupt duration, where one linked list stores a data amount corresponding to the preset interrupt duration;
the digital signal processor is used for sending second data to the direct memory access controller;
the direct memory access controller is further configured to receive the second data sent by the digital signal processor, and send a second interrupt signal to the digital signal processor;
the time division multiplexing interface is further used for receiving the second data transmitted through the linked list;
the direct memory access controller is further configured to generate a first interrupt signal on a channel for reading data;
The digital signal processor is further configured to determine a time point of sending the second data according to the data amount corresponding to the set packing duration and the number of times of receiving the second interrupt signal.
6. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 4 when the computer program is executed.
7. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method according to any one of claims 1 to 4.
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