CN111462651A

CN111462651A - Light-emitting display substrate for assembling surface-mounted micro L ED fluid and preparation method

Info

Publication number: CN111462651A
Application number: CN202010351855.4A
Authority: CN
Inventors: 保罗·约翰·舒勒; 战长青; 佐佐木健司; 葛特鄂孟; 李宗霑
Original assignee: Elevision Co ltd
Current assignee: Elevision Co ltd; eLux Inc
Priority date: 2019-05-08
Filing date: 2020-04-28
Publication date: 2020-07-28
Anticipated expiration: 2040-04-28
Also published as: TW202042287A; TWI750650B; CN111462651B

Abstract

A light emitting display substrate for surface mount micro L ED fluid assembly and a method of fabricating the same are provided, the light emitting display substrate including a support substrate having a planar top surface and a light emitting diode (L ED) cross-point control matrix including an array of column and row wires, a first thin film layer covering the top surface of the support substrate and including a plurality of wells, wherein each well has a convex bottom surface, a first substrate electrode connected to a corresponding column wire, and a second substrate electrode connected to a corresponding row wire.

Description

Light-emitting display substrate for assembling surface-mounted micro L ED fluid and preparation method

Technical Field

The present invention relates generally to display technology and more particularly to the design of Surface Mount (SM) inorganic micro light emitting diodes (μ L ED) with improved electrode interface surface flatness.

Background

A color display consists of pixels that emit light at three wavelengths corresponding to the visible red, green, and blue colors, referred to as an RGB display, the RGB elements of the pixels are turned on and off in an orderly fashion to accumulate the colors that produce the visible spectrum, there are several display types that can generate RGB images in different ways.A liquid crystal display (L CD) is the most popular technology that illuminates a white light source (typically a phosphor-produced white L ED) through the color filters of the subpixels to produce RGB images.

A third display technology is miniature L ED displays, which use micron-sized (10 to 150 μm in diameter) inorganic L ED to directly emit light at the pixel level.to fabricate RGB displays using miniature L ED, large area arrays of three different types of miniature L ED, each emitting in each RGB wavelength range, must be assembled.

Practical display technologies must address the realities of displays manufactured at different sizes and resolutions, thus requiring flexibility in pixel size, from 300 pixels per inch (ppi) for personal devices to very high 10-20ppi large public information display applications, display screen brightness requirements also vary from application to application, 300 nit (candela per square meter) for cell phone displays, 1000 nit for televisions, and 5000 nit for outdoor information displays.

The development of blue L ED based on gallium nitride (GaN) for general illumination and aluminum gallium phosphide (AlGaInP) red L ED for various indicator lamps has been developed for many generations and these processes can produce reliable and efficient devices at very low cost, therefore, perhaps the most important requirement is that the micro L ED structure be compatible with conventional Metal Organic Chemical Vapor Deposition (MOCVD) manufacturing of commercial inorganic L ED L2 ED there are many possible variations in manufacturing L2 ED, therefore, this summary provides only a very brief overview to identify the factors required to manufacture high quality L ED, while also describing the unique differences between the conventional L ED and the micro L ED described herein, the light emitting diodes, the solid state lighting technology and application series 4 (swing, wing, InGaN material system and blue/green emitters ", L i, Jinmin, Zhang, schg. q. (braising), light emitting diodes, the solid state lighting technology and application series 4 (swing, wing, Yang, and AlGaInP 2019, wai) for the light emitting diodes, the" green emitters ", the Jinmin, and algaind 19, jingan, and yellow light emitting technologies" the light emitting diode, phosphor series "(swinglange, swing4, swingning, swing4, wain, swing4, and algaing, lange, algaing, lange, czeen, k, r, and r series).

Fig. 1A-1C are diagrams (prior art) depicting a GaN L ED wafer for general illumination purposes, a blue (about 440 nanometers (nm)) and green (about 530nm) emitting GaN-based L EDs are fabricated in a series of complex high temperature MOCVD steps to produce the vertical L ED structure shown in cross-section in fig. 1A. fabrication is performed on a polished sapphire, silicon (Si), or silicon carbide (SiC) growth substrate of 50 to 200 millimeters (mm) diameter.

After initial growth to produce a crystalline GaN surface, a first L ED layer is grown and Si doping is added to produce n + GaN (n-GaN) for the cathode_xGa_1-xN) and GaN, where the indium content and the thickness of the layers determine the wavelength of the emitted light of the device, an increase in indium content shifts the emission peak to longer wavelengths, but internal stresses are also increased due to lattice mismatch, thus making it impossible to fabricate high efficiency GaN devices for red emission, green emitting devices with efficiency lower than that of blue L ED.

The completed substrate was then patterned and etched to form individual L EDs, and additional processing was performed to form electrodes on the anode and cathode, as shown in FIG. 1B in the simplest process flow, by depositing nickel oxide (NiO)_x) To match the p + GaN (p-GaN) work function, and then depositing a layer of Indium Tin Oxide (ITO) 100 to 300nm thick to form a transparent conductive electrode. This layer is patterned and etched to form a current spreading layer over the anode.

A small area is patterned and etched through the stack to make contact with the n + GaN. Passivation layer, typically silicon dioxide (SiO)₂) Deposited to prevent leakage current between the anode and cathode, and provided with a contact window above the electrode. Electrodes (typically made of titanium/aluminum (Ti/Al)) are deposited to form the cathode contact points, and a second electrode (anode) is added, which may be nickel/gold (Ni/Au), chromium/gold (Cr/Au), or the like. The substrate is thinned to about 100 μm by grinding and the individual devices are singulated by cutting or sawing. The devices produced by this process are typically 100 μmThick and of a size (cross-section) of 150 to 1000 μm, for example as shown in fig. 1C.

Fig. 2A and 2B are diagrams (prior art) showing gallium arsenide (GaAs) L ED wafers used to make red emitting light indicators, as shown in fig. 2A, the high brightness red L ED. growth substrate is a few hundred microns thick n-doped GaAs wafer, the first layer deposited is GaAs to produce a high quality crystal surface, the next layer is aluminum/arsenide (AlAs), which is then used as a release layer L ED stack may start with an optional n-doped Distributed Bragg Reflector (DBR) layer or n-doped inp GaInP window layer and n-doped inp algaap cladding layer, then alternating layers of AlGaInP and AlGaAs are deposited on the MQW active region and adjusted in thickness and composition to make the high efficiency L ED emit light at a selected wavelength, the active region is covered with a p-doped and p-doped GaInP cladding layers to complete L a total L ED thickness over the AlAs release layer may be 10 to 15 μm.

The GaAs growth substrate is lattice matched to the MOCVD growth of AlGaInP, but GaAs is light absorbing and very brittle, which is a serious drawback for L ED packages therefore, as shown in FIG. 2B, L ED devices are removed from the substrate by etching the substrate completely or by undercutting and releasing the devices using selective wet etching (typically hydrochloric acid (HCl): acetic acid). Prior to remove L ED from the substrate, a thick layer of copper is deposited by electroplating as the process interface for the heat spreader and each device.

FIGS. 3A and 3B depict partial cross-sectional views of a conventional packaged blue and red L ED (Prior Art) respectively, which are presented to distinguish between a micro L ED (provided in the detailed description below) and a conventional packaging technique for a larger L ED for general illumination, white light is generated by a blue-emitting GaN device, as shown in FIG. 1B, with an overlayL ED and converts some of the blue light to longer wavelengths, typically broad yellow emitting phosphors, such as cerium (III) doped YAG (YAG: Ce)^3-Or Y₃Al₅O₁₂：Ce³⁺) The package used has a lead frame for making electrical connections, a heat sink for dissipating the heat energy generated in L ED and a reflector to direct the light to the user L ED is bonded to the heat sink by a thermally conductive glue, L ED terminals are connected to the lead frame by wire bonding, after bonding, the package cavity will be filled with a transparent encapsulant, typically silicone or epoxy, which protects the device from mechanical damage and from air and water in the environment.

As described in more detail below, micro L ED dimensions and internal structures are created by using conventional photolithography processes to form patterns controlled by mask design, film thickness, and photoresist exposure.Using the photolithography patterns as masks, the etching process selectively removes material to form features of the complete device.

For the purpose of minimizing failures in the manufacture of display substrates using SM-L ED, it would be advantageous if the substrate interface of L ED electrodes could be maximally flat.

Disclosure of Invention

Described herein are micro light emitting diode (L ED) structures between 10 and 150 μm in diameter that are suitable for fluid assembly of large area arrays to produce high resolution red-green-blue (RGB) displays.A fabrication process for micro L ED is compatible with gallium nitride (GaN) based blue/green L ED and aluminum gallium indium phosphide (AlGaInP) based red L ED produced by conventional metal-organic chemical vapor deposition (MOCVD) growth techniques.A resulting micro L ED has an electrode structure that can electrically and physically join array contacts in a display substrate after fluid assembly to form an active or passive matrix display.A disclosed micro L ED structure is capable of varying pixel brightness over a range that meets different display requirements without changing the structure of the micro L ED, thereby affecting yield and reliability of the fluid assembly process.

Thus, a method for fabricating Surface Mount (SM) micro L ED (μ L ED) is provided that provides MOCVD-L ED structures on a growth substrate a stack of layers overlying the growth substrate, the growth substrate including a first doped semiconductor having a top surface in a first plane, a Multiple Quantum Well (MQW) layer overlying the first doped semiconductor having a top surface in a second plane, and a second doped semiconductor overlying the MQW layer and having a top surface in a third plane, wherein the first and second doped semiconductors are oppositely doped with n and p dopants, see fig. 1A and 2 a. in the case of gallium nitride micro L ED, the first and second doped semiconductors are doped gan.

The method etches a MOCVD stack to form a plurality of individual chips on a growth substrate.A μ L ED. electrical insulator is conformally deposited from each chip by first selectively etching the stack to form a top surface in a fourth plane overlying the etched stack, and then selectively etched to expose a second doped semiconductor to create a first via.A selective etch is also performed to expose the first doped semiconductor to form a second via.A first electrode is formed overlying and connected to the second doped semiconductor by the first via and has a substrate interface surface in a fifth plane.A second electrode is formed overlying and connected to the second via and connected to the first doped semiconductor by the second via and has a substrate interface surface in a fifth plane.

More specifically, the method can produce SM central emission μ L ED. by selectively etching the stack to form a central mesa stack surrounded by trenches exposing the first doped semiconductor and a perimeter stack divided by perimeter trench valleys exposing the first doped semiconductor, the depositing an electrical insulator conformally on the etched stack including forming a fourth plane overlying the central mesa stack and the perimeter stack.

The step of selectively etching to expose the second doped semiconductor includes etching a portion of the electrical insulator overlying the perimeter stack to expose the second doped semiconductor, and the step of selectively etching to expose the first doped semiconductor includes etching a portion of the electrical insulator and an underlying portion of the second doped semiconductor and the MQW layer in the center mesa stack to expose the first doped semiconductor.

The step of selectively etching to expose the second doped semiconductor by selectively etching the stack to form a mesa stack and a peripheral trench valley in the mesa stack and exposing the first doped semiconductor includes etching an electrically insulating layer overlying a portion of the mesa stack to expose the second doped semiconductor.

A first thin film layer overlies the top surface of the support substrate and includes a plurality of wells, each well having a convex bottom surface, a first substrate electrode connected to a corresponding column line and a second substrate electrode connected to a corresponding row line.

Additional details of the above method will be provided below, as well as center, perimeter, full area light emitting SM micro L ED devices and light emitting substrates with convex well bottom surfaces.

Drawings

Fig. 1A to 1C are diagrams depicting GaN-L ED wafers (prior art) for general illumination purposes.

Fig. 2A and 2B are diagrams illustrating gallium arsenide (GaAs) L ED wafers (prior art) for manufacturing red light emitting indicators.

Fig. 3A and 3B depict partial cross-sectional views of blue and red L ED (prior art) respectively of a conventional package.

Fig. 4A and 4B are a partial sectional view and a plan view, respectively, of a light emitting element that can be used as a Surface Mount (SM) L ED.

Fig. 5 is a partial cross-sectional view depicting an alternative to L ED of fig. 4.

Fig. 6A-6J depict the steps of fabricating a micro L ED as described in U.S. patent 9,825,202.

Fig. 7A-7C depict the suspension medium applying torque to a micro L ED having a navigation keel (post).

Fig. 8A and 8B are a plan view and a partial cross-sectional view, respectively, of a micro L ED subpixel layout.

Fig. 9A through 9E are partial cross-sectional views depicting alignment of micro L EDs in an exemplary well variation.

Fig. 10A-10C are partial cross-sectional views of a substrate well and a mating micro L ED showing a well bottom surface pad.

Fig. 11A to 11D are a plan view, two partial sectional views and a perspective view, respectively, of the planar SM center emission μ L ED.

Fig. 12 is a graph showing the relationship between flux and efficiency as a function of current density.

Fig. 13A and 13B are a plan view and a partial sectional view depicting the planar SM peripheral light emission μ L ED, respectively.

Fig. 14A and 14B are a plan view and a partial sectional view, respectively, of the planar SM full-area light emission μ L ED.

Fig. 15A to 15C are plan views comparing light emitting surface areas of micro L EDs of center light emission (fig. 11A), peripheral light emission (fig. 13A), and full-area light emission (fig. 14A).

Fig. 16 is a flow chart illustrating a method for manufacturing SM μ L ED.

Fig. 17 is a flow chart illustrating a method for manufacturing a display substrate having a well bottom surface pad.

Description of the main elements

SM-LED 300

First electrical contact 306

Second electrical contact 308

Second semiconductor layer 402

First semiconductor layer 404

MQW layers 406, 1106, 1306

Electrical insulators

408, 1314

Row line 802

Column line 804

Light emitting display substrate 1000

Support substrate 1001

Support substrate top surface 1002

First thin film layer 1008

Trap 1010

Convex bottom surface 1012

First substrate electrode 1014

Second substrate electrode 1016

Second thin film layer 1018

TFT layer 1018a

First oxide layer 1018b

Second oxide layer 1018c

Shim 1020

Diameter 1022

Width 1024

Top surface 1026

First electrical interface surface 1028

Second electrical interface surface 1030

Via 1032

Central luminescence mu L ED1100

First doped

semiconductor

1102, 1302, 1402

Central platforms

1102a, 1302a

Perimeters 1102b, 1302b

Second doped

semiconductor

1110, 1310, 1410

Electrically-insulator

first portions

1114a, 1414a

Electrically-insulator

second portions

1114b, 1414b

Peripheral groove valleys

1118, 1418

First electrodes

1120, 1318, 1420

Center vias

1124, 1320

Second electrode

first portions

1126a, 1424a

Second electrode

second portions

1126b, 1424b

Peripheral vias

1128, 1326, 1426

Trenches

1130, 1328

Etch stack height

1134, 1332, 1430

First plane

1104, 1304, 1404

Second plane

1108, 1308, 1408

Third planes

1112, 1312, 1412

Fourth plane

1116, 1316, 1416

Fifth plane

1122, 1322, 1422

Sixth plane

1132, 1330, 1428

Navigation keel or

post

1136, 1432

Miniature L ED1300, 1400

Second electrode 1324

First doped semiconductor

substrate bottom surface

1336, 1434

Landing via 1423

The present invention will be further described with reference to the accompanying drawings.

Detailed Description

The general method of fabricating micro light emitting diode (μ L ED) displays using inorganic L ED and fluid assembly over the display backplane is disclosed in the prior family patent application (U.S. patent No. 9,825,202, application No. 15/412,73), which is incorporated herein by reference, in particular, the process flow for fabricating a suitable display backplane is described in the description of fig. 17 in U.S. patent 9,825,202. the geometric requirements for fluid assembly are set forth in the description of fig. 16.

U.S. patent No. 9,825,202 describes two types of gallium nitride (GaN) micro L ED. a structure having a light emitting region at the center of the device is shown in fig. 4A and 4B, and a structure having a light emitter in an outer ring is shown in fig. 5, as described below.

Fig. 4A and 4B are a partial cross-sectional view and a plan view, respectively, of a light emitting element that can be used as a surface mount device (SM) L ED SM-L ED300 includes a first semiconductor layer 404 with n-type dopants or p-type dopants, a second semiconductor layer 402 using dopant types not used in the first semiconductor layer 404, Multiple Quantum Well (MQW) layers 406 interposed between the first semiconductor layer 404 and the second semiconductor layer 402, the MQW layers 406 may typically be a series of quantum well layers not shown (typically 5 layers, e.g., alternating 5nm indium gallium nitride (InGaN) with 9nm n-doped GaN (n-GaN)), there may also be an aluminum gallium nitride (AlGaN) electron blocking layer (not shown) between the MQW layers and the p-doped semiconductor layer, the outer semiconductor layer may be about 200nm thick p-doped GaN (Mg-doped), if higher indium content is used in the MQW layers, the most practical first and second semiconductor layers of blue L ED or green L ED. materials may be formed as high brightness aluminum gallium phosphide or green light emitting materials (light emitting materials or blue light emitting semiconductor materials (algalga-doped inp).

The second electrical contact 308 is configured in a ring shape, and the first semiconductor layer 404 has a disk shape with a periphery below the ring of second electrical contacts. The first electrical contact 306 is formed within the perimeter of the second electrical contact 308, and the second semiconductor layer 402 and the MQW layer 406 are a stack located below the first electrical contact. A trench may be formed between the ring of second electrical contacts 308 and the first electrical contacts 306 and filled with an electrical insulator 408.

Conventional L ED processes (e.g., L ED for illumination) occur on one surface only before separation from the sapphire substrate, some of which use laser lift-off (L L1O) to separate L ED from the sapphire substrate as the last step other processes do not use L O, but cut the sapphire substrate to singulate the L ED.

FIG. 5 is a partial cross-sectional view depicting an alternative to L ED of FIG. 4A. in this aspect, the first electrical contact (electrode) 306 is configured as a ring, and the second semiconductor layer 402 and the MQW layer 406 are annular stacks below the first electrical contact.A second electrical contact 308 is formed within the circumference of the first electrical contact 306. the first semiconductor layer 404 has a disk shape with a center portion below the second electrical contact.A trench is formed between the ring of the first electrical contact 306 and the second electrical contact 308. an electrical insulator 408 fills the trench, as shown.

Fig. 6A-6J depict the steps of fabricating micro L ED's as described in U.S. patent 9,825,202 for consistency of description, the top and bottom surfaces of the micro L ED's are defined relative to the growth substrate, which is the last layer to grow in a MOCVD process, with electrodes, the bottom surface having optional pillars.

1) Other substrates may be used, such as silicon carbide (SiC) or silicon, but sapphire substrates allow for the dissolution of GaN at the bottom device surface adjacent the sapphire substrate by removing μ L ED from the growth substrate by laser lift-off (LL O), as described above, L ED stacks are deposited on a sapphire wafer by MOCVD, the MQW structure is tuned to produce the desired emission color, and the thickness of the resulting structure is between 2 and 7 μm, see also FIG. 1A for an example of the various layers.

2) A current spreading layer is deposited on the p-GaN surface. The composition being generally thin NiO_xThe interfacial layer plus a transparent conductive oxide, such as Indium Tin Oxide (ITO), may be 100 to 500 nanometers (nm) in thickness.

3) The light emitting region is defined by photolithography and the MOCVD stack is etched to a depth extending into the n-doped GaN layer. Depending on the MOCVD structure, the etch depth (Z)_MESA) And may be 300nm to 2 micrometers (μm). Typically less than 1 micron.

4) The μ L ED regions are defined by photolithography and then the entire stack is etched down to the sapphire substrate typically, the pattern is an array of closely packed micro L EDs to maximize the yield of micro L EDs on a MOCVD wafer the size of the micro L EDs is selected to match the width of the trapping sites on the display substrate and is typically in the range of 15 to 150 μm in diameter.

5) An insulating layer, which may be SU8 or photo-patternable polyimide, is deposited and patterned to prevent current leakage between the N-pad and P-pad.

6) A lithographic pattern is formed to prevent metal deposition outside the N-pad area and a metal layer is deposited to establish the electrodes to match the height of the P-pad. The first layer is chosen to match the work function of n-doped GaN and can be 10 to 50nm thick Ti or Cr. The stacking is accomplished by depositing gold of appropriate thickness to match the height of the active region mesa.

7) The metal and photoresist are removed by lift-off, leaving a build-up on the n-GaN contact area.

8) Photolithography is performed to prevent deposition outside the N-pad and P-pad contact areas, and a metal stack is deposited to connect the μ L ED contact holes.

a. The first metal is chosen as a conductive layer between the stack and the solder material and may be chromium/gold (Cr/Au) or titanium/nickel (Ti/Ni) with a total thickness of 100-200 nm.

b. The top layer is a low melting point solder that can be bonded to the substrate electrodes. One system is tin (Sn) alloys such as tin-indium (Sn-In), tin-indium-silver (Sn-In-Ag), and tin-silver-antimony (Sn-Ag-Sb), where the solder metal is chosen to be similar to conventional low melting solder materials. Another metal solder system is gold/germanium (Au/Ge).

9) Excess metal is removed by a lift-off process.

10) The finished wafer dome sides were adhered to a temporary carrier with an adhesive layer and the sapphire growth wafer was removed by LL O (laser lift off).

11) For clarity, the convention of identifying the top and bottom surfaces of micro L ED's based on the original growth orientation is maintained.

12) Optionally, the n-GaN may be etched to reduce the thickness of the micro L EDs.

13) The post may be cylindrical, conical, or concave in shape, with the height and diameter of the post selected to facilitate an orientation with the bottom side of the μ L ED facing upward during fluid assembly, as explained in more detail below.

14) Finally, the intact μ L ED was collected into suspension by dissolving the binder using a suitable solvent.

The micro L EDs that result from the manufacturing process all have critical dimensions, such as diameter, thickness, and pillar height, as well as the size and arrangement of the electrodes configured to match the geometry of the wells and electrodes on the display substrate, so the micro L EDs can be assembled and bonded together with the P-pad and N-pad electrodes that connect the row and column interfaces of the display substrate, respectively, as shown in fig. 8A and 8B, each sub-pixel has two electrodes on the substrate centered on a trap structure with vertical walls (also called wells). the disk-shaped micro L EDs and matching circular wells and electrodes are shown simply, but other shapes such as squares or triangles can be used, provided that the shapes are designed to match complementary shapes in the substrate so that both micro L ED electrodes electrically connect the correct substrate electrodes without shorting.

Fluid assembly of micro L EDs is performed by dispensing micro L EDs in a liquid suspension over a display substrate some examples of suspension components include water, alcohols, ketones, alkanes, and organic acids fluid can be disturbed in some way, such as brushes or blades, or solvent or gas flow, creating a liquid flow over the entire substrate as the micro L EDs move over the substrate many capture attempts can be made as the micro L EDs are captured and fixed in the substrate well structure to create a self-assembled array of micro L EDs precisely positioned their surface mount electrodes in contact with the electrical interface (substrate electrodes) in the substrate well.

It is well known that fluid velocity increases parabolically from zero on a closed surface, so the force on the micro L EDs increases with increasing distance from the top surface of the substrate, when the suspension is first distributed on the substrate, the micro L ED can be dispensed relatively quickly before settling onto the substrate surface, upon reaching the substrate, the micro L ED continues to move under the influence of fluid flow, thus, as shown in fig. 1, the device with the post down as shown in fig. 7A experiences a torque tending to reverse direction, with the electrode down, the post up, similarly, if the micro L ED enters the well with the post down (fig. 7B), the post will prevent the disc from being trapped, and the force on the disc tends to push the micro 2ED out of the well and reverse direction to force the electrode down, if the micro L is trapped in the well, as shown in fig. 7C, the fluid flow will create little force due to the small cross section of the post, so the potential for fluid to escape from the well as to stabilize the fluid configuration with the micro L.

In a typical flat panel display manufacturing, the row and column interconnect lines are aluminum or copper thin films of between 200 and 1500nm in thickness a given micro L ED emits an amount of light that is controlled by the amount of current provided by an external driver chip and the resistance of a TFT control circuit (not shown) that is part of the sub-pixel a key point for manufacturing the micro L is that the two electrodes on the SM micro L ED must be combined with low resistance substrate electrodes to allow the correct amount of current to flow through the micro L ED. substrate electrodes are selected for low resistance and compatibility with the solder layer on the micro 367 ED in one case the substrate electrodes are 200 to 1000nm thick copper to form a copper-tin intermetallic compound with the tin-based layer, the opposite is arranged with the micro 3645 ED electrodes and with a diameter of the micro fluid trap L that can be seen successfully on the micro 368 ED, thus the micro fluid trap may be assembled with the micro ED 358, which is smaller than the diameter of the solder well.

Fig. 9A-9E are partial cross-sectional views depicting alignment of micro L ED in an exemplary well (well) variation fig. 9A depicts a well diameter slightly larger than the micro L ED diameter, which facilitates alignment and bonding, fig. 9B prevents electrical contact between the micro L ED and the substrate due to the unfavorable alignment and bonding caused by the well being too small, fig. 9C, the well diameter is too large to allow L ED electrodes to cause shorting between row and column substrate electrodes.

All of these dimensions are a result of the control of dimensions through reticle design, film thickness and photoresist exposure using relatively conventional photolithography processes. The deposition thickness for the build-up is selected to match the depth of the mesa etch (see fig. 6B), which defines the central active (light emitting) region, so the target thickness must be determined by measuring the etch depth. The GaN etch is performed in a single wafer etch chamber, so the etch rate may differ by 10-20% between successive wafers. In addition, the etch rate is not completely uniform across the wafer, with as much as 10-15% variation from center to edge. As a result, for an etch nominally targeted at 1 micron, the center mesa (Z)_MESA) May be as high as 400 nm. Deposition of the deposited metal is usually accomplished by evaporation or sputtering, usually by processing many wafers together in a batch process, so that the individual deposition thickness for each wafer isIs not feasible. For this case, the target thickness of the build-up deposition is chosen to be Z for all wafers, regardless of the above-described etch differences_MESAThe final structure N-pad (electrode connecting N + semiconductor) and P-pad (electrode connecting P + semiconductor) may not be on the same plane due to variations in GaN etching and deposition of build-up metal, this difference may vary from one micro L ED to another micro L ED, and may be as much as 600nm, which may have a significant negative impact on the yield and reliability of the electrical connection between the micro L ED and the substrate contact.

In FIG. 9D, the N-pad of the peripheral micro L ED is too thick, so the center electrode (P-pad) of the micro L ED does not make electrical contact with the substrate, because the heights of the N-pad and P-pad are not coplanar, the result is a darkening of the pixel due to improper control of electrode planarity. conversely, in FIG. 9E, the N-pad on the periphery is too "low" relative to the center electrode, resulting in incomplete contact of the electrode with the electrical interface of the matching substrate. the tilted micro L ED results in the contact between the N-pad and the substrate electrode being confined to a small area, rather than the entire periphery.

10A-10C are partial cross-sectional views of substrate wells and mating micro L ED showing well bottom surface pads, a light emitting display substrate 1000 includes a support substrate 1001 with a flat top surface 1002 and a L ED cross-point control matrix including an array of column and row conductors, since only one L ED is shown, there is only one pair of column and row lines, shown at 804 and 802, respectively, in FIG. 8A. the active and passive matrix systems are specifically explained in the prior family application, U.S. Pat. No. 9,825,202, which is incorporated herein by reference, as described in the background section above, a light emitting display substrate typically includes millions L ED. of first thin film layers 1008 overlying the support substrate top surface 1002. again, only a single well 1010 is shown 1012. each well 1010 has a convex bottom surface denoted by reference numeral with a first substrate electrode 1014 connecting the corresponding column line (804, see FIG. 8A) and a second substrate electrode 1016 connecting the corresponding row line (802, FIG. 8A).

A second thin film layer 1018 is interposed between the support substrate top surface 1002 and the first thin film layer 1008, as shown in FIGS. 10B and 10C, the second thin film layer 1018 may be comprised of a TFT layer 1018a containing Thin Film Transistors (TFTs), not shown, and interconnected to a row and column of conductive lines for L ED to be operational, the second thin film layer 1018 may also be comprised of some oxide or insulating layer, exemplified by a first oxide layer 1018B and a second oxide layer 1018℃ spacers 1020 are interposed between the support substrate top surface 1002 and the second thin film layer 1018 below the bottom of each well, spacers 1020 may be an insulating material, as shown in FIG. 10A, or an electrical conductor, as shown in FIGS. 10B and 10℃ first thin film layer wells 1010 each have a diameter 1022 or cross section (in the case of a non-circular L ED.) spacers 1020 have a width 1024 smaller than the diameter 1022 and a top surface 1026.

As shown in all examples, the first substrate electrode 1014 is a center substrate electrode having a first electrical interface surface 1028 for electrically connecting the micro L ED and the second substrate electrode 1016 is a peripheral substrate electrode having a second electrical interface surface 1030, lower than the first electrical interface surface, defined relative to the support substrate top surface 1002, and also for electrically connecting the micro L ED. as shown explicitly in fig. 10B and 10C, the pads are formed directly on the column lines, forming column interconnect pads 1020. the first substrate electrode 1014 is a center substrate electrode covering the vias 1032 and connecting the column interconnect pads 1020.

As shown, additional spacer structures may be added to the substrate below the center substrate electrode to raise it above the outer ring substrate electrode by the thickness of the spacer layerThe continuous metal film is made of, for example, aluminum or copper, or an insulating layer, and may have a thickness of 50 to 500 nm. If the spacer is conductive, it is isolated from the center substrate electrode by an interlayer dielectric as shown. Alternatively, the center and edge substrate electrodes may be fabricated separately with layers having different thicknesses. The result is that the center and edge electrodes are no longer coplanar and the height difference is D_sub＝Z_C-Z_E(FIG. 10A). It can be seen that when the electrode height D is_LED＝Z_P-Z_NIs equal to D_SUBThe substrate electrode structure is best matched to the micro L ED, so this structure can be at D_LED<D_SUBIn any case compensate for the "low" P-pad (center) electrode, but at the cost of increased complexity and variability. Of course, for an electrode having a "high" P-pad (D)_LED>0) With the micro L ED, the structure will have lower performance and result in a reduced contact area, as shown in fig. 9E.

In the case of an active matrix display (e.g., fig. 10B), micro L ED wires are constructed on the layers used to fabricate the TFTs (not shown). the micro L ED wires consist of metal interconnect lines arranged in rows and columns, which connect the substrate interface electrodes. low resistance row and column interconnect lines are typically copper or aluminum, and the thickness of the lines is 100 to 900 nm. thus, electrode connections can pass through each other without shorting because the metal layers are separated by insulating layers (typically silicon oxide). in fig. 10B, a first oxide layer 1018B separates the column and row interconnect lines (804 and 802, see fig. 8A), while a second oxide layer 1018C separates the column interconnects from the first substrate electrodes, and the connections between the layers are made through appropriately placed vias. in fig. 10B, the spacers located below the center substrate electrodes are made of the same metal film as used to fabricate the columns, thus the center substrate electrodes are made thicker by the same thickness of the center substrate layer C, where the center substrate layer is raised by the thickness of the center electrode layer C.

Using the above-described spacer, a micro L ED with a "tall" peripheral electrode, as shown in fig. 9D, can be successfully matched to the convex well-bottom structure shown in fig. 10A, 10B, and 10C, however, even though the center and peripheral electrodes of the micro L ED are planar, as shown in fig. 9A, or the micro L ED center electrode is "taller" than the peripheral electrode, as shown in fig. 9E, the micro L ED electrode will be able to connect to the substrate electrode, but at the expense of higher current resistance and reduced contact area.

A simpler and more efficient method to fabricate micro-led electrodes with equal (co-planar) substrate interface surfaces is disclosed in more detail herein. To avoid tolerance issues associated with etching portions of the MOCVD stack first and then depositing and patterning thin films, the inherently co-planar MOCVD stack is advantageously used as a mechanical assembly to lift the N-pad electrode to the same height as the P-pad, ensuring D_LEDUnlike the above-described physical deposition processes, which typically result in topological changes due to grain growth, heteroepitaxy successfully results in a surface that is locally (less than or equal to the diameter of the micro L ED) planar (planar) within at most a few atomic layers, similarly, an insulating layer, typically silicon dioxide deposited by plasma enhanced chemical vapor deposition, is smooth and locally (as defined above) planar, thus, the fourth plane of the substrate used as a surface mount electrode has substantially lower variability, typically less than 10 nanometersAverage fifth plane tolerance of nm. D due to fabrication of miniature L ED_LEDIs always zero, so the shim structure of fig. 10 has no advantage, and with reference to fig. 10, D may be used_SUBThe display substrate was manufactured at 0.

11A-11D are a plan view, two partial cross-sectional views, and a perspective view, respectively, of a planar SM central emission μ L ED central emission μ L ED1100 includes a first doped semiconductor 1102 formed as a substrate and doped with an n or p dopant, As shown in FIGS. 11A and 11C, the first doped semiconductor 1102 substrate has a perimeter that is circular in this example, but is not limited to any particular shape, the first doped semiconductor 1102 has a top surface formed in a first plane 1104, the first plane 1104 includes a central platform 1102a (distinguished by dashed lines) that is separate from the perimeter 1102b (distinguished by separate dashed lines), an MQW layer 1106 (typically formed as several sub-layers) has a top surface formed in a second plane 1108 that overlies the first doped semiconductor central platform 1102a and the perimeter 1102 b. A second doped semiconductor 1110 doped with a dopant opposite to the dopant used in the first doped semiconductor is formed as a layer having a top surface 1112 in a third plane 1106 above the MQW layer 1106.

The electrical insulator has a first portion 1114a formed as a layer having a top surface in the fourth surface 1116 of the second doped semiconductor 1110 and a second portion 1114b covering the perimeter trench valleys 1118 dividing the perimeter 1102 b. The key function of the insulator is to prevent current leakage between the first and second doped semiconductors. The first electrode 1120 overlies the central platform, connects to the second doped semiconductor 1110 through the central via 1124, and has a substrate interface surface in the fifth plane 1122. The second electrode has a first portion 1126a formed over the perimeter trench valley 1118 and connects the first doped semiconductor 1102 through a perimeter via 1128. The second electrode has a second portion 1126b that overlies the perimeter of the electrically-insulator first portion 1114a and connects to the second electrode first portion and has a substrate interface surface in a fifth plane 1122.

The SM center emission μ L ED1100 also includes a trench 1130 formed in the first doped semiconductor 1102 that separates the center mesa 1102a from the perimeter 1102b the trench 1130 and the perimeter trench valleys 1118 have top surfaces formed in a sixth plane 1132 that lies below the first plane 1104.

In one aspect, the first doped semiconductor 1102 and the second doped semiconductor 1110 are doped GaN. Alternatively, the first doped semiconductor 1102 and the second doped semiconductor 1110 are p-doped gallium phosphide (p-GaP) or n-doped indium gallium phosphide (n-GaInP). Technically, the doped semiconductors may also be n-GaP and p-GaInP, but are less practical.

Although not explicitly shown, as is well known in the art, a GaN device may optionally include electron and hole injection and blocking layers, in the case of GaAs devices, optional p and n cladding layers may be used, which are also well known in the art, it is generally desirable to maximize the residence time of electrons and holes in the MQW layer for both red and blue micro L EDs.

The first doped semiconductor 1102, the MQW layer 1106, and the second doped semiconductor 1110 form an etch stack having a height 1134 orthogonal to the first 1104, second 1108, and third 1112 planes of less than 2 microns and flatness tolerances of the first, second, third, and fourth planes of less than 10 nanometers, as described above, the electrode interface surface in the fifth plane has an average flatness tolerance of less than 10nm, rather than relying on the use of thin film build-up processes to form the larger tolerances inherent in planar electrode surfaces, as shown in fig. 6A-6J, the apparatus described herein uses a pre-existing flat surface of the MOCVD stack.

In one aspect, not shown, the solder layer forms part of the first and second electrode interface surfaces and is made of an alloy such as indium/tin (In/Sn) or gold/germanium (Au/Ge). Alternatively, the substrate interface surfaces of the first and second electrodes are gold. Optionally, as shown, a navigation keel or post 1136 is attached to first doped semiconductor base bottom surface 1138.

As shown in FIG. 11A, this exemplary center emitter design uses four equally spaced island-like structural support segments of annular N-pad electrodes one key factor in the design is that the N-pad and P-pad electrodes are coplanar, also note that the island (perimeter) structure is not electrically active and is separated from the N-pad electrodes by an insulator, so the connection to the N-pad electrodes is made through 4 contact points spaced between the islands the number of islands generally depends on the size of the micro L ED, from one to six or more, but at least one opening is provided in the island structure for contact with the N-doped region.

The process flow of the present invention is similar to the prior art flow set forth above, with the removal of the photo, deposition and lift-off steps associated with N-pad build-up (steps 6 and 7 above), thus reducing cost and complexity in producing micro L EDs with perfectly coplanar surface mount electrodes.

1) Other substrates, such as SiC or silicon, may be used, but the sapphire substrate allows the μ L ED. mqw structure to be tuned to produce the desired emission color by laser lift-off (LL O) from the growth substrate with the thickness of the resulting structure between 2 and 7 μm, see also fig. 1A.

2) A current spreading layer is deposited on the p-GaN surface. The composition is typically a thin (10nm or less) NiO_xThe interfacial layer plus a transparent conductive oxide, such as ITO, which may be 100 to 500nm thick.

3) The light emitting region is defined by photolithography and the MOCVD stack is etched to a depth that extends into the n-doped GaN layer, forming a structure referred to herein as an "etch stack".

4) The μ L ED area was defined by photolithography and etching the entire stack down to the sapphire substrate.

5) An insulating layer, typically of Plasma Enhanced CVD (PECVD) silicon dioxide (SiO) with a thickness of 100 to 400nm₂) Deposited to prevent current leakage across the device.

6) Contacts corresponding to the p-GaN and n-GaN regions are opened in the insulating layer.

7) Photolithographic patterns are formed to prevent metal deposition outside the N-pad and P-pad contact areas, and a metal stack is deposited to connect the μ L ED contact holes.

a. The first metal layer is selected to adhere to the oxide and the work function is matched to n-doped GaN. A typical material is Cr 10 to 50nm thick.

b. The next metal is chosen as a conductive barrier between the adhesion layer and the solder material and can be Cr/Au or Ti/Ni with a total thickness of 100-200 nm.

c. The top layer is a low melting point solder that can bond the substrate electrodes. One system is a tin alloy for solder melting temperatures. Another metal system is Au/Ge.

d. Alternatively, the micro L ED may receive only the metal from steps 7a and 7b, and a low melting solder may be formed on the display substrate electrodes.

8) The excess metal is removed by a lift-off process.

9) The top side of the finished wafer was bonded to a temporary carrier by an adhesive layer and the sapphire growth wafer was removed by LL O.

10) Now, μ L ED is bottom side up on the carrier wafer in a planar array suitable for further processing.

11) Alternatively, the n-GaN may be etched to reduce the thickness of the μ L ED.

12) The post may be cylindrical, conical, or concave in shape, with the height and diameter of the post selected to facilitate orientation of the bottom side of the μ L ED upward during fluid assembly.

13) Finally, the intact μ L ED was collected into suspension by dissolving the binder using a suitable solvent.

The process flow is modified for GaAs-based devices since the red L ED was fabricated in a different MOCVD process.

1) The MQW structure is tuned to produce the desired emission color, and the thickness of the resulting structure is between 5 and 10 μm, see also fig. 2A.

2) Alternatively, the p-GaP may be etched to reduce the thickness of the stack.

3) The top surface of the completed wafer is bonded to a glass or sapphire temporary substrate via an adhesive layer, and the GaAs growth wafer is removed by wet etching.

4) The μ L ED region was defined by photolithography and the entire stack was etched.

5) The light emitting region is defined by photolithography and the MOCVD stack is etched to a depth that extends into the p-doped GaP layer, forming an etch stack.

6) A metal layer such as Cr/Au is deposited over the p-GaP region matching the workfunction of the layer.

7) A metal layer such as Ti/Au is deposited over the n-GaP region matching the workfunction of the layer.

8) Depositing an insulating layer, typically 100 to 400nm thick of PECVD SiO₂Is deposited to prevent current leakage across the device.

9) Contacts corresponding to the p-GaP and n-GaP regions are opened in the insulating layer.

10) Photolithographic patterns are formed to prevent metal deposition outside the N-pad and P-pad contact areas, and a metal stack is deposited to connect the μ L ED contact holes.

a. The first metal is chosen as a conductive barrier between the adhesion layer and the solder material, which may be Cr/Au or Ti/Ni with a total thickness of 100-200 nm.

b. The top layer is a low melting point solder that can bond to the substrate electrodes. One system is a tin alloy used to lower the melting temperature of solder. Another suitable low melting point metal system is Au/Ge. Alternatively, the solder layer may be formed on the substrate electrode.

11) Excess metal is removed by a lift-off process.

12) The finished top wafer surface is bonded to a temporary wafer with an adhesive layer and the first temporary substrate is removed by dissolving the first adhesive.

13) Now, μ L EDs are bottom side up on the temporary wafer in a planar array suitable for further processing.

14) Alternatively, the n-GaP may be etched to reduce the thickness of the micro L EDs.

15) The posts may be cylindrical, conical, or concave in shape, with the height and diameter of the posts selected to facilitate the orientation of the bottoms of the micro-scale L ED facing upward during fluid assembly.

16) The finished mini L ED were collected in suspension by dissolving the second binder using a suitable solvent.

One of the most important advantages of miniature L ED displays is that inorganic L ED can achieve very high brightness, which enables flexibility to match the light emission performance of the display to the specific resolution and brightness requirements of the product.A miniature wearable display may only require 150 plus 200 nit (candela per square meter) brightness, while television may be 500 plus 1500 nit, while an outdoor Public Information Display (PID) may be 2000 plus 4000 nit.the resolution of a small display of a cell phone or tablet may exceed 600 pixels per inch (ppi), while a large PID display may only have a resolution of 20 to 60ppi, so the available area of each miniature L ED is also very different.for a 440nm (blue) emitting GaN miniature L ED, as shown in FIG. 12, the luminous flux from a miniature L ED is an approximately linear function of current density over a relatively wide range.A miniature L ED adjusts the intensity of the image by controlling the current provided to each sub-pixel.

The electro-optic conversion efficiency (light output/electrical power) of micro L ED peaks at relatively low flux and then gradually decreases (drops) over a wide range of applied current for display operation, it is desirable to operate near the peak efficiency to minimize waste heat dissipated in the display, however, very low currents are difficult to regulate, and thus the optimal current density for a given display depends on a variety of factors²It would therefore be advantageous to have a structure that allows adjustment of the micro L ED light emitting area to balance performance requirements while maintaining fixed micro L ED characteristics, such as pillar height, thickness and diameter, which are critical for high throughput fluid assembly.

Fig. 13A and 13B are a plan view and a partial cross-sectional view, respectively, depicting a planar SM peripheral emission μ L ED, a peripheral emission μ L ED1300 includes a first doped semiconductor 1302 formed as a base and doped with an n or p dopant, the first doped semiconductor 1302 has a top surface formed in a first plane 1304 that includes a central mesa 1302a spaced from a peripheral edge 1302B, as shown in fig. 13A, the first doped semiconductor base is circular, but other well-known geometries are possible.

The electrical insulator 1314 is formed as a layer having a top surface in a fourth plane 1316 overlying the second doped semiconductor 1310. A first electrode 1318 overlies the central mesa 1302a and is connected to the first doped semiconductor 1302 by a central via 1320. The first electrode 1318 has a substrate interface surface in a fifth plane 1322. A second electrode 1324 covers the perimeter of the electrical insulator 1314 and is connected to the second doped semiconductor 1310 by a perimeter via 1326. The second electrode 1324 has a substrate interface surface in a fifth plane 1322. A trench 1328 is formed in the first doped semiconductor 1302, the trench 1328 separating the central mesa 1302a from the perimeter 1302 b. The trench has a top surface formed in a sixth plane 1330 below the first plane 1302. In one aspect, the first doped semiconductor 1302 and the second doped semiconductor 1310 are doped GaN. Alternatively, the first doped semiconductor 1302 and the second doped semiconductor 1310 are p-doped p-GaP or n-doped n-GaInP. The first doped semiconductor central mesa 1302a, the MQW layer 1306, and the second doped semiconductor 1310 form an etched stack having a height 1332 perpendicular to the first plane 1304, the second plane 1308, and the third plane 1312 of less than 2 microns and a flatness tolerance to the first, second, third, and fourth planes of less than 10 nanometers. The average flatness tolerance of the electrode interface surface in the fifth plane is also less than 10 nm.

In one aspect, not shown, the solder layer forms part of the interface surface of the first and second electrodes and is made of an alloy such as In/Sn or Au/Ge. Alternatively, the substrate interface surface of the first and second electrodes is gold. Optionally, as shown, a navigation keel or post 1336 is attached to the first doped semiconductor base bottom surface 1336.

The center emitter described above and shown in FIGS. 11A and 11C includes a light emitting area of 10% to 15% of the total surface area of the disk-shaped micro-L ED, where the surface area of the micro-L ED is parallel to the first, second and third planes, as shown in FIGS. 13A-13B, the structure can be varied so that the light emitting area is an outer ring structure covered by P-pad and the center island (mesa) is the mechanical support for the N-pad electrode.

Fig. 14A and 14B are a plan view and a partial cross-sectional view, respectively, of a planar SM full-area light emitting μ L ED, a full-area light emitting μ L ED1400 includes a first doped semiconductor 1402 formed as a base and doped with n or p dopants, although the first doped semiconductor base is depicted as circular, it is not limited to any particular geometry.

The first electrode 1420 overlies the mesa and connects to the second doped semiconductor 1410 through a mesa via 1423. The first electrode 1420 has a substrate interface surface in the fifth plane 1422. The second electrode has a first portion 1424a covering the peripheral trench valley 1418. The second electrode has a first portion 1424a covering the peripheral trench valley 1418 and is connected to the first doped semiconductor 1402 through a peripheral via 1426. The second electrode second portion 1424b is formed to cover the perimeter of the electrical insulator first portion 1414a having a substrate interface surface in the fifth plane 1422. The first doped semiconductor perimeter trench valley 1418 has a top surface formed in a sixth plane 1428 that is below the first plane 1408.

In one aspect, the first doped semiconductor 1402 and the second doped semiconductor 1410 are doped GaN or the first doped semiconductor 1402 and the second doped semiconductor 1410 are p-doped p-GaP or n-doped n-GaInP As shown, the SM full area luminescence μ L ED may include a plurality of first doped semiconductor peripheral trench valleys 1418 in that case, a second electrode first portion 1424a is formed on each peripheral trench valley 1418 and connects the first doped semiconductor 1402 through respective peripheral vias 1426. the second electrode second portion 1424b overlies a peripheral portion of the electrical insulator first portion 1414a in the fifth plane 1422 having the substrate interface surface.

The first doped semiconductor 1402, the MQW layer 1406, and the second doped semiconductor 1410 form an etch stack having a height 1430 orthogonal to the first plane 1404, the second plane 1408, and the third plane 1412 of less than 2 microns and having flatness tolerances of the first, second, third, and fourth planes of less than 10 nanometers. The average flatness tolerance of the electrode interface surface in the fifth plane is also less than 10 nm.

In one aspect, not shown, the solder layer forms part of the interface surface of the first and second electrodes and is made of an alloy such as indium/tin (In/Sn) or gold/germanium (Au/Ge). Alternatively, the substrate interface surfaces of the first and second electrodes are gold. Optionally, as shown, a navigation keel or post 1432 is attached to the first doped semiconductor base bottom surface 1434.

Fig. 15A-15C are plan views comparing the light emitting surface area of micro L ED for center emission (fig. 11A), peripheral emission (fig. 13A) and full area emission (fig. 14A) if a large light emitting area is needed, the full emitter design of fig. 14A can be employed the active light emitting region is also the mechanically supporting island of the P-pad electrode, thus making the opening (3 shown) in the active island (mesa) formed to contact the n-GaN region, in this case the light emitting area is about 75% of the micro L ED disk diameter for GaAs based devices, three contact geometry is generally more advantageous than four contact variants because there is only one thin region on any splitting plane, thus making the mechanical strength of the micro L ED higher another advantage of the full light emitting structure is that etch damage to the device periphery has less impact on efficiency, which is especially important for AlGaInP devices where surface recombination due to etch damage can cause a reduction L the luminous efficiency around the micro L, thus limiting the micro ED light emitting efficiency.

Another benefit of the structure is the flexibility to change the light emitting area from 10% to 75% of the micro L ED area without changing the physical properties (diameter, thickness, sidewall angle, and post size) critical to successful fluid assembly.

Although the method is described as a series of numbered steps for clarity, the numbering does not necessarily indicate the order of the steps.

Step 1602 provides a MOCVD L ED structure comprising a growth substrate, a stack overlying the growth substrate comprising a first doped semiconductor having a top surface in a first plane, a MQW layer overlying the first doped semiconductor having a top surface in a second plane, and a second doped semiconductor overlying the MQW layer and having a top surface in a third plane, see fig. 1A and 2 a.

Step 1604 etches the MOCVD stack to form a plurality of individual chips on the growth substrate step 1606 selectively etches the stack from each chip fabrication μ L ED. step 1606a as follows step 1606b conformally deposits an electrical insulator to form a top surface on a fourth plane overlying the etched stack step 1606c selectively etches to expose the second doped semiconductor to form a first via step 1606d selectively etches to expose the first doped semiconductor to form a second via.

Note that in some cases step 1606d may be performed before step 1606c, or step 1606d may be performed concurrently after appropriate lithography and patterning, step 1606 d. step 1606e forms a first electrode overlying the first via, connects the second doped semiconductor through the first via, and has a substrate interface surface in the fifth plane.

In one aspect, the method produces a central emission μ L ED, in which case selectively etching the stack (step 1606a) includes creating a central mesa stack surrounded by trenches exposing the first doped semiconductor, and a peripheral stack separated by peripheral trench valleys exposing the first doped semiconductor.

Selectively etching to expose the second doped semiconductor in step 1606c includes etching a portion of the electrical insulator overlying the central mesa stack to create a first via, and selectively etching to expose the first doped semiconductor in step 1606d includes etching the electrical insulator overlying the peripheral trench valley to create a second via. Then, forming the first electrode in step 1606e includes forming the first electrode overlying the central mesa stack and connecting the second doped semiconductor through the first via. Forming the second electrode in step 1606f includes: forming a second electrode having a first portion formed on the peripheral trench valley, the first portion connected to the first doped semiconductor through a second via, and forming a second portion overlying the electrical insulator formed on the peripheral stack, having a substrate interface surface in a fifth plane.

In another aspect, the method includes conformally depositing an electrical insulator in step 1606b by selectively etching the MOCVD stack (step 1606a) to produce a central mesa stack separated from the peripheral stack by trenches exposing the first doped semiconductor, wherein forming the peripheral emission μ L ED. includes forming a fourth plane overlying the central mesa stack and the peripheral stack, wherein selectively etching to expose the second doped semiconductor in step 1606c includes etching a portion of the electrical insulator overlying the peripheral stack to expose the second doped semiconductor, wherein selectively etching to expose the first doped semiconductor in step 1606d includes etching a portion of the electrical insulator and underlying portions of the second doped semiconductor and the MQW layer in the central mesa stack to expose the first doped semiconductor, wherein forming the first electrode in step 1606e includes forming a first electrode overlying the electrical insulator formed on the peripheral stack and connecting the second doped semiconductor through a first via, and wherein forming the second electrode in step 1606f includes forming a second electrode overlying the central mesa stack and connecting the first doped semiconductor through a second via.

In another variation, the method manufactures the full area luminescence μ L ED. by selectively etching the MOCVD stack (step 1606a) to form a mesa stack and a peripheral trench valley in the mesa stack to expose the first doped semiconductor, wherein selectively etching to expose the second doped semiconductor in step 1606c comprises etching a portion of an electrical insulator overlying the mesa stack to expose the second doped semiconductor, wherein selectively etching to expose the first doped semiconductor in step 1606d comprises etching an electrical insulator overlying the peripheral trench valley, wherein forming the first electrode in step 1606e comprises forming a first electrode overlying the mesa stack and connected to the second doped semiconductor by a first via, and wherein forming the second electrode in step 1606f comprises forming a first portion of the second electrode overlying a peripheral trench via connected to the first doped semiconductor by a second via, and forming a second portion overlying the electrical insulator formed at the periphery of the mesa stack and having a substrate interface surface in a fifth plane.

As described above, step 1608 produces a μ L ED having a maximum cross-section of 150 microns coplanar with the first, second, and third planes, a mesa stack (etch stack) height orthogonal to the first, second, and third planes of less than 2 microns, and an average fifth plane flatness tolerance of less than 10 nanometers.

Fig. 17 is a flow chart illustrating a method for manufacturing a display substrate having a well bottom surface pad. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily represent the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of a strict order of sequence. In general, however, the method is as described above, and generally follows the numerical sequence of steps presented below.

The method begins at step 1700, step 1702 provides a support substrate having a planar top surface and an L ED crosspoint control matrix including an array of column and row conductive lines, step 1704 forms an array of raised well floor structures overlying the top surface of the support substrate, step 1706 forms a first thin film layer overlying the top surface of the support substrate and the raised well floor structures, step 1708 forms a well in the first thin film layer and exposes the raised well floor structures, step 1710 fluid deposits surface mount micro L ED in the well.

In one aspect, forming the array of convex well bottom structures in step 1704 includes: for each of the convex well bottom structures, a first substrate electrode electrically connecting the corresponding column line and a second substrate electrode electrically connecting the corresponding row line are formed. On the other hand, prior to forming the first thin film layer, step 1704a forms an array of spacers covering the top surface of the support substrate. The spacers may be of a conductive or insulating material. Step 1704b forms a second thin film layer overlying the array of pads.

In one aspect, forming the array of shims in step 1704a includes forming shims having a width and a top surface. Then, forming wells in the first thin film layer in step 1708 includes forming wells having a diameter (cross-section) greater than the width of the spacers. The convex bottom surface of the well is shaped in response to a height difference between the top surface of the spacer and the top surface of the support substrate.

In another aspect, the formation of the array of raised well-bottom structures in step 1704 includes additional sub-steps.step 1704c forms a central first substrate electrode having a first electrical interface surface for electrically connecting the micro L ED.step 1704d forms a peripheral second substrate electrode having a second electrical interface surface defined below the first electrical interface surface relative to the top surface of the support substrate for electrically connecting the micro L ED.

In yet another aspect, forming the array of pads in step 1704a includes forming each pad directly overlying (in electrical contact with) a column line, forming a column interconnect pad. Then, forming a second membrane layer in step 1704b includes forming vias in the second membrane layer overlying each column interconnect pad, and forming a center first substrate electrode in step 1704c includes forming a center first substrate electrode overlying the vias and electrically connecting the column interconnect pads.

In step 1710, depositing surface mount micro L ED generally includes filling the wells with micro L ED having a top surface and a substrate interface surface, the top surface of the micro L ED having a center first electrode and a perimeter second electrode, the substrate interface surface connecting the first substrate electrode and the second substrate electrode, respectively in one aspect, the micro L ED has a center first electrode and a perimeter second electrode with coplanar substrate interface surfaces, such as the center emitting, perimeter emitting, and full area emitting micro L ED. described in detail above or the micro L ED may have non-coplanar center first electrode and perimeter second electrode substrate interface surfaces, as shown in FIGS. 9D and 9E.

Planar surface mount micro L ED and related manufacturing processes have been shown examples of specific semiconductor materials, geometries, and explicit process steps have been shown to illustrate the present invention.

Claims

1. A light emitting display substrate, comprising:

a support substrate having a planar top surface and a light emitting diode (L ED) cross-point control matrix comprising an array of column and row conductors;

a first thin film layer covering a top surface of the support substrate and including a plurality of wells;

wherein each well has a convex bottom surface, a first substrate electrode connected to a corresponding column wire, and a second substrate electrode connected to a corresponding row wire.

2. The luminescent display substrate of claim 1, wherein: the light emitting display substrate further comprises:

a second membrane layer between the top surface of the support substrate and the first membrane layer;

a spacer located between the top surface of the support substrate and the second membrane layer and below the bottom of each well.

3. The luminescent display substrate of claim 2, wherein: each well of the first thin film layer has a first diameter;

wherein the shim has a width less than the first diameter and a top surface;

wherein the convex bottom surface of the well is due to a height difference between a top surface of the spacer and a top surface of the support substrate.

4. The luminescent display substrate of claim 2, wherein: the gasket is selected from a conductive material and an electrically insulating material.

5. The light-emitting display substrate of claim 2, wherein the first substrate electrode is a central substrate electrode having a first electrical interface surface for electrically connecting micro L EDs and the second substrate electrode is a peripheral substrate electrode having a second electrical interface surface defined with respect to the top surface of the support substrate, the second electrical interface surface being lower than the first electrical interface surface and for electrically connecting micro L EDs.

6. The luminescent display substrate of claim 2, wherein: the spacers directly cover the column conductors to form a column of interconnection spacers;

wherein the second membrane layer includes vias overlying the column interconnect pads; and

wherein the first substrate electrode is a center substrate electrode covering the via and connecting the column interconnection pads.

7. The luminescent display substrate of claim 5, wherein: the light emitting display substrate further comprises:

a plurality of surface mount micro L EDs filling the plurality of wells,

each micro L ED has a top surface with a central first electrode and a peripheral second electrode and a substrate interface surface connecting the first substrate electrode and the second substrate electrode, respectively.

8. The light-emitting display substrate of claim 7, wherein the central first electrode and the peripheral second electrode of the micro L ED have coplanar substrate interface surfaces.

9. The light-emitting display substrate of claim 8, wherein the surface-mounted micro L ED is selected from the group consisting of center-emitting, peripheral-emitting and full-area emitting micro L ED.

10. The light-emitting display substrate according to claim 7, wherein the substrate interface surfaces of the central first electrode and the peripheral second electrode of the micro L ED are not coplanar.

11. A method of making a light emitting display substrate, comprising:

providing a support substrate having a planar top surface and a light emitting diode (L ED) cross-point control matrix comprising an array of column and row conductors;

forming an array of raised well floor structures overlying a top surface of the support substrate;

forming a first thin film layer covering the top surface of the support substrate and the convex well bottom structure; and

a plurality of wells are formed in the first thin film layer so that the convex well bottom structure is exposed.

12. The method of claim 11, wherein: forming the array of convex well bottom structures comprises: for each of the convex well bottom structures, a first substrate electrode electrically connecting the corresponding column conductive line and a second substrate electrode electrically connecting the corresponding row conductive line are formed.

13. The method of claim 12, wherein: forming the array of convex well bottom structures comprises:

forming an array of spacers overlying a top surface of the support substrate prior to forming the first thin film layer; and

a second thin film layer is formed overlying the array of pads.

14. The method of claim 13, wherein: forming the array of shims comprises forming a shim having a width and a top surface;

wherein forming a plurality of wells in the first thin film layer comprises forming a plurality of wells having a diameter greater than the width of the spacer; and

wherein the convex bottom surface of the well is shaped in response to a height difference between the top surface of the spacer and the top surface of the support substrate.

15. The method of claim 13, wherein: forming the array of pads comprises forming the pads from a material selected from electrically conductive and electrically insulating materials.

16. The method of claim 12, wherein: forming the array of convex well bottom structures comprises:

forming a central first substrate electrode having a first electrical interface surface for electrically connecting the micro L EDs, and

a peripheral second substrate electrode is formed having a second electrical interface surface defined relative to the top surface of the support substrate, the second electrical interface surface being lower than the first electrical interface surface and being for electrically connecting the micro L EDs.

17. The method of claim 16, wherein: forming the array of shims comprises:

forming each pad directly overlying the column conductor, forming a column interconnect pad;

wherein forming the second thin-film layer comprises forming vias in the second thin-film layer covering each column interconnect pad; and

wherein forming the center first substrate electrode comprises forming a center first substrate electrode overlying the via and electrically connecting the column interconnect pads.

18. The method of claim 11, further comprising fluid depositing a plurality of surface mount micro L EDs in the plurality of wells.

19. The method of claim 18, wherein depositing the plurality of surface mount micro L EDs comprises filling the plurality of wells with a plurality of micro L EDs, the micro L EDs having a top surface with a central first electrode and a peripheral second electrode and a substrate interface surface connecting the first substrate electrode and the second substrate electrode, respectively.

20. The method of claim 19, wherein depositing the plurality of surface mount micro L EDs comprises depositing micro L EDs having a central first electrode and a peripheral second electrode coplanar with a substrate interface surface.

21. The method of claim 20, wherein depositing the plurality of surface mount micro L EDs comprises depositing micro L EDs selected from center emission, peripheral emission, and full area emission.

22. The method of claim 19, wherein depositing the plurality of surface mount micro L EDs comprises depositing micro L EDs having non-coplanar central first electrode and peripheral second electrode substrate interface surfaces.