CN117199211A

CN117199211A - Light emitting diode and method of manufacturing the same

Info

Publication number: CN117199211A
Application number: CN202210621763.2A
Authority: CN
Inventors: 王彦钦; 陈劲华; 郭桓邵; 彭钰仁
Original assignee: Quanzhou Sanan Semiconductor Technology Co Ltd
Current assignee: Quanzhou Sanan Semiconductor Technology Co Ltd
Priority date: 2022-06-01
Filing date: 2022-06-01
Publication date: 2023-12-08

Abstract

The invention provides a light emitting diode, which at least comprises: a substrate; the epitaxial structure is arranged on part of the upper surface of the substrate and comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially stacked; the first electrode is positioned on the upper surface of the first semiconductor layer and is electrically connected with the first semiconductor layer, and the second electrode is positioned on the upper surface of the second semiconductor layer and is electrically connected with the second semiconductor layer; the insulating layer is formed on the epitaxial structure and at least covers the upper surfaces and the side wall areas of the epitaxial structure, the first electrode and the second electrode, and the upper surface of the insulating layer formed on the upper surface of the first electrode and the upper surface of the insulating layer formed on the upper surface of the second electrode are positioned in the same constant-height plane; the first bonding pad is positioned on part of the upper surface of the insulating layer and is electrically connected with the first electrode, and the second bonding pad is positioned on part of the upper surface of the insulating layer and is electrically connected with the second electrode, wherein the upper surface of the first bonding pad is flush with the upper surface of the second bonding pad.

Description

Light emitting diode and method of manufacturing the same

Technical Field

The present invention relates to the field of semiconductor light emitting devices, and more particularly, to a light emitting diode and a method for manufacturing the same.

Background

With the development of LED (light emitting diode) chips and the technological alternation of related products, mini LED (sub-millimeter light emitting diode) chips and Micro LED (Micro light emitting diode, also called Micro LED) chips are attracting attention based on their advantages in terms of small size, high integration, fast response speed, good thermal stability, low energy consumption, etc., and gradually realize commercial application in existing products.

In the conventional flip-chip light emitting diode, a step structure is provided between a P-type semiconductor region and an N-type semiconductor region, and a height difference exists between a pad of a P electrode and a pad of an N electrode. When the chip is smaller, the distance between the pads corresponding to the P/N electrodes is difficult to control, so that the area of the equal-height area between the pads corresponding to the P/N electrodes is too small, and further the pads of the P/N electrodes are easy to break.

In order to reduce or eliminate the adverse effect caused by the height difference between the pads corresponding to the P/N electrodes, one of the existing flip-chip led structure solutions is: the P/N electrode and the corresponding bonding pad are arranged for a plurality of planes presenting height difference, so that the upper surfaces of the P/N bonding pads are flush. Although the arrangement can solve the height difference between the P/N electrode bonding pads, when the area of the equal-height area between the bonding pads corresponding to the P/N electrodes is smaller, one bonding pad in the P/N electrode is easy to break in the climbing process of the multiple table boards, so that the bonding pads corresponding to the P/N electrodes cannot be conducted, and the normal use of the flip-chip light-emitting diode is affected.

Therefore, in the flip-chip led, how to reduce or eliminate the adverse effect of the height difference between the pads corresponding to the P/N electrodes and ensure the normal optoelectronic performance of the chip has become one of the technical difficulties to be solved by those skilled in the art.

Disclosure of Invention

An embodiment of the invention provides a light emitting diode, which at least includes: the semiconductor device comprises a substrate, an epitaxial structure, a first electrode, a second electrode, an insulating layer, a first bonding pad and a second bonding pad. The epitaxial structure is arranged on part of the upper surface of the substrate and comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially stacked. The first electrode is positioned on the upper surface of the first semiconductor layer and is electrically connected with the first semiconductor layer; the second electrode is positioned on the upper surface of the second semiconductor layer and is electrically connected with the second semiconductor layer. The insulating layer is formed on the epitaxial structure and at least covers the upper surfaces and the side wall areas of the epitaxial structure, the first electrode and the second electrode, and the upper surface of the insulating layer formed on the upper surface of the first electrode and the upper surface of the insulating layer formed on the upper surface of the second electrode are located in the same constant-height plane. The first bonding pad is positioned on part of the upper surface of the insulating layer and is electrically connected with the first electrode; the second bonding pad is positioned on part of the upper surface of the insulating layer and is electrically connected with the second electrode; wherein, the upper surface of the first bonding pad and the upper surface of the second bonding pad are positioned in the same plane.

In some embodiments, the insulating layer is one of a single layer structure, a double layer structure, or a multi-layer structure.

In some embodiments, the insulating layer is made of at least one of flowable silicon dioxide and insulating glue. The insulating adhesive material at least contains carbon and oxygen elements.

In some embodiments, the first pad and the second pad are at least one of Ti, pt, au, ni, sn and alloys thereof. The thickness between the upper surfaces of the first and second pads and the upper surface of the insulating layer, respectively, is 2 μm or more. In a preferred embodiment, the thickness between the upper surfaces of the first and second pads and the upper surface of the insulating layer, respectively, is 2 μm to 4 μm.

In some embodiments, the first electrode and the second electrode are ohmic contact electrodes. The first electrode and the second electrode are at least one of chromium, nickel, aluminum, titanium, platinum, gold, palladium, silver and combinations thereof, and the thickness of the first electrode and the second electrode is 1000 angstroms to 5000 angstroms respectively. In other embodiments, the first electrode and the second electrode are at least one of BeAu, znAu, ni, geAu, au and combinations thereof, and the first electrode and the second electrode each have a thickness of 1000 angstroms to 5000 angstroms.

In some embodiments, the thickness of the insulating layer is 1.2 μm to 2.0 μm to fill and cover exposed surfaces of the substrate, the epitaxial structure, the first electrode and the second electrode.

In some embodiments, the light emitting diode has a core particle size of 300 μm or less. For example: the light emitting diode may be a Mini LED or a Micro LED.

The manufacturing method of the light emitting diode provided by the embodiment of the invention at least comprises the following steps: growing an epitaxial structure, arranging electrodes, manufacturing an insulating layer, manufacturing a connecting through hole and a connecting bonding pad.

Step S11: and growing an epitaxial structure, and sequentially growing a first semiconductor layer, a light-emitting layer and a second semiconductor layer on a substrate to form the epitaxial structure.

Step S12: and setting electrodes, namely forming a first electrode and a second electrode on part of the upper surfaces of the first semiconductor layer and the second semiconductor layer respectively, wherein the first electrode is electrically connected with the first semiconductor layer, and the second electrode is electrically connected with the second semiconductor layer.

Step S13: and manufacturing an insulating layer, and forming the insulating layer on the epitaxial structure in a spin coating mode, wherein the insulating layer at least covers the upper surfaces and the side wall areas of the epitaxial structure, the first electrode and the second electrode.

Step S14: and manufacturing a connecting through hole, and forming a first through hole and a second through hole in the insulating layer region corresponding to the upper parts of the first electrode and the second electrode respectively.

Step S15: and the first bonding pad and the second bonding pad are respectively and electrically connected with the first electrode and the second electrode through the first through hole and the second through hole, and the upper surfaces of the first bonding pad and the second bonding pad are positioned in the same plane.

In some embodiments, in the step of applying an insulating layer, the insulating layer is formed on the epitaxial structure by spin coating using a flowable silicon dioxide or insulating paste.

In some embodiments, in the step of fabricating the connection channel, a fabrication method is one of dry etching, wet etching, or exposure developing.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic cross-sectional view of an embodiment of a light emitting diode according to the present invention;

FIG. 1' is a schematic cross-sectional view of an embodiment of a conventional LED;

FIG. 2 is a flow chart of a method for manufacturing a light emitting diode according to an embodiment of the invention; fig. 3 to 7 are schematic views illustrating a manufacturing method of a light emitting diode according to an embodiment of the invention.

Reference numerals:

1. 1' -light emitting diode 10-substrate 20-epitaxial structure

21-first semiconductor layer 22-light-emitting layer 23-second semiconductor layer

30-first electrode 40-second electrode 50-insulating layer

51-first via 52-second via 60-first pad

70-second bonding pads H1, H2-thickness 24-mesa

h-height difference

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. The technical features which are designed in the different embodiments of the invention described below can be combined with one another as long as they do not conflict with one another.

Referring to fig. 1, fig. 1 is a schematic cross-sectional view of an embodiment of a light emitting diode according to the present invention. To achieve at least one of the advantages and other advantages, an embodiment of the present invention provides a light emitting diode 1, which may at least include a substrate 10, an epitaxial structure 20, a first electrode 30, a second electrode 40, an insulating layer 50, a first pad 60 and a second pad 70, wherein an upper surface of the first pad 60 and an upper surface of the second pad 70 are located in the same plane, and an upper surface of the insulating layer 50 formed on an upper surface of the first electrode 30 and an upper surface of the insulating layer 50 formed on an upper surface of the second electrode 40 are located in the same contour plane. In other words, in this kind of light emitting diode 1, the upper surface of the first pad 60 and the upper surface of the second pad 70 are on the same constant-height surface.

The substrate 10 may be an insulating substrate, and preferably may be made of a transparent material or a translucent material or a non-transparent material. In the illustrated embodiment, the substrate 10 is sapphire (Al ₂ O ₃ ) A substrate. In some embodiments, substrate 10 may be a patterned sapphire substrate, but is not limited thereto. The substrate 10 may also be made of a conductive or semiconductor material. For example, the substrate 10 may be silicon carbide (SiC), silicon (Si), magnesium aluminum oxide (MgAl) ₂ O ₄ ) Magnesium oxide (MgO), lithium aluminum oxide (LiAlO) ₂ ) Aluminum gallium oxide (LiGaO) ₂ ) And at least one of gallium nitride (GaN). In some embodiments, the substrate 10 may be thinned or otherwiseAnd removing to form the thin film type LED chip.

In some embodiments, the upper surface of the substrate 10 may have a patterned structure (not shown) that may improve the external light extraction efficiency and crystallinity of the epitaxial structure 20. Alternatively, the upper surface patterned structure of the substrate 10 may be formed in various shapes, such as a mesa, a cone, a triangular pyramid, a hexagonal pyramid, a conical-like, a triangular-like pyramid, or a hexagonal-like pyramid. In addition, the patterned structure of the upper surface of the substrate 10 may be selectively formed at the respective regions or may be omitted. The patterned structure may be the same material as the substrate 10 or may be different from the substrate 10. For example, the patterned structure may be made of a material having a refractive index lower than that of the substrate 10 to facilitate light extraction, and may be SiO ₂ Etc.

Further, the upper and lower positions are defined by the positions of the substrate 10 in the present specification. Assume that the direction approaching the substrate 10 is downward and the direction away from the substrate 10 is upward. The setting of the vertical position in this specification is limited to the description of the positional relationship of the respective components in the illustrated embodiment, and does not represent an indication or suggestion that it is necessary to have a specific orientation.

The epitaxial structure 20 may be formed on the substrate 10 by Metal Organic Chemical Vapor Deposition (MOCVD), molecular Beam Epitaxy (MBE), hydride vapor deposition (HVPE), physical Vapor Deposition (PVD), or ion plating. Specifically, the substrate 10 has opposite upper and lower surfaces, and the epitaxial structure 20 is formed on the upper surface of the substrate 10. Wherein the first semiconductor layer 21 may be grown from the upper surface of the substrate 10, and the light emitting layer 22 (or active layer 22, active layer 22) and the second semiconductor layer 23 are sequentially grown on the upper surface of the first semiconductor layer 21 in a stacked manner. In other embodiments, the epitaxial structure 20 may also be formed on the substrate 10 by a bonding layer, which is preferably a light transmissive material.

The epitaxial structure 20 may provide light of a particular center emission wavelength, such as blue, green, or red, or violet, or ultraviolet light. The present embodiment is described with respect to the epitaxial structure 20 providing blue light. In the illustrated embodiment, the first semiconductor layer 21 in the epitaxial structure 20 is an N-type semiconductor layer, and electrons can be supplied to the light emitting layer 22 under the power supply. In some embodiments, the N-type semiconductor layer in the first semiconductor layer 21 includes an N-type doped nitride layer. The N-doped nitride layer may include one or more N-type impurities of a group IV element. The N-type impurity may be one of Si, ge, sn, or a combination thereof.

In other embodiments, for example, when the epitaxial structure 20 is for providing red light or infrared light, the first semiconductor layer 21 may be N-doped AlGaInP, alGaAs, or other materials of the same system as the two.

The light emitting layer 22 may be a Quantum Well (QW) structure. In some embodiments, the light emitting layer 22 (or active layer 22, active layer 22) may be a multiple quantum well (multiple quantum wells, abbreviated as MQWs) structure that is alternately stacked by quantum well layers and quantum barrier layers. The light emitting layer 22 may be a single quantum well structure or a multiple quantum well structure. The quantum barrier layer may be a GaN layer or an AlGaN layer. In some embodiments, the light emitting layer 22 may include a multiple quantum well structure of GaN/AlGaN, inAlGaN/InAlGaN, inGaN/AlGaN, gaInP/AlGaInP, or GaInP/AlInP. To increase the light emitting efficiency of the light emitting layer 22, this may be achieved by varying the depth of the quantum wells, the number of layers, thickness and/or other features of the pairs of quantum wells and quantum barriers in the light emitting layer 22.

In the illustrated embodiment, the second semiconductor layer 23 in the epitaxial structure 20 is a P-type semiconductor layer, and holes can be provided to the light emitting layer 22 under the power supply. In some embodiments, the P-type semiconductor layer in the second semiconductor layer 23 includes a P-type doped nitride layer, a phosphide layer, or an arsenide layer. A P-doped nitride layer, a phosphide layer or an arsenide layer. One or more group II P-type impurities may be included. The P-type impurity may Be one of Mg, zn, be, or a combination thereof. The second semiconductor layer 23 may have a single-layer structure or a multi-layer structure having different compositions. The arrangement of the epitaxial structure 20 is not limited thereto, and other types of epitaxial structures 20 may be selected according to practical requirements.

In some embodiments, a buffer layer (not shown) may be provided between the substrate 10 and the epitaxial structure 20 in the light emitting diode 1 to mitigate lattice mismatch between the substrate 10 and the first semiconductor layer 21. In some embodiments, the buffer layer may include an unintentionally doped GaN layer (u-GaN for short) or an unintentionally doped AlGaN layer (u-AlGaN for short).

The buffer layer may be a single layer or multiple layers. The buffer layer may be formed by metal organic chemical vapor deposition, molecular beam epitaxy, or physical vapor deposition (Physical Vapour Deposition, abbreviated as PVD). Wherein, physical vapor deposition may include sputtering (sputtering), such as reactive sputtering, or evaporation; such as electron beam evaporation or thermal evaporation. In one embodiment, the buffer layer may include an aluminum nitride (AlN) buffer layer formed on the substrate 10 having the patterned structural surface by a sputtering method. Sputtering can form a dense buffer layer with high uniformity, so that an aluminum nitride buffer layer can be deposited on the patterned structured surface of the substrate 10.

In some embodiments, a portion of the epitaxial structure 20 is removed from the second semiconductor layer 23 and the light emitting layer 22 to expose the first semiconductor layer 21, forming one or more mesas. That is, the mesa is a surface of the first semiconductor layer 21 not covered by the second semiconductor layer 23 and the light emitting layer 22. The mesa may be used to provide the first contact electrode. The distribution of the mesas can be designed according to the actual chip size and shape, and the mesas can be connected together or separated from each other.

The light emitting diode 1 may further include a first electrode 30 and a second electrode 40, which are separated from each other. As shown in fig. 1, the first electrode 30 is an N electrode, and the second electrode 40 is a P electrode. In the illustrated embodiment, the first electrode 30 and the second electrode 40 are ohmic contact electrodes. The first electrode 30 is disposed on the upper surface of the first semiconductor layer 21 and electrically connected to the first semiconductor layer 21. The second electrode 40 is disposed on the upper surface of the second semiconductor layer 23 and is electrically connected to the second semiconductor layer 23.

The first electrode 30 may have a single-layer, double-layer or multi-layer structure, and has a thickness of 1000 to 5000 angstroms. The first electrode 30 may be formed of a stack of one or more electrode layers of chromium, nickel, aluminum, titanium, platinum, gold, palladium, silver, or the like. In other embodiments, the first electrode 30 may be one of Ni, geAu, au and combinations thereof. In some embodiments, the first electrode 30 may be formed directly on the mesa of the epitaxial structure 20, the first semiconductor layer 21 having a higher Al composition, and the first electrode 30 being alloyed by high temperature fusion after being deposited on the mesa, thereby forming a good ohmic contact with the first semiconductor layer 21.

The second electrode 40 may be made of a transparent conductive material or a metal material, and may be adaptively selected according to doping conditions of a surface layer (e.g., a p-type GaN surface layer) of the second semiconductor layer 23. The thickness of the second electrode 40 is 1000 angstroms to 5000 angstroms. In some embodiments, the second electrode 40 is made of a transparent conductive material, which may include Indium Tin Oxide (ITO), zinc indium oxide (IZO), indium oxide (InO), tin oxide (SnO), cadmium Tin Oxide (CTO), tin antimony oxide (ATO), aluminum Zinc Oxide (AZO), zinc Tin Oxide (ZTO), zinc doped gallium oxide (GZO), indium doped tungsten oxide (IWO), or zinc oxide (ZnO), but the embodiments of the present disclosure are not limited thereto. In some embodiments, the second electrode 40 may be formed from a stack of one or more electrode layers of chromium, nickel, aluminum, titanium, platinum, gold, palladium, silver, or the like. In other embodiments, the second electrode 40 may be one of Au, beAu, znAu and combinations thereof.

The insulating layer 50 is formed on the epitaxial structure 20 and covers at least the upper surfaces and sidewall regions of the epitaxial structure 20, the first electrode 30 and the second electrode 40, and can be used to prevent the first semiconductor layer 21 and the second semiconductor layer 23 from being electrically connected due to leakage of the conductive material, so as to reduce the abnormal short circuit of the light emitting diode 1, but the embodiment of the disclosure is not limited thereto. The insulating layer 50 may be one of a single-layer structure, a double-layer structure, or a multi-layer structure. The thickness of the insulating layer 50 is 1.2 μm to 2.0 μm to fill and cover the exposed surfaces of the substrate 10, the epitaxial structure 20, the first electrode 30 and the second electrode 40, thereby realizing insulation protection.

Referring to fig. 1 'in conjunction with fig. 1, fig. 1' is a schematic cross-sectional view of an embodiment of a conventional led. In the conventional light emitting diode 1', after the insulating layer 50 is formed over the substrate 10, the epitaxial structure 20, the first electrode 30, and the second electrode 40, a height difference h is formed between the upper surface of the insulating layer 50 formed on the upper surface of the first electrode 30 and the upper surface of the insulating layer 50 formed on the upper surface of the second electrode 40. It is understood that the upper surface of the insulating layer 50 above the first electrode 30 is not on the same contour as the upper surface of the insulating layer 50 above the second electrode 40. In the present invention, after the insulating layer 50 is formed, the upper surface of the insulating layer 50 above the first electrode 30 and the upper surface of the insulating layer 50 above the second electrode 40 are in the same constant-height plane. That is, in comparison with the conventional light emitting diode 1', the present invention makes the insulating layer 50 formed over the first electrode 30 and the second electrode 40 have no level difference in the process of forming the insulating layer 50, so that it is possible to ensure that there is no level difference between the upper surface of the formed first pad 60 and the upper surface of the second pad 70.

The material of the insulating layer 50 comprises a non-conductive material. The non-conductive material is preferably an inorganic material or a dielectric material. The inorganic material may comprise silica gel. The dielectric material may comprise an electrically insulating material such as aluminum oxide, silicon nitride, silicon oxide, titanium oxide, or magnesium fluoride. For example, the insulating layer may be silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, or a combination thereof, which may be, for example, a bragg reflector (DBR) formed by repeatedly stacking two materials of different refractive indices.

In the illustrated embodiment, the insulating layer 50 is formed on the epitaxial structure 20 by spin coating, and a flat constant-height surface is formed above the first semiconductor layer 21, the second semiconductor layer 23, the first electrode 30, and the second electrode 40. The spin-on glass (SOG) is a solution containing dielectric material and is applied uniformly on the wafer surface by spin coating to fill the holes of the recesses of the deposited dielectric layer. Then, the solvent is removed by heat treatment, and the solidified (Curing) approximate silicon dioxide (SiO) is left on the wafer surface ₂ ) Dielectric of (2)A material.

In one embodiment, as shown, the insulating layer 50 may be a single layer structure, utilizing flowable SiO ₂ Or the insulating adhesive material is subjected to spin coating to fill up the height difference between the first electrode 30 and the second electrode 40, so as to form a constant-height surface above the first electrode 30 and the second electrode 40. Furthermore, siO ₂ Or the insulating adhesive material can be used as an insulating layer to protect the side wall of the chip, so that the overall stable photoelectric performance of the light-emitting diode 1 is ensured. The insulating adhesive material is preferably an exposable insulating adhesive material, so as to facilitate the implementation of subsequent manufacturing processes. The insulating adhesive material at least contains carbon (C) and oxygen (O).

In other embodiments, the insulating layer 50 may be a multi-layer structure. In one embodiment, the insulating layer 50 formed over the second electrode 40 includes a transparent conductive layer and SiO ₂ Or a passivation layer formed of an insulating paste. The transparent conductive layer serves as a current spreading between the second electrode 40 and the second semiconductor layer 23. The transparent conductive layer is an indium tin oxide layer or other transparent conductive material doped with aluminum zinc oxide. When the material of the epitaxial structure circuit 20 is GaN series, the thickness of the transparent conductive layer is 50 to 1000 angstroms.

A first through hole 51 and a second through hole 52 are respectively provided in the insulating layer 50 corresponding to the upper sides of the first electrode 30 and the second electrode 40. The first pad 60 and the second pad 70 are located on a portion of the upper surface of the insulating layer 50 and are electrically connected to the first electrode 30 and the second electrode 40 through the first via hole 51 and the second via hole 52, respectively. Wherein the upper surfaces of the first pads 60 and the second pads 70 are located in the same plane. It is understood that the upper surfaces of the first pads 60 and the second pads 70 are on the same contour. The first pad 60 and the second pad 70 may be metal pads, may be formed together using the same material in the same process, and thus may have the same layer structure.

As shown in fig. 1, a thickness H1 between the upper surface of the first pad 60 and the upper surface of the insulating layer 50 is equal to a thickness H2 (h1=h2) between the upper surface of the second pad 70 and the upper surface of the insulating layer 50. The upper surface of the insulating layer 50 above the first and second electrodes 30 and 40 is a constant-height surface, and in this case, the thicknesses of the first and second pads 60 and 70 above the upper surface of the insulating layer 50 are equal, so that the upper surfaces of the first and second pads 60 and 70 are located at the same height or in the same plane.

The thickness H1 between the upper surface of the first pad 60 and the upper surface of the insulating layer 50 and the thickness H1 between the upper surface of the second pad 70 and the upper surface of the insulating layer 50 are respectively equal to or greater than 2 μm to ensure good electrical connection between the first pad 60 and the first electrode 30 and between the second pad 70 and the second electrode 40. In a preferred embodiment, the thickness H1 between the upper surface of the first pad 60 and the upper surface of the insulating layer 50 and the thickness H2 between the upper surface of the second pad 70 and the upper surface of the insulating layer 50 are 2 μm to 4 μm. Thus, when the light emitting diode 1 is a Mini LED or a Micro LED, there is enough insulation protection above the first electrode 30 and the second electrode 40, and at the same time, the light emitting diode 1 has better photoelectric performance as a whole.

The core particle size of the light emitting diode 1 is 300 μm or less. For example: the light emitting diode may be a Mini LED or a Micro LED.

An embodiment of the present invention proposes a method for manufacturing a light emitting diode 1, which can be used to manufacture the light emitting diode 1 having the above-described structure. Fig. 2 is a schematic flow chart of a manufacturing method of the light emitting diode 1 according to a preferred embodiment of the invention, but the manufacturing method and flow chart of the light emitting diode 1 according to the invention are not limited to those shown in fig. 2.

Referring to fig. 3 to 7 in combination with fig. 1 and 2, fig. 3 to 7 are schematic process views of a preferred embodiment of a method for manufacturing a light emitting diode 1 according to the present invention. The flow of the manufacturing method of the light emitting diode 1 shown in fig. 1 obtained by the manufacturing method of the light emitting diode 1 shown in fig. 2 is described as follows.

The manufacturing method of the light emitting diode 1 may at least comprise the steps of: epitaxial structure 20 is grown, electrodes 30/40 are provided, insulating layer 50 is fabricated, connecting vias 51/52 are fabricated, and connecting pads 60/70 are fabricated. The specific implementation of each step is described below.

Step S11: growth of epitaxial structure 20

As shown in fig. 3, a substrate 10 is provided, and a first semiconductor layer 21, a light emitting layer 22, and a second semiconductor layer 23 are sequentially grown on an upper surface of the substrate 10, thereby forming an epitaxial structure 20 on the upper surface of the substrate 10.

In the illustrated embodiment, the substrate 10 is a sapphire substrate. In the epitaxial structure 20 grown on the sapphire substrate 10, the first semiconductor layer 21 is an N-type semiconductor layer, and the second semiconductor layer 23 is a P-type semiconductor layer. A portion of the epitaxial structure 20 is removed from the second semiconductor layer 23 and the light emitting layer 22 to expose the first semiconductor layer 21 to form one or more mesas 24. The mesa 24 refers to a surface of the first semiconductor layer 21 that is not covered by the second semiconductor layer 23 and the light emitting layer 22. The mesa 24 may be used for providing a first contact electrode. Mesa 24 may be formed by an etching method.

In some embodiments, after step S11, the method further includes the steps of: the side edges of the first semiconductor layer 21 in the epitaxial structure 20 are etched to expose a portion of the substrate 10 to facilitate a subsequent structural process of the light emitting diode 1.

Step S12: setting electrodes 30/40

As shown in fig. 4, an electrode is provided on the epitaxial structure 20 grown in step S11. A first electrode 30 (or N-electrode) is formed on mesa 24 on the upper surface of first semiconductor layer (N-type) 21 in epitaxial structure 20, and a second electrode 40 (or P-electrode) is formed on the upper surface of second semiconductor layer (P-type) 23.

The N electrode 30 and the P electrode 40 are ohmic contact electrodes. The N electrode 30 may be formed by stacking one or more electrode layers of chromium, nickel, aluminum, titanium, platinum, gold, palladium, silver, or the like. In some embodiments, the first electrode 30 may be formed directly on the mesa of the epitaxial structure 20, the first semiconductor layer 21 having a higher Al composition, and the first electrode 30 being alloyed by high temperature fusion after being deposited on the mesa, thereby forming a good ohmic contact with the first semiconductor layer 21. The P-electrode 40 may be made of a transparent conductive material or a metal material, and may be adaptively selected according to the doping condition of the surface layer (e.g., P-type GaN surface layer) of the second semiconductor layer 23.

Step S13: manufacture of insulating layer 50

As shown in fig. 5, an insulating layer 50 is formed on the first electrode 30, the second electrode 40, and the upper surface of the epitaxial structure 20 formed in step S12. In the illustration, the insulating layer 50 is formed on the epitaxial structure 20 to cover at least the upper surfaces and sidewall areas of the epitaxial structure 20, the first electrode 30 and the second electrode 40 and the upper surface of a portion of the substrate 10, and can be used to prevent the first semiconductor layer 21 and the second semiconductor layer 23 from being electrically connected due to leakage of the conductive material, so as to reduce the abnormal short circuit of the light emitting diode 1, but the embodiment of the disclosure is not limited thereto. The thickness of the insulating layer 50 is 1.2 μm to 2.0 μm to fill and cover the exposed surfaces of the substrate 10, the epitaxial structure 20, the first electrode 30 and the second electrode 40, thereby realizing insulation protection.

In a preferred embodiment, the insulating layer 50 is a single layer structure, such as SiO, with fluidity ₂ Or the insulating paste is spin-coated, and a flat constant-height surface is formed over the first semiconductor layer 21, the second semiconductor layer 23, the first electrode 30, and the second electrode 40. In other words, the insulating layer 50 formed by the spin coating method forms a constant-height surface over the first electrode 30 and the second electrode 40 to fill up the height difference between the first electrode 30 and the second electrode 40. Furthermore, siO ₂ Or the insulating adhesive material can be used as an insulating layer to protect the side wall of the chip, so that the overall stable photoelectric performance of the light-emitting diode 1 is ensured. The insulating adhesive material is preferably an exposable insulating adhesive material, so as to facilitate the implementation of subsequent manufacturing processes. The insulating adhesive material at least contains carbon (C) and oxygen (O).

Step S14: making connection vias 51/52

As shown in fig. 6, a connection via is made in the insulating layer 50 formed in step S13. The insulating layer 50 is subjected to a polishing process so that the surface of the insulating layer 50 remains smooth. When the insulating layer 50 is made of flowable SiO ₂ When manufactured, the circuit-via first and second vias 51 and 52 are formed in the insulating layer 50 using a dry etching or wet etching process. In a preferred embodiment, in the formation of the connection via, a photoresist is coated on the insulating layer 50 in a yellow light environment, and then dry etching or wet etching is performedThe etching process forms a circuit via first via 51 and a second via 52 in the insulating layer 50. When the insulating layer 50 is made of an exposable insulating adhesive material, the first through hole 51 and the second through hole 52 of the circuit path can be formed in the edge layer 50 by direct development, so that the etching process of the insulating adhesive material is omitted, and the operation is convenient.

The first through hole 51 may expose a portion of the upper surface of the first electrode 30, so as to provide a desired contact surface for subsequent electrical connection of the first electrode 30. The second through hole 52 may expose a portion of the upper surface of the second electrode 40 to provide a desired contact surface for subsequent electrical connection of the second electrode 40. The upper surfaces of the first through hole 51 and the second through hole 52 are flush or in the same contour plane.

Step S15: connection pads 60/70

As shown in fig. 7, the first and second pads 60 and 70 are plated on the upper surfaces of the first and second electrodes 30 and 40, respectively, via the first and second through holes 51 and 52 formed in step S14. The upper surfaces or upper end surfaces of the first and second pads 60 and 70, which are positioned on or exposed from the upper surface of the insulating layer 50, are flush.

Referring to fig. 1 in conjunction with fig. 7, a pitch (thickness H1) between the upper surface of the first pad 60 and the upper surface of the insulating layer 50 is equal to a pitch (thickness H2) between the upper surface of the second pad 70 and the upper surface of the insulating layer 50. In other words, the first and second pads 60 and 70 are exposed above the insulating layer 50 to the same height, respectively.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A light emitting diode, characterized by: at least comprises:

a substrate;

the epitaxial structure is arranged on part of the upper surface of the substrate and comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially stacked;

the first electrode is positioned on the upper surface of the first semiconductor layer and is electrically connected with the first semiconductor layer;

the second electrode is positioned on the upper surface of the second semiconductor layer and is electrically connected with the second semiconductor layer;

an insulating layer formed on the epitaxial structure and at least covering the upper surfaces and sidewall regions of the epitaxial structure, the first electrode and the second electrode, wherein the upper surface of the insulating layer formed on the upper surface of the first electrode and the upper surface of the insulating layer formed on the upper surface of the second electrode are positioned in the same constant-height plane;

the first bonding pad is positioned on part of the upper surface of the insulating layer and is electrically connected with the first electrode;

the second bonding pad is positioned on part of the upper surface of the insulating layer and is electrically connected with the second electrode;

wherein, the upper surface of the first bonding pad and the upper surface of the second bonding pad are positioned in the same plane.

2. A light emitting diode according to claim 1 wherein: the insulating layer is one of a single-layer structure, a double-layer structure or a multi-layer structure.

3. A light emitting diode according to claim 1 wherein: the thickness of the insulating layer is 1.2-2.0 mu m.

4. A light emitting diode according to claim 1 wherein: the insulating layer is made of at least one of flowable silicon dioxide and insulating adhesive.

5. A light emitting diode according to claim 4 wherein: the insulating adhesive material at least contains carbon and oxygen elements.

6. A light emitting diode according to claim 1 wherein: the first bonding pad and the second bonding pad are at least one of Ti, pt, au, ni, sn and an alloy thereof, and the thickness between the upper surfaces of the first bonding pad and the second bonding pad and the upper surface of the insulating layer is more than or equal to 2 mu m respectively.

7. A light emitting diode according to claim 1 wherein: the first electrode and the second electrode are ohmic contact electrodes, the first electrode and the second electrode are at least one of chromium, nickel, aluminum, titanium, platinum, gold, palladium, silver and combinations thereof, and the thicknesses of the first electrode and the second electrode are respectively 1000-5000 angstroms.

8. A light emitting diode according to claim 1 wherein: the first electrode and the second electrode are at least one of BeAu, znAu, ni, geAu, au and a combination thereof, and the thicknesses of the first electrode and the second electrode are respectively 1000-5000 angstroms.

9. A light emitting diode according to claim 1 wherein: the core particle size of the light emitting diode is 300 mu m or less.

10. A method of manufacturing a light emitting diode, the method comprising:

growing an epitaxial structure, and sequentially growing a first semiconductor layer, a light-emitting layer and a second semiconductor layer on a substrate to form the epitaxial structure;

setting electrodes, namely forming a first electrode and a second electrode on part of the upper surfaces of the first semiconductor layer and the second semiconductor layer respectively, wherein the first electrode is electrically connected with the first semiconductor layer, and the second electrode is electrically connected with the second semiconductor layer;

manufacturing an insulating layer, and forming the insulating layer on the epitaxial structure in a spin coating mode, wherein the insulating layer at least covers the upper surfaces and side wall areas of the epitaxial structure, the first electrode and the second electrode;

manufacturing a connecting through hole, and forming a first through hole and a second through hole in the insulating layer area corresponding to the upper parts of the first electrode and the second electrode respectively;

and the first bonding pad and the second bonding pad are respectively and electrically connected with the first electrode and the second electrode through the first through hole and the second through hole, and the upper surfaces of the first bonding pad and the second bonding pad are positioned in the same plane.

11. The method of manufacturing a light emitting diode according to claim 10, wherein: in the step of coating the insulating layer, the insulating layer is formed on the epitaxial structure in a spin coating manner by adopting flowable silicon dioxide or insulating gel material.

12. The method of manufacturing a light emitting diode according to claim 10, wherein: in the step of manufacturing the connection channel, the adopted manufacturing method is one of dry etching, wet etching or exposure and development.