CN111462651B

CN111462651B - Light-emitting display substrate for assembling surface-mounted micro LED fluid and preparation method

Info

Publication number: CN111462651B
Application number: CN202010351855.4A
Authority: CN
Inventors: 保罗·约翰·舒勒; 战长青; 佐佐木健司; 葛特鄂孟; 李宗霑
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2019-05-08
Filing date: 2020-04-28
Publication date: 2021-12-10
Anticipated expiration: 2040-04-28
Also published as: TW202042287A; TWI750650B; CN111462651A

Abstract

A light-emitting display substrate for surface mount micro LED fluid assembly and a preparation method thereof are provided. The light emitting display substrate includes: a support substrate having a planar top surface and a Light Emitting Diode (LED) cross-point control matrix comprising an array of column and row conductors; a first thin film layer covering a top surface of the support substrate and including a plurality of wells; wherein each well has a convex bottom surface, a first substrate electrode connected to a corresponding column wire, and a second substrate electrode connected to a corresponding row wire.

Description

Light-emitting display substrate for assembling surface-mounted micro LED fluid and preparation method

Technical Field

The present invention relates generally to display technology and more particularly to the design of Surface Mount (SM) inorganic micro light emitting diodes (μ LEDs) with improved electrode interface surface flatness.

Background

A color display is composed of pixels that emit light of three wavelengths corresponding to visible red, green, and blue colors, which is called an RGB display. The RGB elements of a pixel are turned on and off in an orderly fashion to produce colors that sum to the visible spectrum. There are several display types that can generate RGB images in different ways. Liquid Crystal Displays (LCDs) are the most popular technology, which produce RGB images by illuminating a white light source (typically a phosphor-produced white LED) through a color filter of a subpixel. Some portion of the white light wavelengths are absorbed while others pass through color filters transmissive color filters. Organic Light Emitting Diode (OLED) displays generate RGB light by directly emitting light of each of those wavelengths at the pixel level from inside an organic light emitting material. Organic Light Emitting Diode (OLED) displays generate RGB light by directly emitting light of each of those wavelengths at the pixel level from inside an organic light emitting material.

A third display technology is miniature LED displays. This display technology uses micron-sized (10 to 150 μm in diameter) inorganic LEDs to directly emit light at the pixel level. To fabricate an RGB display using micro-LEDs, a large area array of three different types of micro-LEDs emitting light in each RGB wavelength range, respectively, must be assembled. Low cost manufacturing of micro LED displays requires the use of massively parallel fluid assembly techniques to place millions of individual micro LEDs in a regular array. Currently the mainstream television with HDTV resolution has 600 million pixels, while the higher resolution 4K and 8K standards have 25 and 99 million pixels, respectively.

In order to produce a high-yield, low-cost display with adequate brightness, fluid assembly techniques place some unique requirements on micro LED structures, some of which are discussed herein. Practical display technologies have to address the reality that displays are manufactured in different sizes and resolutions, thus requiring flexibility in pixel size, from 300 pixels per inch (ppi) for personal devices to very high 10-20ppi large public information display applications. The display brightness requirements also vary from application to application, with a cell phone display requiring 300 nits (candela per square meter), a television requiring 1000 nits, and an outdoor information display requiring 5000 nits. Therefore, micro-LED technology must accommodate a wide range of resolution and brightness requirements while still maintaining the physical properties necessary for assembly using fluids.

The development of gallium nitride (GaN) -based blue LEDs for general illumination and aluminum gallium phosphide (AlGaInP) red LEDs for various indicator lamps has been developed for many generations and these processes can produce reliable, efficient devices at very low cost. Therefore, perhaps the most important requirement is that the micro LED structures be compatible with conventional Metal Organic Chemical Vapor Deposition (MOCVD) fabrication of commercial inorganic LEDs. There are many possible variations in LED manufacturing, and therefore this summary provides only a very brief overview to identify the factors needed to manufacture a high quality LED, while also describing the unique differences between conventional LEDs and the miniature LEDs described herein. AlGaInP-based red LEDs by chang and Liu (Ning Zhang and Zhiqiang Liu, "InGaN material systems and blue/green emitters", in Li, Jinmin, Zhang, g.q. (braids), light emitting diodes, solid state lighting technology and applications series 4(Springer, Switzerland, 2019)) and Wang et al (Guohong Wang, Xiaoyan Yi, Teng Zhan, and Yang huangang, "AlGaInP/AlGaAs material systems and red/yellow LEDs", Li, Jinmin, Zhang, G.Q. (braids), light emitting diodes, solid state lighting technology and applications series 4(Springer, Switzerland, inventors: Schuele, Zhan, Sasaki, Ulmer and Lee 2019) are useful in the visible spectrum for conventional LED technology.

Fig. 1A to 1C are diagrams depicting a GaN LED wafer for general illumination purposes (prior art). A GaN-based LED emitting blue (about 440 nanometers (nm)) and green (about 530nm) light was fabricated in a complex series of high temperature MOCVD steps to produce the vertical LED structure shown in cross-section in fig. 1A. Fabrication is performed on a growth substrate of polished sapphire, silicon (Si), or silicon carbide (SiC) having a diameter of 50 to 200 millimeters (mm). The surface is prepared by depositing an optional AIN buffer layer and undoped GaN to produce a crystal surface with low defects and GaN lattice constant. The thickness and temperature of this initial deposition are adjusted to compensate for the lattice mismatch between the growth substrate and the GaN. Surface weight increases with increasing thickness, and thus the thickness of high efficiency devices exceeds about 3 micrometers (μm). Since the MOCVD deposition process is complex and expensive, it is important to optimize the micro LED process to most effectively utilize the entire area of the growth wafer (growth substrate).

After initial growth to prepare a crystalline GaN surface, a first LED layer is grown and Si doping is added to produce n + GaN (n-GaN) for the cathode. Alternatively, the stack may comprise layers tuned for electron injection and hole blocking. Next, indium gallium nitride (In) is used_xGa_1-xN) and GaN, wherein the indium content and the thickness of the layers determine the wavelength of the emitted light of the device. An increase in indium content shifts the emission peak to longer wavelengths, but internal stress is also increased due to lattice mismatch, so that a high-efficiency GaN device cannot be fabricated for red light emission, and the efficiency of a green light emitting device is lower than that of a blue LED. After the MQW, the stack may include tuning for electron blocking and hole injectionAnd (4) forming a whole layer. Finally, the MOCVD sequence is completed by depositing magnesium (Mg) doped GaN to form a p + anode.

The completed substrate is then patterned and etched to form individual LEDs, and additional processing is performed to form electrodes on the anode and cathode, as shown in fig. 1B. In the simplest process flow, nickel oxide (NiO) is deposited_x) To match the p + GaN (p-GaN) work function, and then depositing a layer of Indium Tin Oxide (ITO) 100 to 300nm thick to form a transparent conductive electrode. This layer is patterned and etched to form a current spreading layer over the anode.

A small area is patterned and etched through the stack to make contact with the n + GaN. Passivation layer, typically silicon dioxide (SiO)₂) Deposited to prevent leakage current between the anode and cathode, and provided with a contact window above the electrode. Electrodes (typically made of titanium/aluminum (Ti/Al)) are deposited to form the cathode contact points, and a second electrode (anode) is added, which may be nickel/gold (Ni/Au), chromium/gold (Cr/Au), or the like. The substrate is thinned to about 100 μm by grinding and the individual devices are singulated by cutting or sawing. The devices produced by this process are typically 100 μm thick and have dimensions (cross-section) of 150 to 1000 μm, as shown, for example, in FIG. 1C.

Fig. 2A and 2B are diagrams illustrating gallium arsenide (GaAs) LED wafers used to manufacture red light emitting indicators (prior art). As shown in fig. 2A, a high brightness red LED is fabricated using a significantly different MOCVD process sequence based on a GaAs material system. The growth substrate is a wafer of n-doped GaAs that is several hundred microns thick, the first layer deposited being GaAs to produce a high quality crystal surface. The next layer is aluminum/arsenide (AlAs), which is then used as the release layer. The LED stack may start with an optional n-doped Distributed Bragg Reflector (DBR) layer or an n-doped GaInP window layer and an n-doped AlGaInP cladding layer. Alternating layers of AlGaInP and AlGaAs are then deposited over the MQW active region, and their thickness and composition are adjusted to cause the high efficiency LED to emit light at selected wavelengths. The active region is covered with a p-doped cladding layer of AlGaInP and a p-doped GaInP window layer to complete the LED. The thickness of the entire LED stack above the AlAs release layer may be 10 to 15 μm.

The GaAs growth substrate is lattice matched to the MOCVD growth of AlGaInP, but GaAs absorbs light and is very brittle, which is a serious drawback for LED packages. Thus, as shown in fig. 2B, the LED device is removed from the substrate by completely etching the substrate or by undercutting and releasing the device using a selective wet etch, typically hydrochloric acid (HCl): acetic acid. A thick layer of copper deposited by electroplating serves as a heat sink and process interface for each device before the LEDs are removed from the substrate. First, a gold strike layer is deposited and patterned to define copper regions, and then copper is electroplated to a thickness of about 100 μm. The LED stack is then etched down around the copper islands to the GaAs buffer layer, followed by a wet etch of the AlAs layer to release the etch undercut. The device dimensions (cross-section) are similar to 150 to 1000 microns for GaN general illumination LEDs.

Fig. 3A and 3B depict partial cross-sectional views of conventional packaged blue and red LEDs (prior art), respectively. These figures are presented to distinguish between miniature LEDs (provided in the detailed description below) and conventional packaging techniques for larger LEDs. For general illumination, white light is produced from a blue-emitting GaN device, as shown in FIG. 1B, with one additional color converting phosphor covering the LED and converting some of the blue light to longer wavelengths, typically a broad yellow emitting phosphor, such as cerium (III) doped YAG (YAG: Ce)^3-Or Y₃Al₅O₁₂：Ce³⁺). The package used has a leadframe for making electrical connections, a heat sink for dissipating the heat energy generated in the LED and a reflector to direct the light to the user. The LED is adhered to the radiating fin through heat conducting glue, and the LED terminal is connected with the lead frame through lead wire adhesion. After bonding, the package cavity is filled with a transparent encapsulant, typically silicone or epoxy, which protects the device from mechanical damage and from atmospheric air and water. The encapsulant may also contain a color converting phosphor, or the phosphor may be in a separate film over the encapsulation (not shown). After packaging is complete, the device will be tested for efficiency and peak wavelength in a process called binning. If the device has acceptable performance, it is glued to the print along with the other devices in the arrayOn a circuit board (PCB). It is important to note that the lighting array contains multiple devices in series, parallel, or series/parallel depending on the desired operating voltage and brightness. Unlike display arrays (e.g., television or smartphone displays) which require each pixel to have a controllable brightness to produce an image, all devices in a common illumination array operate simultaneously.

Fabricating displays with pixel densities (PPI) in the range of 10 to 600 necessarily requires the cross-section (diameter) of the micro-LEDs to be less than 150 microns. As described in more detail below, the micro-LED dimensions and internal structures are created by using conventional photolithography processes to form patterns controlled by mask design, film thickness, and photoresist exposure. Using the lithographic pattern as a mask, an etching process selectively removes material to form features of the completed device. In the case of GaN, for example, etching does not proceed completely uniformly across the entire wafer and between wafers, and therefore the amount of build-up required to create a structure with coplanar N-pad (the electrode connecting the N + semiconductor) and P-pad (the electrode connecting the P + semiconductor) may vary greatly. Deposition of the deposit metal is done by evaporation or sputtering and the thickness control is even less precise than the photolithography step. If the N-pad and P-pad electrodes of the micro LED are not coplanar, the electrical connection of the micro LED to the display substrate may be incomplete, resulting in failure or high series resistance.

For the purpose of minimizing failures in the manufacture of display substrates using SM-LEDs, it would be advantageous if the substrate interface of the LED electrodes could be maximally flat.

Disclosure of Invention

Described herein are miniature Light Emitting Diode (LED) structures between 10 and 150 μm in diameter that are suitable for large area array fluidic assembly to fabricate high resolution red-green-blue (RGB) displays. The fabrication process of the micro-LEDs is compatible with gallium nitride (GaN) based blue/green LEDs and aluminum gallium indium phosphide (AlGaInP) based red LEDs produced by conventional metal-organic chemical vapor deposition (MOCVD) growth techniques. The resulting micro-LEDs have electrode structures that can electrically and physically bond to array contacts in a display substrate after fluid assembly to form an active or passive matrix display. The disclosed micro LED structure is capable of varying pixel brightness within a range satisfying different display requirements without changing the structure of the micro LED, thereby not affecting the yield and reliability of the fluid assembly process.

Accordingly, a method for manufacturing a Surface Mount (SM) micro LED (μ LED) is provided. The method provides an MOCVD-LED structure on a growth substrate. A stack overlies a growth substrate comprising a first doped semiconductor having a top surface in a first plane, a Multiple Quantum Well (MQW) layer overlying the first doped semiconductor having a top surface in a second plane, and a second doped semiconductor overlying the MQW layer and having a top surface in a third plane, wherein the first and second doped semiconductors are oppositely doped with n and p dopants, see fig. 1A and 2A. In the case of a gallium nitride micro LED, the first and second doped semiconductors are doped GaN. In the case of gallium arsenide (GaAs) micro LEDs, the first and second doped semiconductors may be doped gallium phosphide (p-GaP) or doped indium gallium phosphide (n-GaInP).

The method etches the MOCVD stack to form a plurality of individual chips on a growth substrate. The μ LEDs are fabricated from each chip by first selectively etching the above-described stack. An electrical insulator is conformally deposited to form a top surface in a fourth plane overlying the etch stack and then selectively etched to expose the second doped semiconductor to create the first via. A selective etch is also performed to expose the first doped semiconductor to form a second via. The first electrode is formed overlying and connected to the second doped semiconductor through the first via and has a substrate interface surface in a fifth plane. A second electrode is formed overlying and connected to the first doped semiconductor through the second via and has a substrate interface surface in a fifth plane. Finally, the fabricated μ LED is separated from the growth substrate. Due to the use of a conventional MOCVD wafer, the LED has a maximum cross-section of 150 microns coplanar with the first, second and third planes, a mesa stack height orthogonal to the first, second and third planes of less than 2 microns, and a mean flatness tolerance of the fifth plane of less than 10 nanometers.

More specifically, the method is capable of fabricating an SM center emitting μ LED by selectively etching the stack to form a central mesa stack surrounded by trenches exposing the first doped semiconductor and a peripheral stack divided by peripheral trench valleys exposing the first doped semiconductor. Then, conformally depositing an electrical insulator on the etch stack includes forming a fourth plane overlying the central mesa stack and the peripheral stack. The step of selectively etching to expose the second doped semiconductor comprises: etching a portion of the electrical insulator overlying the central mesa stack to form a first via, and the step of selectively etching to expose the first doped semiconductor comprises: the electrical insulator overlying the peripheral trench valley is etched to form a second via. As a result, the first electrode overlies the central mesa stack and is connected through the first via to a second doped semiconductor having a substrate interface surface in a fifth plane. The second electrode has a first portion formed on the peripheral trench valley and is connected to the first doped semiconductor through a second via. The second electrode has a second portion (connected to the first portion) overlying the electrical insulator formed on the perimeter stack and having a substrate interface surface in a fifth plane.

The SM peripheral emitting μ LED is formed by selectively etching the stack to form a central mesa stack that is separated from the peripheral stack by a trench that exposes the first doped semiconductor. A conformally deposited electrical insulator covers the central mesa stack and the peripheral stack. The step of selectively etching to expose the second doped semiconductor comprises: etching a portion of the electrical insulator overlying the perimeter stack to expose the second doped semiconductor, and selectively etching to expose the first doped semiconductor comprises: a portion of the electrical insulator, and underlying portions of the second doped semiconductor and the MQW layer in the central mesa stack are etched to expose the first doped semiconductor. As a result, a second electrode is formed overlying the central mesa stack and connected to the first doped semiconductor through the second via. A first electrode is formed overlying the electrical insulator formed on the perimeter stack and connected to the second doped semiconductor through the first via.

A SM-mu LED full-area light emitting mu LED is fabricated by selectively etching the stack to form a mesa stack and a peripheral trench valley in the mesa stack and exposing the first doped semiconductor. The step of selectively etching to expose the second doped semiconductor comprises: the electrically insulating layer is etched to cover a portion of the mesa stack to expose the second doped semiconductor. The step of selectively etching to expose the first doped semiconductor comprises: the electrical insulator covering the peripheral trench valleys is etched. The first electrode covers the mesa stack and is connected to the second doped semiconductor through the first via. The second electrode includes a first portion overlying the perimeter trench via and is connected to the first doped semiconductor through the second via. The second portion of the second electrode (connected to the first portion) covers the electrical insulator formed on the perimeter of the mesa stack and has a substrate interface surface in a fifth plane.

A light emitting display substrate having a non-planar substrate electrode interface surface is also provided. The display consists of a supporting substrate having a planar top surface and an array of LED cross-point control matrices forming an array of column and row conductors. The first thin film layer covers a top surface of the support substrate and includes a plurality of wells. Each well has a convex bottom surface, a first substrate electrode connected to a corresponding column line and a second substrate electrode connected to a corresponding row line. The second thin film layer is interposed between the top surface of the support substrate and the first thin film layer. The convex surfaces of the well bottoms are formed by spacers interposed between the top surface of the support substrate and the second thin film layer and located below the bottom of each well.

Additional details of the above method will be provided below, as well as center, perimeter, full area light emitting SM micro LED devices and light emitting substrates with convex well bottom surfaces.

Drawings

Fig. 1A to 1C are diagrams depicting a GaN-LED wafer (prior art) for general illumination purposes.

Fig. 2A and 2B are diagrams illustrating gallium arsenide (GaAs) LED wafers (prior art) for manufacturing red light emitting indicators.

Fig. 3A and 3B depict partial cross-sectional views of a conventionally packaged blue and red LED (prior art), respectively.

Fig. 4A and 4B are a partial sectional view and a plan view, respectively, of a light emitting element that can be used as a Surface Mount (SM) LED.

Fig. 5 is a partial cross-sectional view depicting an alternative to the LED of fig. 4.

Fig. 6A to 6J depict the steps of manufacturing a micro LED as described in us patent 9,825,202.

Fig. 7A-7C depict the suspension medium applying torque to a micro LED with a navigation keel (post).

Fig. 8A and 8B are a plan view and a partial cross-sectional view, respectively, of a micro LED subpixel layout.

Fig. 9A to 9E are partial cross-sectional views depicting micro LED alignment in an exemplary well variation.

Fig. 10A-10C are partial cross-sectional views of a substrate well and a mating micro LED showing a well bottom surface pad.

Fig. 11A to 11D are a plan view, two partial sectional views and a perspective view, respectively, of a planar SM center-emitting μ LED.

Fig. 12 is a graph showing the relationship between flux and efficiency as a function of current density.

Fig. 13A and 13B are a plan view and a partial sectional view depicting a planar SM peripheral light emission μ LED, respectively.

Fig. 14A and 14B are a plan view and a partial sectional view, respectively, of a planar SM full-area light emission μ LED.

Fig. 15A to 15C are plan views comparing light emitting surface areas of micro LEDs of center light emission (fig. 11A), peripheral light emission (fig. 13A), and full-area light emission (fig. 14A).

Fig. 16 is a flowchart illustrating a method for manufacturing an SM μ LED.

Fig. 17 is a flow chart illustrating a method for manufacturing a display substrate having a well bottom surface pad.

Description of the main elements

SM-LED 300

First electrical contact 306

Second electrical contact 308

Second semiconductor layer 402

First semiconductor layer 404

MQW layers 406, 1106, 1306

Electrical insulators

408, 1314

Row line 802

Column line 804

Light emitting display substrate 1000

Support substrate 1001

Support substrate top surface 1002

First thin film layer 1008

Trap 1010

Convex bottom surface 1012

First substrate electrode 1014

Second substrate electrode 1016

Second thin film layer 1018

TFT layer 1018a

First oxide layer 1018b

Second oxide layer 1018c

Shim 1020

Diameter 1022

Width 1024

Top surface 1026

First electrical interface surface 1028

Second electrical interface surface 1030

Via 1032

Center emitting mu LED1100

First doped

semiconductor

1102, 1302, 1402

Central platforms

1102a, 1302a

Perimeters 1102b, 1302b

Second doped

semiconductor

1110, 1310, 1410

Electrically-insulator

first portions

1114a, 1414a

Electrically-insulator

second portions

1114b, 1414b

Peripheral groove valleys

1118, 1418

First electrodes

1120, 1318, 1420

Center vias

1124, 1320

Second electrode

first portions

1126a, 1424a

Second electrode

second portions

1126b, 1424b

Peripheral vias

1128, 1326, 1426

Trenches

1130, 1328

Etch stack height

1134, 1332, 1430

First plane

1104, 1304, 1404

Second plane

1108, 1308, 1408

Third planes

1112, 1312, 1412

Fourth plane

1116, 1316, 1416

Fifth plane

1122, 1322, 1422

Sixth plane

1132, 1330, 1428

Navigation keel or

post

1136, 1432

Miniature LED1300, 1400

Second electrode 1324

First doped semiconductor

substrate bottom surface

1336, 1434

Landing via 1423

The present invention will be further described with reference to the accompanying drawings.

Detailed Description

A general method of fabricating micro light emitting diode (μ LED) displays using inorganic LEDs and fluid assembly on the display backplane is disclosed in the prior family patent application (U.S. patent No. 9,825,202, application No. 15/412,73), which is incorporated herein by reference. In particular, the process flow for manufacturing a suitable display backplane is described in the description of FIG. 17 in U.S. Pat. No. 9,825,202. The geometrical requirements for the fluid assembly are set forth in the description of fig. 16. The device described herein is an improvement over the surface-mounted micro LED structures discussed in the above-referenced prior family patent applications, which simplifies the manufacture of the device while increasing the yield and versatility of the micro LED display.

U.S. patent No. 9,825,202 describes two types of gallium nitride (GaN) micro LEDs. A structure having a light emitting region at the center of the device is shown in fig. 4A and 4B, and a structure having a light emitter in an outer ring is shown in fig. 5, as described below.

Fig. 4A and 4B are a partial sectional view and a plan view, respectively, of a light emitting element that can be used as a Surface Mount (SM) LED. The SM-LED300 includes a first semiconductor layer 404 having an n-type dopant or a p-type dopant. The second semiconductor layer 402 uses a dopant type that is not used in the first semiconductor layer 404. A Multiple Quantum Well (MQW) layer 406 is interposed between first semiconductor layer 404 and second semiconductor layer 402. The MQW layer 406 may typically be a series of quantum well layers (typically 5 layers, for example alternating 5nm indium gallium nitride (InGaN) and 9nm n-doped GaN (n-GaN)) not shown. There may also be an aluminum gallium nitride (AlGaN) electron blocking layer (not shown) between the MQW layer and the p-doped semiconductor layer. The outer semiconductor layer may be p-doped GaN (Mg-doped) about 200nm thick. If a higher indium content is used in the MQW, a high brightness blue LED or green LED can be formed. The most practical materials for the first and second semiconductor layers are GaN capable of emitting blue or green light or aluminum gallium indium phosphide (AlGaInP) capable of emitting red light.

The second electrical contact 308 is configured in a ring shape, and the first semiconductor layer 404 has a disk shape with a periphery below the ring of second electrical contacts. The first electrical contact 306 is formed within the perimeter of the second electrical contact 308, and the second semiconductor layer 402 and the MQW layer 406 are a stack located below the first electrical contact. A trench may be formed between the ring of second electrical contacts 308 and the first electrical contacts 306 and filled with an electrical insulator 408.

Conventional LED processes (e.g., LEDs used for illumination) occur on one surface only before separation from the sapphire substrate. Some of these processes use laser lift-off (LLO) to separate the LEDs from the sapphire substrate as a final step. Other processes do not use LLO, but rather cut out the sapphire substrate to singulate the LEDs. However, the SM-LED architecture requires electrodes on the surface opposite the posts (navigation keel) in order to fabricate the posts after removal of the μ LEDs from the growth substrate. Conventional processes do not provide a way to maintain a known position of each LED when it is removed from the sapphire, so photolithography can be performed at the bottom of the LED. Precise x-y positions are required to accurately position the post at a desired location (e.g., in the center) on the top surface of the LED. A precise z (vertical) position is required to establish a focal plane for lithography to image the pillar structures with dimensional control (e.g., surface orientation) required for fluid assembly. That is, the LLO of SM-LEDs requires that the SM-LED be placed on a transfer substrate in a controlled manner to form its pillars, which are then released from the transfer substrate to make a suspension for fluid assembly.

Fig. 5 is a partial cross-sectional view depicting an alternative to the LED of fig. 4A. In this aspect, the first electrical contact (electrode) 306 is configured as a ring, and the second semiconductor layer 402 and the MQW layer 406 are ring-shaped stacks below the first electrical contact. The second electrical contact 308 is formed within the perimeter of the first electrical contact 306. The first semiconductor layer 404 has a disk shape with a central portion located below the second electrical contact point. As shown, a trench is formed between the ring of first electrical contacts 306 and the second electrical contacts 308. An electrical insulator 408 fills the trench.

Fig. 6A to 6J depict the steps of manufacturing a micro LED as described in us patent 9,825,202. For consistency of description, the top and bottom surfaces of the micro-LED are defined relative to the growth substrate, which is the last layer grown in the MOCVD process, with electrodes, and the bottom surface with optional pillars. Thus, the surface mount configuration for connecting substrates is bottom-side up. For simplicity, the bottom layer in the MOCVD stack is assumed to be n-GaN and the top layer p-GaN, but of course the opposite structure is possible and the doping and electrode work function can be chosen appropriately. The exemplary fabrication process flows schematically illustrated in fig. 6A to 6J are substantially the same for GaN and GaAs variants, as follows:

1) as described above, the LED stack is deposited on the sapphire wafer by MOCVD. Other substrates, such as silicon carbide (SiC) or silicon, may be used, but sapphire substrates allow for removal of the μ LED from the growth substrate by laser lift-off (LLO), thereby decomposing the GaN at the bottom device surface adjacent to the sapphire substrate. The MQW structure is tuned to produce the desired emission color and the thickness of the resulting structure is between 2 and 7 μm. See also fig. 1A for an example of the various layers.

2) A current spreading layer is deposited on the p-GaN surface. The composition being generally thin NiO_xThe interfacial layer plus a transparent conductive oxide, such as Indium Tin Oxide (ITO), may be 100 to 500 nanometers (nm) in thickness.

3) The light emitting region is defined by photolithography and the MOCVD stack is etched to a depth extending into the n-doped GaN layer. Depending on the MOCVD structure, the etch depth (Z)_MESA) And may be 300nm to 2 micrometers (μm). Typically less than 1 micron.

4) The mu LED area is defined by photolithography and then the entire stack is etched down to the sapphire substrate. Typically, the pattern is an array of closely spaced micro-LEDs to maximize the yield of micro-LEDs on a MOCVD wafer. The size of the micro-LEDs is chosen to match the width of the capture sites on the display substrate and is typically in the range of 15 to 150 μm in diameter.

5) An insulating layer, which may be SU8 or photo-patternable polyimide, is deposited and patterned to prevent current leakage between the N-pad and P-pad.

6) A lithographic pattern is formed to prevent metal deposition outside the N-pad area and a metal layer is deposited to establish the electrodes to match the height of the P-pad. The first layer is chosen to match the work function of n-doped GaN and can be 10 to 50nm thick Ti or Cr. The stacking is accomplished by depositing gold of appropriate thickness to match the height of the active region mesa.

7) The metal and photoresist are removed by lift-off, leaving a build-up on the n-GaN contact area.

8) Photolithography is performed to prevent deposition outside the N-pad and P-pad contact areas, and a metal stack is deposited to connect the μ LED contact holes.

a. The first metal is chosen as a conductive layer between the stack and the solder material and may be chromium/gold (Cr/Au) or titanium/nickel (Ti/Ni) with a total thickness of 100-200 nm.

b. The top layer is a low melting point solder that can be bonded to the substrate electrodes. One system is tin (Sn) alloys such as tin-indium (Sn-In), tin-indium-silver (Sn-In-Ag), and tin-silver-antimony (Sn-Ag-Sb), where the solder metal is chosen to be similar to conventional low melting solder materials. Another metal solder system is gold/germanium (Au/Ge).

9) Excess metal is removed by a lift-off process.

10) The finished wafer dome sides were adhered to a temporary carrier with an adhesive layer and the sapphire growth wafer was removed by LLO (laser lift off).

11) Now, the μ LEDs are bottom up on a temporary carrier in a planar array suitable for further processing. For clarity, the convention of identifying the top and bottom surfaces of the micro-LEDs based on the original growth orientation is maintained.

12) Optionally, the n-GaN may be etched to reduce the thickness of the micro-LED.

13) A post structure for fluid assembly, also known as a navigation keel, may be fabricated on the base near the center of the micro LED. The pillars may be cylindrical, conical, or concave in shape, with the height and diameter of the pillars being selected to facilitate an orientation with the bottom side of the μ LED facing upward during fluid assembly, as explained in more detail below.

14) Finally, the complete μ LED is collected in suspension by dissolving the binder using a suitable solvent.

The micro-LEDs produced by the manufacturing process all have critical dimensions such as diameter, thickness and pillar height, as well as the size and arrangement of electrodes configured to match the geometry of the wells and electrodes on the display substrate, so that the micro-LEDs can be assembled and bonded together with the P-pad and N-pad electrodes, which connect the row and column interfaces of the display substrate, respectively. As shown in fig. 8A and 8B, each sub-pixel has two electrodes centered on a trap structure having vertical walls (also referred to as wells) on a substrate. The disc-shaped micro-LEDs and matching circular wells and electrodes are simply shown, but other shapes such as squares or triangles may be used as long as the shape is designed to match a complementary shape in the substrate so that both micro-LED electrodes are electrically connected to the correct substrate electrode without shorting.

Fluid assembly of micro-LEDs is performed by dispensing the micro-LEDs in a liquid suspension over a display substrate. Some examples of suspension components include water, alcohols, ketones, alkanes, and organic acids. The fluid may be disturbed by some means, such as brushes or blades, or by a flow of solvent or gas, thereby creating a flow of liquid over the entire substrate. As the micro-LEDs move over the substrate, many capture attempts are made as the micro-LEDs are captured and fixed in a substrate well structure to create a self-assembled array of micro-LEDs with their surface mount electrodes precisely positioned in contact with the electrical interface (substrate electrodes) in the substrate well. When the fluid assembly is complete, as determined by an in-situ monitoring system that can determine assembly yield using a camera and machine vision algorithms, the suspension is removed and the display is completed by annealing to form a solder bond between the micro-LEDs and the substrate electrodes. Fluid assembly is essentially a random process, and therefore the dimensions of the device and trap and the parameters of the assembly process are selected based on a statistical analysis of the trapping efficiency.

Fig. 7A-7C depict the suspension medium applying torque to a micro LED with a navigation keel (post). It is well known that the fluid velocity increases parabolically from zero at the enclosed surface, and therefore the force on the micro-LEDs increases with increasing distance from the top surface of the substrate. When the suspension is first distributed on the substrate, the micro-LEDs may be dispensed relatively quickly before settling onto the substrate surface. Upon reaching the substrate, the micro-LEDs continue to move under the influence of the fluid flow, and thus, as shown in fig. 1, the device with the pillars facing down, as shown in fig. 7A, experiences a torque that tends to reverse direction, causing the electrodes to face down and the pillars to face up. Similarly, if the micro-LED enters the well with the post down (fig. 7B), the post will prevent the disk from being trapped and the force on the disk will tend to push the micro-LED out of the well and flip the direction with the electrode down. If the micro-LEDs are trapped in a well, as shown in fig. 7C, the resultant force from the fluid flow is much less due to the smaller cross-section of the post, and therefore the potential for escape is low. Successful fluid assembly requires proper handling of the micro-LEDs so that their most stable configuration is also bonded to the substrate in the correct position and orientation.

Fig. 8A and 8B are a plan view and a partial cross-sectional view, respectively, of a micro LED subpixel layout. Each micro LED sub-pixel in the display array is driven by a voltage applied to two electrodes arranged in a cross-point matrix of row lines 802 and column lines 804, respectively. In typical flat panel display manufacturing, the row and column interconnect lines are thin films of aluminum or copper with a thickness between 200 and 1500 nm. The amount of light emitted by a given micro LED is controlled by the amount of current supplied by the external driver chip and the resistance of the TFT control circuit (not shown) that is part of the sub-pixel. The key point for manufacturing micro LEDs is that both electrodes on the SM micro LEDs have to be combined with low resistance substrate electrodes to allow the correct amount of current to flow through the micro LEDs. The substrate electrodes are chosen for low resistance and compatibility with the solder layer on the micro-LEDs. In one case, the substrate electrode is 200 to 1000nm thick copper to form a copper-tin intermetallic compound with the tin-based solder layer. Of course, the opposite arrangement, with solder on the substrate electrodes and gold electrodes on the micro LEDs, is also possible. As can be seen in fig. 8B, successful fluid assembly requires that the diameter of the micro-LEDs be smaller than the diameter of the wells so that the micro-LEDs can be captured and bonded to the substrate electrodes.

Fig. 9A to 9E are partial cross-sectional views depicting alignment of micro LEDs in an exemplary well (well) variation. Fig. 9A depicts the well diameter being slightly larger than the micro LED diameter, which facilitates alignment and bonding. In fig. 9B, the wells are too small to result in unfavorable alignment and bonding, thereby preventing electrical contact between the micro-LEDs and the substrate. In fig. 9C, the well diameter is too large to allow the LED electrodes to cause a short circuit between the row and column substrate electrodes.

All of these dimensions are a result of the control of dimensions through reticle design, film thickness and photoresist exposure using relatively conventional photolithography processes. The deposition thickness for the build-up is selected to match the depth of the mesa etch (see fig. 6B), which defines the central active (light emitting) region, so the target thickness must be determined by measuring the etch depth. The GaN etch is performed in a single wafer etch chamber, so the etch rate may differ by 10-20% between successive wafers. In addition, the etch rate is not completely uniform across the wafer, with as much as 10-15% variation from center to edge. As a result, for an etch nominally targeted at 1 micron, the center mesa (Z)_MESA) May be as high as 400 nm. Deposition of the deposited metal is typically accomplished by evaporation or sputtering, typically many wafers are processed together in a batch process, so individual deposition thicknesses for each wafer are not feasible. For this case, the target thickness of the build-up deposition is chosen to be Z for all wafers, regardless of the above-described etch differences_MESAAverage and the result is that the thickness of the stack is too great for some wafers and too thin for others. The final structure N-pad (electrode connecting the N + semiconductor) and P-pad (electrode connecting the P + semiconductor) may not be on the same plane due to variations in GaN etching and deposition of the deposited metal. This difference can vary from one micro LED to another and can be as much as 600nm, which can have a significant negative impact on the yield and reliability of the electrical connections between the micro LEDs and the substrate contacts.

In FIG. 9D, the N-pad of the peripheral micro-LED is too thick, so the center electrode (P-pad) of the micro-LED does not electrically contact the substrate because the heights of the N-pad and P-pad are not coplanar. The result is a darkening of the pixel due to improper control of the electrode planarity. In contrast, in FIG. 9E, the N-pad on the perimeter is too "low" relative to the center electrode, resulting in incomplete contact of the electrode with the electrical interface of the mating substrate. The tilted micro-LEDs result in the contact between the N-pad and the substrate electrode being confined to a small area, rather than the entire perimeter. Small area contacts increase series resistance and reduce the reliability of the electrical connection. To prevent the described alignment and bonding failure mechanisms, it would be advantageous to fabricate the micro-LEDs in such a way that the P-pad and N-pad electrodes are always at the correct relative coplanar height to achieve optimal contact with the substrate electrodes.

Fig. 10A-10C are partial cross-sectional views of a substrate well and a mating micro LED showing a well bottom surface pad. The light emitting display substrate 1000 comprises a support substrate 1001 with a flat top surface 1002 and an LED cross point control matrix comprising an array of column and row conductors. Since only one LED is shown, there is only one pair of column and row lines, shown at 804 and 802, respectively, in fig. 8A. The active and passive matrix systems are specifically explained in prior family application U.S. patent 9,825,202, which is incorporated herein by reference. As described in the background section above, light emitting display substrates typically include millions of LEDs. A first membrane layer 1008 overlies the support substrate top surface 1002. Again, only a single well 1010 is shown. Each well 1010 has a convex bottom surface, indicated by reference numeral 1012, with the bottom surface having a first substrate electrode 1014 connected to a corresponding column line (804, see fig. 8A) and a second substrate electrode 1016 connected to a corresponding row line (802, fig. 8A).

Second membrane layer 1018 is interposed between support substrate top surface 1002 and first membrane layer 1008. As shown in fig. 10B and 10C, the second thin film layer 1018 may be composed of a TFT layer 1018a containing Thin Film Transistors (TFTs), not shown, and interconnected to a row and column wiring for the purpose of enabling the LED operation. The second thin film layer 1018 may also be formed of some oxide or insulating layer, such as a first oxide layer 1018b and a second oxide layer 1018 c. A spacer 1020 is interposed between the support substrate top surface 1002 and the second thin film layer 1018, below the bottom of each well. The spacer 1020 may be an insulating material, as shown in fig. 10A, or an electrical conductor, as shown in fig. 10B and 10C. The first thin-film layer wells 1010 each have a diameter 1022 or cross-section (in the case of a non-circular LED). Shim 1020 has a width 1024 less than diameter 1022 and a top surface 1026. The convex bottom surface 1012 of the well is due to the difference in height between the top surface 1026 of the spacer and the top surface 1002 of the support substrate.

As shown in all examples, the first substrate electrode 1014 is a central substrate electrode having a first electrical interface surface 1028 for electrically connecting the micro-LEDs, and the second substrate electrode 1016 is a peripheral substrate electrode having a second electrical interface surface 1030, lower than the first electrical interface surface, which is defined relative to the support substrate top surface 1002, also for electrically connecting the micro-LEDs. As best shown in fig. 10B and 10C, the pads are formed directly on the column lines, forming column interconnect pads 1020. The first substrate electrode 1014 is a center substrate electrode overlying the via 1032 and connects to the column interconnect pad 1020.

Several methods may be used to match the micro LED electrodes to electrical interface structures on the display substrate to facilitate solder bonding. Additional spacer structures may be added to the substrate below the center substrate electrode to elevate it above the outer ring substrate electrode by the thickness of the spacer layer, as shown. The spacers may be made of metal films used elsewhere for interconnects, such as aluminum or copper, or of insulating layers and may be 50 to 500nm thick. If the spacer is conductive, it is isolated from the center substrate electrode by an interlayer dielectric as shown. Alternatively, the center and edge substrate electrodes may be fabricated separately with layers having different thicknesses. The result is that the center and edge electrodes are no longer coplanar and the height difference is D_sub＝Z_C-Z_E(FIG. 10A). It can be seen that when the electrode height D is_LED＝Z_P-Z_NIs equal to D_SUBThe substrate electrode structure is best matched with the micro-LED. Thus, such a configuration may be found at D_LED<D_SUBIn any case compensate for the "low" P-pad (center) electrode, but at the cost of increased complexity and variability. Of course, for an electrode having a "high" P-pad (D)_LED>0) This structure will have lower performance and result in a reduced contact area, as shown in fig. 9E.

The spacer may be fabricated in various ways as long as the height of the substrate electrodes is typically 50 to 500nm and the height difference is suitable for interfacing with the micro-LEDs. In the case of an active matrix display (e.g., fig. 10B), micro LED wiring is constructed on the layers used to fabricate the TFTs (not shown). The micro LED wiring consists of metal interconnects arranged in rows and columns, which connect to substrate interface electrodes. The row and column interconnect lines are typically copper or aluminum with a line thickness of 100 to 900 nm. Thus, since the metal layers are separated by an insulating layer (typically silicon oxide), the electrode connections can pass each other without shorting. In fig. 10B, a first oxide layer 1018B separates the column and row interconnect lines (804 and 802, see fig. 8A), while a second oxide layer 1018c separates the column interconnects and the first substrate electrodes, and the connections between the layers are made by appropriately placed vias. In fig. 10B, the spacer located below the center substrate electrode is made of the same metal as the metal film used to make the column interconnection line, and thus the center substrate electrode is lifted by the thickness of the film. In fig. 10C, an alternative strategy is used in which the height of the central substrate electrode is increased by the thickness of the first oxide layer and the column interconnect layer.

Using the above-described spacer, a micro LED with a "high" perimeter electrode, as shown in fig. 9D, can be successfully matched to the convex well-bottom structure shown in fig. 10A, 10B, and 10C. However, even if the center and perimeter electrodes of the micro-LEDs are planar, as shown in fig. 9A, or the micro-LED center electrode is "higher" than the perimeter electrode, as shown in fig. 9E, the micro-LED electrodes will be able to connect with the substrate electrode, but at the expense of higher current resistance and reduced contact area.

A simpler and more efficient method to fabricate micro-led electrodes with equal (co-planar) substrate interface surfaces is disclosed in more detail herein. To avoid tolerance issues associated with etching portions of the MOCVD stack first and then depositing and patterning thin films, the inherently co-planar MOCVD stack is advantageously used as a mechanical assembly to lift the N-pad electrode to the same height as the P-pad, ensuring D _LED0. MOCVD growth of GaN and AlGaInP is a heteroepitaxial process in which the crystal structure is built up layer by layer from a base structure as a template. Unlike the physical deposition process described above, the physical deposition process usually results in topological changes due to grain growth, which is heterogeneousSuccess has resulted in its surface being locally (less than or equal to the micro LED diameter) flat (planar) within at most a few atomic layers. Similarly, the insulating layer, typically silicon dioxide deposited by plasma enhanced chemical vapor deposition, is smooth and locally (as defined above) planar. Thus, the fourth plane of the substrate used as the surface mount electrode has substantially lower variability, typically less than 10 nanometers. The surface mount electrodes with low melting point solder as described above are deposited on the fourth plane and the final electrode interface surface is on the same fifth plane. The overall variability in electrode deposition thickness can result in micro-LEDs of different thicknesses, but when considered locally, the two surface mount electrode interface surfaces of all micro-LEDs are on the same (fifth) plane. Unlike CVD processes, Physical Vapor Deposition (PVD) of metals can result in solder surfaces having some roughness due to agglomeration and grain growth. Therefore, the surface roughness of the final surface may be about 10 to 100 nm. In view of this potential surface roughness, the micro LED electrode interface surface can be said to have an average fifth plane tolerance of 10 nm. Due to the manufacture of the micro LED, the LED_LEDIs always zero, so the shim structure of fig. 10 has no advantage, and with reference to fig. 10, D may be used_SUBThe display substrate was manufactured at 0.

Fig. 11A to 11D are a plan view, two partial sectional views and a perspective view, respectively, of a planar SM center-emitting μ LED. The center emitting μ LED1100 includes a first doped semiconductor 1102 formed as a substrate and doped with an n or p dopant. As shown in fig. 11A and 11C, the first doped semiconductor 1102 substrate in this example has a circular perimeter, but is not limited to any particular shape. The first doped semiconductor 1102 has a top surface formed in a first plane 1104, the first plane 1104 including a central mesa 1102a (distinguished by a dashed line) separated from a perimeter 1102b (distinguished by a separate dashed line). The MQW layer 1106 (typically formed as several sublayers) has a top surface formed in a second plane 1108 that covers the first doped semiconductor central mesa 1102a and the periphery 1102 b. A second doped semiconductor 1110 doped with an opposite dopant from that used in the first doped semiconductor 1102 is formed as a layer having a top surface in a third plane 1112 above the MQW layer 1106.

The electrical insulator has a first portion 1114a formed as a layer having a top surface in the fourth surface 1116 of the second doped semiconductor 1110 and a second portion 1114b covering the perimeter trench valleys 1118 dividing the perimeter 1102 b. The key function of the insulator is to prevent current leakage between the first and second doped semiconductors. The first electrode 1120 overlies the central platform, connects to the second doped semiconductor 1110 through the central via 1124, and has a substrate interface surface in the fifth plane 1122. The second electrode has a first portion 1126a formed over the perimeter trench valley 1118 and connects the first doped semiconductor 1102 through a perimeter via 1128. The second electrode has a second portion 1126b that overlies the perimeter of the electrically-insulator first portion 1114a and connects to the second electrode first portion and has a substrate interface surface in a fifth plane 1122.

The SM center emitting μ LED1100 also includes a trench 1130 formed in the first doped semiconductor 1102 that separates the central mesa 1102a from the perimeter 1102 b. The groove 1130 and the peripheral groove valley 1118 have top surfaces formed in a sixth plane 1132 that is below the first plane 1104.

In one aspect, the first doped semiconductor 1102 and the second doped semiconductor 1110 are doped GaN. Alternatively, the first doped semiconductor 1102 and the second doped semiconductor 1110 are p-doped gallium phosphide (p-GaP) or n-doped indium gallium phosphide (n-GaInP). Technically, the doped semiconductors may also be n-GaP and p-GaInP, but are less practical.

Although not explicitly shown, the GaN device may optionally include electron and hole injection and blocking layers, as is known in the art. In the case of GaAs devices, optional p and n cladding layers may be used, as is also well known in the art. In general, it is desirable to maximize the residence time of electrons and holes in the MQW layer for both red and blue micro LEDs. Considering only the anode side, for example, it is desirable to prevent electrons from leaving, so the electron blocking layer (AlGaN) has a high barrier to electrons in the conduction band. It is also desirable that holes enter easily, so a separate hole injection layer can be added on top of the electron blocking layer to eliminate small discontinuities in the valence band. In the case of AlGaInP, the n and p cladding layers have the same purpose, but for historical reasons they are referred to as windows and cladding layers. As shown, the SM center emitting μ LED1100 may include a plurality of first doped semiconductor perimeter segments 1102b separated by a plurality of perimeter trench valleys 1118. In that case, MQW layer 1106, second doped semiconductor 1110 and electrical insulator first portion 1114a cover each first doped semiconductor perimeter segment 1102 b. A second electrode first portion 1126a is formed over each peripheral trench valley 1118 and connects to the first doped semiconductor 1102 through a corresponding peripheral via 1128. Second electrode second portion 1126b overlies a segmented perimeter of electrically insulator first portion 1114a and has a substrate interface surface in fifth plane 1122.

The first doped semiconductor 1102, the MQW layer 1106 and the second doped semiconductor 1110 form an etch stack having a height 1134 orthogonal to the first 1104, second 1108 and third 1112 planes of less than 2 microns and a flatness tolerance of the first, second, third and fourth planes of less than 10 nanometers. As described above, the electrode interface surface in the fifth plane has an average flatness tolerance of less than 10 nm. Rather than relying on the larger tolerances inherent in using a thin film build-up process to form a planar electrode surface, the apparatus described herein uses the pre-existing planar surface of the MOCVD stack, as shown in fig. 6A-6J. Thus, the MOCVD plane can be used to maintain flatness between substrate interfaces of finally formed electrodes even if there is a difference in stack etching between chips on a wafer or between wafers. Briefly, the micro LED1100, as well as the

micro LEDs

1300 and 1400 presented below, can be described as a device in which electrodes are formed on an etched MOCVD wafer (i.e., an etch stack) without an intervening semiconductor layer being subsequently deposited.

In one aspect, not shown, the solder layer forms part of the first and second electrode interface surfaces and is made of an alloy such as indium/tin (In/Sn) or gold/germanium (Au/Ge). Alternatively, the substrate interface surfaces of the first and second electrodes are gold. Optionally, as shown, a navigation keel or post 1136 is attached to first doped semiconductor base bottom surface 1138.

As shown in FIG. 11A, this exemplary center emitter design uses four equally spaced island-like structural support segments of annular N-pad electrodes. One key factor in the design is the co-planarity of the N-pad and P-pad electrodes. Note also that the island (perimeter) structure is electrically inactive and is isolated from the N-pad electrode by an insulator, so the connection to the N-pad electrode is made through 4 contacts spaced between the islands. The number of islands typically ranges from one to six or more, depending on the size of the micro-LED, but at least one opening for contacting the N-doped region is provided in the island structure. Fewer contacts allow more area for solder to contact the substrate electrodes, but increase diffusion resistance in the n-doped layer. Conversely, the more openings between islands, the smaller the resulting area for contact between the micro-LED and the substrate electrode. On the one hand, it has been found that three or four islands/contacts are preferred to achieve the best compromise between series resistance and bond strength.

The process flow of the present invention is similar to the prior art flow set forth above, in that the photo, deposition and lift-off steps associated with N-pad build-up (steps 6 and 7 above) are eliminated, thus reducing cost and complexity in producing micro-LEDs with perfectly coplanar surface mount electrodes. An exemplary process flow for fabricating the presently designed GaN-based micro LEDs is as follows:

1) as described above, the LED stack is deposited on the sapphire wafer by MOCVD. Other substrates, such as SiC or silicon, may be used, but sapphire substrates allow for removal of the μ LEDs from the growth substrate by laser lift-off (LLO). The MQW structure is tuned to produce the desired emission color and the resulting structure has a thickness of between 2 and 7 μm, see also fig. 1A.

2) A current spreading layer is deposited on the p-GaN surface. The composition is typically a thin (10nm or less) NiO_xThe interfacial layer plus a transparent conductive oxide, such as ITO, which may be 100 to 500nm thick.

3) The light emitting region is defined by photolithography and the MOCVD stack is etched to a depth that extends into the n-doped GaN layer, forming a structure referred to herein as an "etch stack".

4) The area of the μ LED is defined by photolithography and etching the entire stack down to the sapphire substrate.

5) An insulating layer, typically of Plasma Enhanced CVD (PECVD) silicon dioxide (SiO) with a thickness of 100 to 400nm₂) Deposited to prevent current leakage across the device.

6) Contacts corresponding to the p-GaN and n-GaN regions are opened in the insulating layer.

7) Photolithographic patterns are formed to prevent metal deposition outside the N-pad and P-pad contact areas, and a metal stack is deposited to connect the μ LED contact holes.

a. The first metal layer is selected to adhere to the oxide and the work function is matched to n-doped GaN. A typical material is Cr 10 to 50nm thick.

b. The next metal is chosen as a conductive barrier between the adhesion layer and the solder material and can be Cr/Au or Ti/Ni with a total thickness of 100-200 nm.

c. The top layer is a low melting point solder that can bond the substrate electrodes. One system is a tin alloy for solder melting temperatures. Another metal system is Au/Ge.

d. Alternatively, the micro-LEDs may receive only the metal from steps 7a and 7b, and a low melting solder may be formed on the display substrate electrodes.

8) The excess metal is removed by a lift-off process.

9) The finished wafer top surface was bonded to a temporary carrier by an adhesive layer and the sapphire growth wafer was removed by LLO.

10) Now, the μ LEDs are bottom side up on the carrier wafer in a planar array suitable for further processing.

11) Optionally, the n-GaN can be etched to reduce the thickness of the μ LED.

12) A post (navigation keel) structure for fluid assembly is optionally fabricated on the bottom surface near the center of the μ LED. The pillars may be cylindrical, conical, or concave in shape, with the height and diameter of the pillars selected to facilitate orientation of the bottom side of the μ LED upward during fluid assembly.

13) Finally, the complete μ LED is collected in suspension by dissolving the binder using a suitable solvent.

Since the red LEDs are fabricated in different MOCVD processes, the process flow is modified for GaAs based devices. The shape of the device and the location of the electrodes and pillars are similar to those of GaN devices, but the thickness of the device may be different. An exemplary process flow proceeds as follows:

1) as described above, the LED stack is deposited on a GaAs wafer by MOCVD. The MQW structure is tuned to produce the desired emission color and the thickness of the resulting structure is between 5 and 10 μm. See also fig. 2A.

2) Alternatively, the p-GaP may be etched to reduce the thickness of the stack.

3) The top surface of the completed wafer is bonded to a glass or sapphire temporary substrate via an adhesive layer, and the GaAs growth wafer is removed by wet etching.

4) The area of the μ LED is defined by photolithography and the entire stack is etched.

5) The light emitting region is defined by photolithography and the MOCVD stack is etched to a depth that extends into the p-doped GaP layer, forming an etch stack.

6) A metal layer such as Cr/Au is deposited over the p-GaP region matching the workfunction of the layer.

7) A metal layer such as Ti/Au is deposited over the n-GaP region matching the workfunction of the layer.

8) Depositing an insulating layer, typically 100 to 400nm thick of PECVD SiO₂Is deposited to prevent current leakage across the device.

9) Contacts corresponding to the p-GaP and n-GaP regions are opened in the insulating layer.

10) Photolithographic patterns are formed to prevent metal deposition outside the N-pad and P-pad contact areas, and a metal stack is deposited to connect the μ LED contact holes.

a. The first metal is chosen as a conductive barrier between the adhesion layer and the solder material, which may be Cr/Au or Ti/Ni with a total thickness of 100-200 nm.

b. The top layer is a low melting point solder that can bond to the substrate electrodes. One system is a tin alloy used to lower the melting temperature of solder. Another suitable low melting point metal system is Au/Ge. Alternatively, the solder layer may be formed on the substrate electrode.

11) Excess metal is removed by a lift-off process.

12) The finished top wafer surface is bonded to a temporary wafer with an adhesive layer and the first temporary substrate is removed by dissolving the first adhesive.

13) Now, the μ LEDs are bottom side up on the temporary wafer in a planar array suitable for further processing.

14) Optionally, the n-GaP may be etched to reduce the thickness of the micro LED.

15) The post structure for fluid assembly is optionally fabricated at the bottom near the center of the micro LED. The posts may be cylindrical, conical, or concave in shape, with the height and diameter of the posts selected to facilitate the bottom-up orientation of the micro-LEDs during fluid assembly.

16) The completed micro-LEDs are collected in a suspension by dissolving the second binder using a suitable solvent.

Fig. 12 is a graph showing the relationship between flux and efficiency as a function of current density. One of the most important advantages of miniature LED displays is that inorganic LEDs can achieve very high brightness, which enables flexibility in matching the light emitting properties of the display to the specific resolution and brightness requirements of the product. A small wearable display may only require 150 plus 200 nits (candela per square meter) brightness, while a television may be 500 plus 1500 nits, and an outdoor Public Information Display (PID) may be 2000 plus 4000 nits. The resolution of small displays for cell phones or tablets may exceed 600 pixels per inch (ppi), while the resolution of large PID displays may be only 20 to 60ppi, and thus the available area for each micro LED is quite different. For a 440nm (blue) emitting GaN micro-LED, the luminous flux from the micro-LED is an approximately linear function of current density over a relatively wide range, as shown in fig. 12. Therefore, the micro LED display adjusts the gray scale intensity by controlling the current supplied to each sub-pixel.

The electro-optical conversion efficiency (light output/electrical power) of micro-LEDs peaks at a relatively low flux,and then gradually decreases (falls) over a wide range of applied currents. For display operation, it is desirable to operate near the peak of efficiency to minimize waste heat dissipated in the display. However, very low currents are difficult to adjust, and therefore the optimum current density for a given display depends on a number of factors. Common illumination LEDs operate at high current densities of about 70 amps per square centimeter (a/cm2) to maximize the light output of each device, thereby minimizing the cost per bulb. Micro LED displays typically operate at lower current densities for higher reliability and lower heat dissipation, and thus may operate in the range of 1 to 30A/cm²In the meantime. Other factors that influence the micro-LED configuration selection include the efficiency of each colored micro-LED, the color gamut requirements, and the sensitivity of the green-centered human visual system. It would therefore be advantageous to have a structure that allows the adjustment of the micro-LED light emitting area to balance performance requirements while maintaining fixed micro-LED characteristics, such as pillar height, thickness and diameter, which are critical for high throughput fluid assembly.

Fig. 13A and 13B are a plan view and a partial sectional view depicting a planar SM peripheral light emission μ LED, respectively. The perimeter emitting μ LED1300 includes a first doped semiconductor 1302 formed as a substrate and doped with an n or p dopant. The first doped semiconductor 1302 has a top surface formed in a first plane 1304 that includes a central mesa 1302a spaced apart from a perimeter 1302 b. As shown in fig. 13A, the first doped semiconductor substrate is circular, but other well-known geometries are possible. A MQW layer 1306 having a top surface is formed in a second plane 1308 covering the first doped semiconductor central mesa 1302a and the perimeter 1302 b. A second doped semiconductor 1310 doped with a dopant opposite to the dopant used for the first doped semiconductor 1302 has a top surface in the third plane 1312 overlying the MQW layer 1306.

The electrical insulator 1314 is formed as a layer having a top surface in a fourth plane 1316 overlying the second doped semiconductor 1310. A first electrode 1318 overlies the central mesa 1302a and is connected to the first doped semiconductor 1302 by a central via 1320. The first electrode 1318 has a substrate interface surface in a fifth plane 1322. A second electrode 1324 covers the perimeter of the electrical insulator 1314 and is connected to the second doped semiconductor 1310 by a perimeter via 1326. The second electrode 1324 has a substrate interface surface in a fifth plane 1322. A trench 1328 is formed in the first doped semiconductor 1302, the trench 1328 separating the central mesa 1302a from the perimeter 1302 b. The trench has a top surface formed in a sixth plane 1330 below the first plane 1302. In one aspect, the first doped semiconductor 1302 and the second doped semiconductor 1310 are doped GaN. Alternatively, the first doped semiconductor 1302 and the second doped semiconductor 1310 are p-doped p-GaP or n-doped n-GaInP. The first doped semiconductor central mesa 1302a, the MQW layer 1306, and the second doped semiconductor 1310 form an etched stack having a height 1332 perpendicular to the first plane 1304, the second plane 1308, and the third plane 1312 of less than 2 microns and a flatness tolerance to the first, second, third, and fourth planes of less than 10 nanometers. The average flatness tolerance of the electrode interface surface in the fifth plane is also less than 10 nm.

In one aspect, not shown, the solder layer forms part of the interface surface of the first and second electrodes and is made of an alloy such as In/Sn or Au/Ge. Alternatively, the substrate interface surface of the first and second electrodes is gold. Optionally, as shown, a navigation keel or post 1336 is attached to the first doped semiconductor base bottom surface 1336.

The center light emitter described above and shown in fig. 11A and 11C includes: the light emitting area is 10% to 15% of the total surface area of the disc-shaped micro LEDs, wherein the surface area of the micro LEDs is parallel to the first, second and third planes. As shown in fig. 13A-13B, the structure can be modified such that the light emitting area is an outer ring structure covered by P-pad, while the central island (mesa) is the mechanical support for the N-pad electrode. In this aspect, the light emitting area may be about 50% of the micro LED disk surface area. The advantage of this configuration is that the continuous P-pad electrode is not interrupted by contact holes, thus allowing a full 360 degree circular contact with the substrate interface electrical contact. In this structure, a trade-off is made between diffusion resistance, which is reduced by increasing the center contact area, and reducing the area of the mesa, which keeps the solder in contact with the substrate electrode.

Fig. 14A and 14B are a plan view and a partial sectional view, respectively, of a planar SM full-area light emission μ LED. The full-area light emitting μ LED1400 includes a first doped semiconductor 1402 formed as a substrate and doped with an n or p dopant. Although the first doped semiconductor substrate is depicted as circular, it is not limited to any particular geometry. The first doped semiconductor 1402 has a top surface formed in a first plane 1404 that includes a mesa. The MQW layer 1406 has a top surface formed in a second plane 1408 overlying the first doped semiconductor mesa. A second doped semiconductor 1410 doped with a dopant opposite to the dopant used in the first doped semiconductor is formed as a layer having a top surface in a third plane 1412 overlying the MQW layer 1406. An electrical insulator having a first portion 1414a is formed as a layer having a top surface in a fourth plane 1416 overlying the second doped semiconductor 1410. A second insulator 1414b covers the first doped semiconductor peripheral trench valley 1418.

The first electrode 1420 overlies the mesa and connects to the second doped semiconductor 1410 through a mesa via 1423. The first electrode 1420 has a substrate interface surface in the fifth plane 1422. The second electrode has a first portion 1424a covering the peripheral trench valley 1418. The second electrode has a first portion 1424a covering the peripheral trench valley 1418 and is connected to the first doped semiconductor 1402 through a peripheral via 1426. The second electrode second portion 1424b is formed to cover the perimeter of the electrical insulator first portion 1414a having a substrate interface surface in the fifth plane 1422. The first doped semiconductor perimeter trench valley 1418 has a top surface formed in a sixth plane 1428 that is below the first plane 1408.

In one aspect, the first doped semiconductor 1402 and the second doped semiconductor 1410 are doped GaN. Alternatively, the first doped semiconductor 1402 and the second doped semiconductor 1410 are p-doped p-GaP or n-doped n-GaInP. As shown, the SM full-area light emitting μ LED may include a plurality of first doped semiconductor peripheral trench valleys 1418. In that case, a second electrode first portion 1424a is formed on each peripheral trench valley 1418 and connected to the first doped semiconductor 1402 through a corresponding peripheral via 1426. The second electrode second portion 1424b overlies a peripheral portion of the electrical insulator first portion 1414a having a substrate interface surface in the fifth plane 1422.

The first doped semiconductor 1402, the MQW layer 1406, and the second doped semiconductor 1410 form an etch stack having a height 1430 orthogonal to the first plane 1404, the second plane 1408, and the third plane 1412 of less than 2 microns and having flatness tolerances of the first, second, third, and fourth planes of less than 10 nanometers. The average flatness tolerance of the electrode interface surface in the fifth plane is also less than 10 nm.

In one aspect, not shown, the solder layer forms part of the interface surface of the first and second electrodes and is made of an alloy such as indium/tin (In/Sn) or gold/germanium (Au/Ge). Alternatively, the substrate interface surfaces of the first and second electrodes are gold. Optionally, as shown, a navigation keel or post 1432 is attached to the first doped semiconductor base bottom surface 1434.

Fig. 15A to 15C are plan views comparing light emitting surface areas of micro LEDs of center light emission (fig. 11A), peripheral light emission (fig. 13A), and full-area light emission (fig. 14A). The full emitter design of fig. 14A can be used if a large light emitting area is desired. The active light emitting region is also a mechanically supporting island of the P-pad electrode, thus allowing the openings (3 shown) in the active island (mesa) to be formed to contact the n-GaN region. In this case, the light emitting area is about 75% of the diameter of the micro LED disk. For GaAs based devices, the three-contact geometry is generally more advantageous than the four-contact variant because there is only one thin region on any splitting plane, thus making the mechanical strength of the micro-LED higher. Another advantage of the full light emitting structure is that etching damage to the periphery of the device has less impact on efficiency. This is particularly important for AlGaInP devices where surface recombination due to etch damage can result in a reduction in the luminous efficiency around the perimeter of the LED, limiting the light emission of small micro-LEDs.

The micro LED design described herein is compatible with conventional MOCVD manufacturing and facilitates fluid assembly and integration with surface mount electrodes formed on the same plane. Another benefit of the structure is the flexibility to change the light emitting area from 10% to 75% of the micro-LED area without changing the physical properties (diameter, thickness, sidewall angle and post size) critical to successful fluid assembly.

Fig. 16 is a flowchart illustrating a method for manufacturing an SM μ LED. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily indicate the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence. Generally, however, the method follows the numerical sequence of the depicted steps. The method starts at step 1600.

Step 1602 provides a MOCVD LED structure comprising a growth substrate, a stack overlying the growth substrate comprising a first doped semiconductor having a top surface in a first plane, a MQW layer overlying the first doped semiconductor having a top surface in a second plane, and a second doped semiconductor overlying the MQW layer and having a top surface in a third plane, see fig. 1A and 2A. The first and second doped semiconductors are oppositely doped with n and p dopants. Specific semiconductor materials that can be used are mentioned above.

Step 1604 etches the MOCVD stack to form a plurality of individual chips on the growth substrate. Step 1606 manufactures the μ LEDs from each chip as follows. Step 1606a selectively etches the stack. Step 1606b conformally deposits an electrical insulator to form a top surface on the fourth plane overlying the etch stack. Step 1606c selectively etches to expose the second doped semiconductor, forming a first via. Step 1606d selectively etches to expose the first doped semiconductor to form a second via.

Note that: step 1606d may be performed before step 1606c in some cases, or step 1606d may be performed concurrently after appropriate lithography and patterning. Step 1606e forms a first electrode overlying the first via, connects to the second doped semiconductor through the first via, and has a substrate interface surface in a fifth plane. Step 1606f forms a second electrode overlying the second via, connects to the first doped semiconductor through the second via, and has a substrate interface surface in a fifth plane. In some aspects, steps 1606e and 1606f may be performed in reverse order or concurrently with appropriate photolithography and patterning. Step 1608 separates the fabricated μ LED from the growth substrate.

In one aspect, the method manufactures a center emitting μ LED, in which case selectively etching the stack (step 1606a) includes creating a center mesa stack surrounded by trenches exposing the first doped semiconductor, and a peripheral stack separated by peripheral trench valleys exposing the first doped semiconductor. Conformally depositing an electrical insulator on the etched stack in step 1606b includes forming a fourth plane covering the central platform stack and the peripheral stack.

Selectively etching to expose the second doped semiconductor in step 1606c includes etching a portion of the electrical insulator overlying the central mesa stack to create a first via, and selectively etching to expose the first doped semiconductor in step 1606d includes etching the electrical insulator overlying the peripheral trench valley to create a second via. Then, forming the first electrode in step 1606e includes forming the first electrode overlying the central mesa stack and connecting the second doped semiconductor through the first via. Forming the second electrode in step 1606f includes: forming a second electrode having a first portion formed on the peripheral trench valley, the first portion connected to the first doped semiconductor through a second via, and forming a second portion overlying the electrical insulator formed on the peripheral stack, having a substrate interface surface in a fifth plane.

In another aspect, the method manufactures a peripheral emitting μ LED by selectively etching the MOCVD stack (step 1606a) to create a central mesa stack separated from the peripheral stack by trenches exposing the first doped semiconductor. Conformally depositing the electrical insulator in step 1606b includes forming a fourth plane overlying the central platform stack and the peripheral stack. Selectively etching to expose the second doped semiconductor in step 1606c comprises: a portion of the electrical insulator overlying the perimeter stack is etched to expose the second doped semiconductor. Selectively etching to expose the first doped semiconductor in step 1606d includes: a portion of the electrical insulator and underlying portions of the second doped semiconductor and MQW layer in the central mesa stack are etched to expose the first doped semiconductor. Forming the first electrode in step 1606e can include forming a first electrode overlying the electrical insulator formed on the perimeter stack and connected to the second doped semiconductor through the first via. Forming the second electrode in step 1606f includes forming a second electrode overlying the central mesa stack and connected to the first doped semiconductor through the second via.

In another variation, the method manufactures a full-area light emitting μ LED by selectively etching the MOCVD stack (step 1606a) to form a mesa stack and a peripheral trench valley in the mesa stack to expose the first doped semiconductor. Selectively etching to expose the second doped semiconductor in step 1606c comprises: an electrical insulator is etched covering a portion of the mesa stack to expose the second doped semiconductor. Selectively etching to expose the first doped semiconductor in step 1606d includes etching an electrical insulator covering the peripheral trench valleys. Forming the first electrode in step 1606e can include forming a first electrode overlying the mesa stack and connected to the second doped semiconductor through the first via. Forming the second electrode in step 1606f includes: forming a first portion of a second electrode covering a peripheral trench via connected to the first doped semiconductor through a second via; and forming a second portion overlying the electrical insulator formed at the periphery of the mesa stack and having a substrate interface surface in a fifth plane.

Step 1608, as described above, produces a μ LED having a maximum cross-section of 150 microns coplanar with the first, second, and third planes, a mesa stack (etch stack) height orthogonal to the first, second, and third planes of less than 2 microns, and a flatness tolerance of an average fifth plane of less than 10 nanometers.

Fig. 17 is a flow chart illustrating a method for manufacturing a display substrate having a well bottom surface pad. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily represent the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of a strict order of sequence. In general, however, the method is as described above, and generally follows the numerical sequence of steps presented below.

The method starts in step 1700. Step 1702 provides a support substrate having a flat top surface and an LED cross-point control matrix comprising an array of column and row conductors. Step 1704 forms an array of raised well bottom structures overlying the top surface of the support substrate. Step 1706 forms a first thin-film layer overlying the top surface of the support substrate and the raised well bottom structure. Step 1708 forms a well in the first thin film layer and exposes the convex well floor structure. Step 1710 deposits surface mount micro LEDs in the wells with a fluid.

In one aspect, forming the array of convex well bottom structures in step 1704 includes: for each of the convex well bottom structures, a first substrate electrode electrically connecting the corresponding column line and a second substrate electrode electrically connecting the corresponding row line are formed. On the other hand, prior to forming the first thin film layer, step 1704a forms an array of spacers covering the top surface of the support substrate. The spacers may be of a conductive or insulating material. Step 1704b forms a second thin film layer overlying the array of pads.

In one aspect, forming the array of shims in step 1704a includes forming shims having a width and a top surface. Then, forming wells in the first thin film layer in step 1708 includes forming wells having a diameter (cross-section) greater than the width of the spacers. The convex bottom surface of the well is shaped in response to a height difference between the top surface of the spacer and the top surface of the support substrate.

On the other hand, forming the array of convex well-bottom structures in step 1704 includes additional substeps. Step 1704c forms a central first substrate electrode having a first electrical interface surface for electrically connecting the micro LEDs. Step 1704d forms a peripheral second substrate electrode having a second electrical interface surface defined relative to the support substrate top surface below the first electrical interface surface for electrically connecting the micro LEDs.

In yet another aspect, forming the array of pads in step 1704a includes forming each pad directly overlying (in electrical contact with) a column line, forming a column interconnect pad. Then, forming a second membrane layer in step 1704b includes forming vias in the second membrane layer overlying each column interconnect pad, and forming a center first substrate electrode in step 1704c includes forming a center first substrate electrode overlying the vias and electrically connecting the column interconnect pads.

Depositing the surface mount micro-LEDs in step 1710 typically includes filling the wells with micro-LEDs having a top surface with a central first electrode and a peripheral second electrode and a substrate interface surface connecting the first substrate electrode and the second substrate electrode, respectively. In one aspect, the micro-LEDs have a central first electrode and a peripheral second electrode with coplanar substrate interface surfaces, such as the center emitting, peripheral emitting and full area emitting micro-LEDs described in detail above. Alternatively, the micro-LEDs may have non-coplanar central first electrode and peripheral second electrode substrate interface surfaces, as shown in fig. 9D and 9E.

Planar surface mount micro LEDs and associated manufacturing processes have been shown. Examples of specific semiconductor materials, geometries, and specific process steps have been shown to illustrate the invention. However, the present invention is not limited to these examples. Other variations and embodiments of the invention will occur to those skilled in the art.

Claims

1. A light emitting display substrate, comprising:

a support substrate having a planar top surface and a Light Emitting Diode (LED) cross-point control matrix comprising an array of column and row conductors;

a first thin film layer covering a top surface of the support substrate and including a plurality of wells;

wherein each well has a convex bottom surface, a first substrate electrode connected to a corresponding column conductor, and a second substrate electrode connected to a corresponding row conductor;

the light emitting display substrate further comprises:

a second membrane layer between the top surface of the support substrate and the first membrane layer;

a spacer located between the top surface of the support substrate and the second membrane layer and below the bottom of each well;

the convex bottom surface of the well is due to a height difference between the top surface of the spacer and the top surface of the support substrate.

2. The luminescent display substrate of claim 1, wherein: each well of the first thin film layer has a first diameter;

wherein the shim has a width less than the first diameter.

3. The luminescent display substrate of claim 1, wherein: the gasket is selected from a conductive material and an electrically insulating material.

4. The luminescent display substrate of claim 1, wherein: the first substrate electrode is a central substrate electrode having a first electrical interface surface for electrically connecting micro-LEDs, and the second substrate electrode is a peripheral substrate electrode having a second electrical interface surface defined relative to the top surface of the support substrate, the second electrical interface surface being lower than the first electrical interface surface and being for electrically connecting micro-LEDs.

5. The luminescent display substrate of claim 1, wherein: the spacers directly cover the column conductors to form a column of interconnection spacers;

wherein the second membrane layer includes vias overlying the column interconnect pads; and

wherein the first substrate electrode is a center substrate electrode covering the via and connecting the column interconnection pads.

6. The luminescent display substrate of claim 4, wherein: the light emitting display substrate further comprises:

a plurality of surface mount micro LEDs filling the plurality of wells,

each micro LED has a top surface with a central first electrode and a peripheral second electrode and a substrate interface surface connecting the first substrate electrode and the second substrate electrode, respectively.

7. The luminescent display substrate of claim 6, wherein: the central first electrode and the peripheral second electrode of the micro LED have coplanar substrate interface surfaces.

8. The luminescent display substrate of claim 7, wherein: the surface mount micro LED is selected from micro LEDs with central light emission, peripheral light emission and full-area light emission.

9. The luminescent display substrate of claim 6, wherein: the substrate interface surfaces of the central first electrode and the peripheral second electrode substrate of the micro LED are not coplanar.

10. A method of making a light emitting display substrate, comprising:

providing a support substrate having a planar top surface and a Light Emitting Diode (LED) cross-point control matrix comprising an array of column and row conductors;

forming an array of raised well floor structures overlying a top surface of the support substrate;

forming a first thin film layer covering the top surface of the support substrate and the convex well bottom structure; and

forming a plurality of wells in the first thin film layer, thereby exposing a convex well bottom structure;

forming the array of convex well bottom structures comprises:

forming an array of spacers overlying a top surface of the support substrate prior to forming the first thin film layer; and

forming a second thin film layer overlying the array of pads;

the shape of the convex bottom surface of the well is due to a height difference between the top surface of the spacer and the top surface of the support substrate.

11. The method of claim 10, wherein: forming the array of convex well bottom structures comprises: for each of the convex well bottom structures, a first substrate electrode electrically connecting the corresponding column conductive line and a second substrate electrode electrically connecting the corresponding row conductive line are formed.

12. The method of claim 10, wherein: forming the array of shims comprises forming a shim having a width and a top surface;

wherein forming a plurality of wells in the first thin film layer comprises forming a plurality of wells having a diameter greater than the width of the spacer.

13. The method of claim 10, wherein: forming the array of pads comprises forming the pads from a material selected from electrically conductive and electrically insulating materials.

14. The method of claim 11, wherein: forming the array of convex well bottom structures comprises:

forming a central first substrate electrode having a first electrical interface surface for electrically connecting the micro-LEDs; and

a peripheral second substrate electrode is formed having a second electrical interface surface defined relative to the top surface of the support substrate, the second electrical interface surface being lower than the first electrical interface surface and being for electrically connecting the micro-LEDs.

15. The method of claim 14, wherein: forming the array of shims comprises:

forming each pad directly overlying the column conductor, forming a column interconnect pad;

wherein forming the second thin-film layer comprises forming vias in the second thin-film layer covering each column interconnect pad; and

wherein forming the center first substrate electrode comprises forming a center first substrate electrode overlying the via and electrically connecting the column interconnect pads.

16. The method of claim 10, wherein: the method further comprises: a fluid deposits a plurality of surface mount micro LEDs in the plurality of wells.

17. The method of claim 16, wherein: depositing the plurality of surface mount micro-LEDs includes filling the plurality of wells with a plurality of micro-LEDs having a top surface with a central first electrode and a peripheral second electrode and a substrate interface surface connecting the first substrate electrode and the second substrate electrode, respectively.

18. The method of claim 17, wherein: depositing the plurality of surface mount micro-LEDs includes depositing a micro-LED having a central first electrode and a peripheral second electrode coplanar substrate interface surface.

19. The method of claim 18, wherein: depositing the plurality of surface mount micro-LEDs comprises depositing micro-LEDs selected from center emitting, perimeter emitting, and full area emitting.

20. The method of claim 17, wherein: depositing the plurality of surface mount micro-LEDs includes depositing micro-LEDs having non-coplanar central first electrode and peripheral second electrode substrate interface surfaces.