CN111460754B - Impedance checking method - Google Patents
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- CN111460754B CN111460754B CN201910716538.5A CN201910716538A CN111460754B CN 111460754 B CN111460754 B CN 111460754B CN 201910716538 A CN201910716538 A CN 201910716538A CN 111460754 B CN111460754 B CN 111460754B
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Abstract
A method for impedance inspection. In the wiring software, a rule name of a line segment setting rule is formulated in a predefined format, the rule name comprises a target impedance value, and the line segment setting rule comprises line distance information and line width information of a plurality of lines. And reading the line segment setting rule from the layout design drawing by using extraction software to obtain a plurality of lines to be subjected to impedance calculation. And acquiring a target impedance value from the rule name by using extraction software, and feeding the target impedance value into simulation software. The impedance value of each line is calculated by simulation software, and whether the calculated impedance value of each line is abnormal or not is judged based on the target impedance value.
Description
Technical Field
The present invention relates to an analog method, and more particularly, to an impedance checking method.
Background
As the transmission speed of signals is faster and faster, impedance control has been regarded as the most important loop, and when impedance control of a wiring (layout routing) of a Printed Circuit Board (PCB) is suitable, the reflected energy of the signal is smaller. And the energy loss is small, and the signal quality is good. Therefore, impedance control is particularly important when laying out a printed circuit board to produce a good quality product.
In current technologies, most of the printed circuit boards have impedance control lines, such as antenna traces, universal Serial Bus (USB), mobile Industry Processor Interface (MIPI), high Definition Multimedia Interface (HDMI), clock (Clock), serial Advanced Technology Attachment (SATA), peripheral component interconnect Express (PCI Express, PCIe), and display ports (display ports, DP), which need to be impedance controlled.
The current process of checking impedance is as follows. Software is purchased and then the software vendor is asked to train the employee. After training, the staff also needs time to practice the operation, and the service of impedance checking can be started for the special case of the company after the familiarity of the software is high enough. Before performing the inspection, a large amount of data is prepared, such as listing the line name to be inspected, listing each segment, and listing if there is a serial number. However, since the impedance of each line (net) requires that the determination pass/fail (fail) criteria be different, the target impedance value for each line is also listed to begin the simulation and to generate the report.
The above conventional method has the following problems: the action of impedance checking must be performed by a person familiar with software, and manually collating the line data required for impedance control not only takes a lot of time, but also may cause data omission due to human error.
Disclosure of Invention
The invention provides an impedance checking method, which can be used for carrying out automatic system integration on wiring software and simulation software, and can save manpower and reduce the problem of artificial careless mistakes.
The impedance checking method of the invention comprises the following steps: in wiring software, a rule name of a line segment setting rule is formulated in a predefined format and is stored in a layout design drawing, wherein the rule name comprises a target impedance value, and the line segment setting rule comprises line distance information and line width information of a plurality of lines; using extraction software to read the line segment setting rule from the layout design drawing to obtain a plurality of lines (net) to be subjected to impedance calculation; extracting software is used for obtaining a target impedance value from the rule name of the layout design drawing, and feeding the target impedance value into simulation software; and calculating the impedance value of each line by using simulation software, and judging whether the calculated impedance value of each line is abnormal or not based on the target impedance value.
In an embodiment of the present invention, formulating the rule name of the line segment setting rule in a predefined format further includes: based on the predefined format, the target impedance value is set at a specific location in the rule name and subsequent numbers following the target impedance value are prohibited.
In an embodiment of the invention, the specific position is one of a start position, a middle position and an end position of the rule name.
In an embodiment of the present invention, the method of impedance checking further includes: and in wiring software, sleeving the line with the impedance control requirement into the line segment setting rule.
In an embodiment of the present invention, in the wiring software, after the line with the impedance control requirement is nested into the line segment setting rule, if it is determined that one of the lines violates the line segment setting rule, a notification message is sent.
In an embodiment of the present invention, the step of determining whether the calculated impedance value of each line is abnormal based on the target impedance value includes: setting a target impedance range based on the target impedance value; judging whether the calculated impedance value of each line exceeds a target impedance range; if the calculated impedance value exceeds the target impedance range, judging the corresponding line to be abnormal; and if the calculated impedance value is within the target impedance range, determining that the corresponding line passes the inspection.
In an embodiment of the invention, after determining whether the calculated impedance value of each line is abnormal based on the target impedance value, a result interface is generated, and the result interface is connected with the layout design diagram, so that when a selection instruction is received through the result interface, the layout design diagram is displayed, and a corresponding position is marked in the layout design diagram.
Based on the above, the wiring software of any printed circuit board and any simulation software for calculating impedance can successfully complete the integration of the automation system, thereby avoiding the problem of time waste caused by human intervention in the process of importing the simulation software.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram of a system architecture according to an embodiment of the invention.
Fig. 2 is a flow chart of a method of impedance checking according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a user interface of a routing software according to an embodiment of the invention.
FIG. 4 is an interface schematic diagram of routing software according to an embodiment of the present invention.
FIG. 5A is a schematic diagram of a results interface according to one embodiment of the invention.
FIG. 5B is a diagram of a layout design according to an embodiment of the present invention.
Description of reference numerals:
110: wiring software
120: extraction software
130: simulation software
S205, S210, S215, S220: method steps for impedance inspection
310. 410: constraint rule checker
510: results interface
511: result options
520: layout design drawing
521: position of
Detailed Description
FIG. 1 is a block diagram of a system architecture according to an embodiment of the invention. In the present embodiment, the system architecture for implementing the method for impedance checking includes a wiring software 110, an extraction software 120, and a simulation software 130.
The embodiment is implemented by an electronic device with computing capability. The electronic device includes a processor, a storage device, and the like. The storage device stores wiring software 110, extraction software 120, and simulation software 130, and the processor drives the wiring software 110, the extraction software 120, and the simulation software 130 to implement the impedance checking method.
The Processor may be implemented by a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Physical Processing Unit (PPU), a programmable Microprocessor (Microprocessor), an embedded control chip, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or other similar devices. The storage device is any form of fixed or removable Random Access Memory (RAM), read-Only Memory (ROM), flash Memory (Flash Memory), secure Digital Card (SD), hard disk, or other similar device or combination of these devices.
Fig. 2 is a flow chart of a method of impedance checking according to an embodiment of the invention. Referring to fig. 1 and fig. 2, in step S205, a rule name of a line segment setting rule is formulated in a predefined format in the wiring software 110, and the line segment setting rule is stored in a layout drawing (board file). For example, rule naming is set for a line segment using a constraint rule checker in accordance with a predefined format. The line segment setting rule can limit line distance information and line width information of a plurality of lines. Here, the predefined format is used to define the target impedance value to be included in the rule name. In one embodiment, the routing software 110 sets the target impedance value to a specific location in the rule name based on a predefined format and prohibits subsequent numbers after the target impedance value to avoid the extraction software 120 identifying errors. The specific position is one of a start position, a middle position and an end position of the rule name. For example, taking the target impedance value as 85 ohms, the rule name "85ohm _PCIE" conforms to the predefined format, and the rule name "852_PCIE" does not conform to the predefined format.
FIG. 3 is a schematic diagram of a constraint rule checker of routing software in accordance with one embodiment of the present invention. Referring to fig. 3, the constraint rule checker 310 includes a plurality of segment setting rules (e.g., PCS) and rule names corresponding to the segment setting rules, and target impedance values are input into initial positions of the rule names. For example, the target impedance value of the rule name "83OHM _ [ B ]4=" is 83 OHMs, and no number is continued after the target impedance value "83". In addition, the target impedance value of the rule name "85OHM _ [ a ]3=" is 85 OHMs.
In other embodiments, the target impedance value may be set to start at the middle position of the rule name, for example, the 4 th character, or may be set to start at the end position of the rule name.
During wiring, the wiring software 110 inserts the line with the impedance control requirement into the line segment setting rule. After the line is sleeved into the line segment setting rule, if the line violates the sleeved line segment setting rule, a notification message is sent. For example, the constraint rule checker may correct and check whether the layout complies with the line segment setting rule, and when the route does not comply with the line segment setting rule, the notification information is displayed.
After the placement plan is completed by the routing software 110, the relevant information can be obtained from the placement plan by the extraction software 120. That is, in step S210, the extraction software 120 is used to obtain a plurality of lines to be subjected to impedance calculation from the layout. In step S215, the extraction software 120 is used to obtain a target impedance value from the rule name of the layout design, and the target impedance value is fed to the simulation software 130.
FIG. 4 is a schematic diagram of an interface of the routing software according to an embodiment of the present invention. In the constraint rule checker 410 of fig. 4, taking the rule name "50OHM (4 OHM) (175)" as an example, the column of the rule name "50OHM (4 OHM) (175)" is expanded to view a plurality of lines a included in the segment setting rule (e.g., NCIs). Accordingly, the extraction software 120 can obtain a plurality of lines a applying the line segment setting rule after reading the rule name "50OHM (4 OHM 5) (175)" of the line segment setting rule. And, based on the rule name, the target impedance value of the line segment setting rule is 50 ohms. By analogy, the extraction software 120 can obtain the lines and the corresponding target impedance values included in each line segment setting rule, and feed the lines and the corresponding target impedance values into the simulation software 130.
Thereafter, in step S220, the impedance value of each line is calculated by the simulation software 130, and it is determined whether the calculated impedance value of each line is abnormal based on the target impedance value.
Specifically, the simulation software 130 sets a target impedance range based on the target impedance value corresponding to each line. For example, assuming a target impedance value of 50 ohms, the target impedance range will be set to within plus or minus 10% of 50 ohms. However, the above description is only for illustrative purposes and is not limited thereto. Next, the simulation software 130 calculates the impedance value of each line according to the layout design diagram, and determines whether the calculated impedance value of each line exceeds its corresponding target impedance range. And if the calculated impedance value exceeds the corresponding target impedance range, judging that the corresponding line is abnormal. Otherwise, if the calculated impedance value is within the corresponding target impedance range, the corresponding line is determined to pass the inspection.
After determining whether the calculated impedance value of each line is abnormal based on the target impedance value, the simulation software 130 may generate a result interface, and connect the result interface with the layout design diagram, so as to display the layout design diagram and mark a corresponding position in the layout design diagram when receiving the selection instruction through the result interface.
FIG. 5A is a schematic diagram of a results interface according to one embodiment of the invention. FIG. 5B is a diagram of a layout design according to an embodiment of the present invention. Referring to fig. 5A and 5B, after the result interface 510 is generated, the result interface 510 is connected to the layout design 520. So as to switch to the corresponding position in the layout design 520 when receiving the selection instruction through the result interface 510. Taking result option 511 of fig. 5A as an example, when a selection instruction is received through result option 511 of result interface 510, layout 520 of fig. 5B is displayed, and a corresponding position 521 is marked in layout 520.
In summary, the above embodiments can be applied to any wiring software and any simulation software for simulating impedance calculation. And establishing a predefined format to formulate a rule name, so that the rule name has significance, and developed extraction software can identify the rule name and effectively extract data. Moreover, since the data is extracted from the layout design diagram, any line name for impedance control is extracted, thereby greatly reducing the omission (such as name filling error) or omission during manual filling. In addition, the above embodiments do not relate to or define any way of calculating the impedance, and therefore, any third-party impedance calculation simulation software may be used. By the embodiment, any wiring software and any simulation software can successfully complete the integration of the automation system, and time waste caused by interruption due to human intervention in the process is avoided.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (6)
1. A method of impedance inspection, comprising:
in a wiring software, formulating a rule name of a line segment setting rule by a predefined format and storing the line segment setting rule into a layout design drawing, wherein the rule name comprises a target impedance value, and the line segment setting rule comprises line distance information and line width information of a plurality of lines;
reading the line segment setting rule from the layout design drawing by using extraction software to obtain a plurality of lines to be subjected to impedance calculation;
obtaining the target impedance value from the rule name of the layout design drawing by using the extraction software, and feeding the target impedance value into a simulation software; and
calculating an impedance value of each of the plurality of lines using the simulation software, and determining whether the calculated impedance value of each of the plurality of lines is abnormal based on the target impedance value,
wherein the rule name for formulating the line segment setting rule in the predefined format further comprises:
based on the predefined format, the target impedance value is set at a specific location in the rule name and consecutive numbers following the target impedance value are prohibited.
2. The impedance inspection method of claim 1, wherein the specific location is one of a start location, a middle location and an end location of the rule name.
3. The method of impedance inspection according to claim 1, further comprising:
in the wiring software, the plurality of lines with the impedance control requirement are nested into the line segment setting rule.
4. The method of claim 3, wherein the step of nesting the plurality of lines with impedance control requirements into the line segment setting rule in the routing software further comprises:
if one of the lines is determined to violate the segment setting rule, a notification message is sent.
5. The method of impedance checking according to claim 1, wherein the step of determining whether the calculated impedance value of each of the plurality of lines is abnormal based on the target impedance value comprises:
setting a target impedance range based on the target impedance value;
judging whether the calculated impedance value of each line exceeds the target impedance range or not;
if the calculated impedance value exceeds the target impedance range, determining that the corresponding line is abnormal; and
if the calculated impedance value is within the target impedance range, the corresponding line is judged to pass the inspection.
6. The method for impedance checking according to claim 1, wherein after the step of determining whether the calculated impedance value of each of the plurality of lines is abnormal based on the target impedance value, further comprising:
and generating a result interface, connecting the result interface with the layout design drawing, displaying the layout design drawing when a selection instruction is received through the result interface, and marking a corresponding position in the layout design drawing.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108100248A TWI732167B (en) | 2019-01-03 | 2019-01-03 | Method of checking impedance |
| TW108100248 | 2019-01-03 |
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| CN111460754A CN111460754A (en) | 2020-07-28 |
| CN111460754B true CN111460754B (en) | 2023-04-07 |
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| TWI831584B (en) * | 2023-01-19 | 2024-02-01 | 和碩聯合科技股份有限公司 | Routing layout design device and routing layout design method |
| TWI838128B (en) * | 2023-02-17 | 2024-04-01 | 華碩電腦股份有限公司 | Circuit layout method and device |
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| CN102298090A (en) * | 2010-06-28 | 2011-12-28 | 鸿富锦精密工业（深圳）有限公司 | Signal integrity test system and method |
| TW201217808A (en) * | 2010-10-29 | 2012-05-01 | Inventec Corp | A checking method of the multi layer of the PCB |
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| TW200521451A (en) * | 2003-12-22 | 2005-07-01 | Jet Technology Co Ltd | Detecting and positioning method of circuit board and test mechanism |
| US7089139B2 (en) * | 2004-08-16 | 2006-08-08 | Agilent Technologies, Inc. | Method and apparatus for configuration of automated debug of in-circuit tests |
| TWI281985B (en) * | 2004-12-22 | 2007-06-01 | Inventec Corp | System and method for resistance measuring |
| TW200723970A (en) * | 2005-12-01 | 2007-06-16 | Inventec Corp | Circuit board layout method |
| TWI445980B (en) * | 2010-06-25 | 2014-07-21 | Hon Hai Prec Ind Co Ltd | Signal integrity testing system and method |
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Patent Citations (4)
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| TW200825813A (en) * | 2006-12-07 | 2008-06-16 | Inventec Corp | A method of establish coupon bar library |
| CN102298090A (en) * | 2010-06-28 | 2011-12-28 | 鸿富锦精密工业（深圳）有限公司 | Signal integrity test system and method |
| TW201217808A (en) * | 2010-10-29 | 2012-05-01 | Inventec Corp | A checking method of the multi layer of the PCB |
| CN106131333A (en) * | 2016-07-04 | 2016-11-16 | 广东欧珀移动通信有限公司 | The control method of a kind of terminal current, speaking circuit and mobile terminal |
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| TWI732167B (en) | 2021-07-01 |
| CN111460754A (en) | 2020-07-28 |
| TW202026917A (en) | 2020-07-16 |
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