CN111448666B - 具有原子级薄沟道的场效应晶体管 - Google Patents

具有原子级薄沟道的场效应晶体管 Download PDF

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CN111448666B
CN111448666B CN201880059759.3A CN201880059759A CN111448666B CN 111448666 B CN111448666 B CN 111448666B CN 201880059759 A CN201880059759 A CN 201880059759A CN 111448666 B CN111448666 B CN 111448666B
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blocks
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thin layer
molding
transistor
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CN111448666A (zh
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托马斯·阿拉瓦
托马斯·恩斯特
韩拯
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Abstract

晶体管的生成，该晶体管的沟道结构包括至少一个带鳍的沟道结构，方法包括：‑从衬底(1)形成模制块(3)，‑在模制块上形成细层(7)，该细层从给定的半导体或半金属材料制成并由二维晶体的一个至十个原子或分子单层构成，‑移除模制块，同时保留细层的在模制块的侧面上延伸的部分(7a)，所述保留的部分(7a)形成鳍，该鳍能够形成晶体管的沟道结构，‑在所述鳍处生成覆盖的栅电极。

Description

具有原子级薄沟道的场效应晶体管
技术领域
本发明涉及通常被称为finFET类型的晶体管的领域，在该晶体管中，沟道结构由至少一个还被称为鳍的柱形成，鳍在具有至少一个栅电极的衬底上延伸，至少一个栅电极可布置在鳍的数个面上和/或围绕鳍的周围分布。
本发明涉及具有一个或多个鳍的晶体管的用途，该一个或多个鳍具有非常小的临界尺寸，尤其是小于10nm(纳米)，本发明尤其可应用于生产设置有这种晶体管且其灵敏度提高的传感器，例如生物传感器或气体传感器。
背景技术
一般而言，一直在寻求减小晶体管的尺寸，尤其是提高其集成密度。
Sujay B.Desai等人在Science 354(2016)99-102上发表的文献“MoS2transistors with 1-nanometer gate lengths(具有1纳米栅极长度的MoS2晶体管)”描述了例如具有大大减小的尺寸且尤其设置有大约1nm的栅极长度的晶体管，该晶体管以纳米管的形式存在。在此处，沟道结构未呈鳍的形式，而是布置在纳米管上的MoS2层。
在寻求减小晶体管的尺寸的同时，还寻求提高晶体管的电性能。
由于finFET型晶体管的带鳍的结构，使得finFET型晶体管尤其能够进行优良的静电沟道控制。
在鳍式晶体管领域中，Chen等人在2014的IEDM上发表的文献“Hybrid Si/TMD 2DElectronic Double Channels Fabricated Using Solid CVD Few Layer-MoS2 stackingfor Vth Matching and CMOS-compatible 3DFETs(将固态CVD少量层-MoS2叠层用于阈值匹配和CMOS兼容的3DFET而制造的混合Si/TMD 2D电子双沟道)”描述了例如呈硅鳍的形式的增强型沟道结构，该硅鳍上覆盖有介于MoS2的3至16个分子单层之间的2D半导体材料薄层。
与薄层2D半导体材料毗邻的这种鳍结构能够获得尤其是针对传导电流而言提高的电性能。
然而，在此处，沟道结构的尺寸基本上取决于硅鳍的尺寸，而硅鳍的尺寸通过由目前可用的光刻方法强制施加。
问题在于：使用具有带鳍的沟道结构且其尺寸进一步减小的晶体管。
发明内容
本发明的目的在于提供一种新的具有一个或多个鳍的晶体管，该一个或多个鳍具有大大减小的临界尺寸，尤其小于10纳米，优选地小于或等于3nm，同时具有良好的电性能。
为此，根据第一实施例，本发明涉及一种用于生成晶体管的方法，在该晶体管中，沟道结构包括一个或多个鳍，该方法包括：
-在衬底上形成一个或多个被称为“模制块”的块，
-在所述一个或多个模制块上形成层，该层基于给定的半导体或半金属材料，该层被称为“薄层”，该薄层由二维晶体的最多十个原子或分子单层或片层构成，
-至少部分地去除所述一个或多个模制块，同时保留薄层的在所述模制块的至少一个侧面上延伸的一个或多个部分，所述一个或多个保留的部分形成一个或多个鳍，该一个或多个鳍适合于形成晶体管的沟道结构，
-在所述一个或多个鳍处生成栅电极。
因此，鳍具有不依赖于光刻方法而是对应于沉积厚度的临界尺寸。
优选地，薄层由二维晶体的一个至五个原子或分子单层构成。
当二维晶体有利地呈单层或单个片层的形式时，该厚度可约为原子或分子的尺寸。
有利地，薄层的给定材料是石墨烯或金属硫族化合物，尤其是MoS2或WS2或WSe2或MoSe2。这种材料适合于生成具有非常高的表面积-体积比同时具有非常良好的电性能的鳍。
形成在鳍上的栅极优选地是周围栅极，周围栅极可围绕鳍的一部分分布在数个不同的平面上。
通常，薄层通过催化生长形成，所述一个或多个模制块基于用于所述给定材料的生长的催化材料。
根据一个用途选项，模制块可由介电材料尤其是SiO2制成。
方法可包括在去除模制块之前，形成一个或多个被称为“保持块”的块，该一个或多个保持块分别位于模制块的一个或多个端部，所述一个或多个保持块适合于在所述一个或多个模制块去除期间确保所述一个或多个鳍的机械强度。
优选地，晶体管的源电极和漏电极实现保持块的功能。
在所述模制块的去除仅是部分去除的情况下，这些块优选地基于介电材料，使得只有薄层和对应的鳍结构执行传导功能。
在部分地去除采用非绝缘材料例如半导体或导电材料的模制块的可选情况下，于是想到这些模制块的尺寸和部分去除，使得模制块不会在其端部处与每个保持块接触。这防止了模制块与源极块和漏极块两者接触。
有利地，源电极和漏电极基于导电材料，然而，所述一个或多个模制块基于适合于相对于所述导电材料被选择性地蚀刻的材料形成。
根据方法的一个用途选项，为了能够在不去除整个薄层的情况下蚀刻模制块，在形成薄层之后且在去除模制块之前，方法可包括如下步骤：
-形成覆盖模制块的掩膜，
-去除掩膜的厚度以暴露模制块的顶部部分。
根据方法的特定用途，其中，栅极是通过形成包括至少一个栅极介电层和至少一个栅极材料层的栅极叠层而生成的周围栅极，方法可进一步包括局部去除周围栅极的一个或多个区域，以暴露所述一个或多个鳍的一个或多个给定区域。
在进行局部去除以去除栅极叠层的区域之后，基于适合于吸收和/或吸附至少一种化学物质的材料的至少一个捕获层可形成在所述一个或多个鳍的暴露的给定区域上。
根据另一方面，本发明涉及一种用于制造化学或生物传感器的方法，该化学或生物传感器设置有至少一个使用如上所限定的方法实现的晶体管。
根据另一方面，本发明涉及一种晶体管尤其是finFET型晶体管，该晶体管包括：
-沟道结构，设置有一个或多个由半导体或半金属材料构成的鳍，该鳍具有二维晶体的一个至十个原子或分子单层，
-围绕所述一个或多个鳍的周围栅电极。
给定材料通常是范德瓦尔斯型材料或二维半导体。
给定材料可以尤其是石墨烯或过渡金属硫族化合物(dichalcogenide)。
有利地，给定材料可由石墨烯的单个单层(或片层)形成，或者甚至由过渡金属硫族化合物的单个单层(或片层)形成。
因此，晶体管可配备有非常薄的鳍，该鳍具有原子或分子中的一个的厚度，同时保持良好的电性能。
晶体管可设置有源电极和漏电极，该源电极和漏电极分别设置在鳍的第一端和第二端，源电极和漏电极基于金属材料。
根据晶体管的实施例，晶体管可形成在衬底上并包括至少第一鳍和至少第二鳍，第一鳍和第二鳍与衬底的主平面平行并朝向不同的方向，第一鳍与第二鳍接触。
对于某些应用，晶体管可设置成使得鳍的一部分由周围栅极覆盖，鳍的另一部分由至少一个捕获层覆盖，捕获层适合于吸收和/或吸附至少一种化学或生物物质。
由于鳍的尺寸，使得晶体管尤其适合于检测小量的化学或生物元素。
因此，根据另一方面，本发明涉及一种化学或生物传感器，该化学或生物传感器设置有一个或多个如上所限定的鳍式晶体管。
附图说明
通过参考附图阅读仅以指明的方式给出而非作为限制的实施例示例的描述，将更清楚地理解本发明，在附图中：
-图1A至图1G和图2A至图2F用于示出用于生成具有鳍的晶体管的方法的示例，该鳍具有大大减小的尺寸并可实现原子或分子的尺寸；
-图3A至图3B用于示出用于生成鳍式晶体管的方法的替代实施例；
-图4示出了finFET晶体管的示例，该晶体管具有大大减小尺寸的鳍并如根据本发明的实施例那样使用；
-图5示出了如根据本发明的实施例那样使用的鳍式晶体管的示例，该鳍式晶体管进一步设置有用于检测气体或生物元素的捕获层；
-图6示出了晶体管的特定示例，该晶体管具有彼此相关并在至少一个接触点接合在一起的正交鳍；
为了使附图更清晰，附图中表示的不同部件不一定根据一致的比例表示。
不同的选项(替代实施例和实施例)应该理解为不是互相排斥的，而是彼此可以组合。
此外，在下文的描述中，与结构的方位相关的术语例如“竖直”、“水平”、“底部”、“侧面”是考虑到该结构如附图中所示那样定向而应用。
具体实施方式
将不会参考图1A至图1G(给出了横向剖视图)和图2A至图2F(其中生成的结构以透视图表示)描述用于生成晶体管尤其是finFET型晶体管的方法的示例，在该晶体管中，如根据本发明的实施例所使用的那样，沟道结构由一个或多个纳米尺寸的鳍形成。
可想到以例如由硅制成的大块半导体衬底作为起始材料。替代地，还可以从由半导体基层(例如，硅)形成的绝缘体上半导体型衬底1开始，基层上覆盖有由介电材料(通常是二氧化硅)制成的绝缘层，绝缘层进而覆盖有表面半导体层。
衬底1可设置有对齐标记，对齐标记例如通过蚀刻未被光敏树脂掩膜保护的部分而形成，或者甚至通过金属沉积然后进行蚀刻而形成。
在衬底1上，生成一个或多个被称为模制块的块3(图1A)，在图2A中示出的特定示例中，模制块是平行六面体形状的长块。在该示例中，数个模制块3根据预定间隔彼此平行地设置，该预定间隔可以例如介于10nm和100μm之间。
块3具有通常介于30nm和100μm之间的临界尺寸Dc1。临界尺寸Dc1可以小于30nm，该尺寸通常对应于由目前可用的光刻方法(尤其是使用电子束(e-beam)的光刻方法)强制施加的极限尺寸。
“临界尺寸”指的是平行于衬底1的主平面测量的图案的最小尺寸。“主平面”限定为穿过衬底1并与附图中给定的正交参考系[O；x；y；z]的平面[O；x；y]平行的平面。
模制块3可例如通过沉积基于材料4的层然后对该材料4进行光刻和蚀刻以限定图案而形成。
替代地，为了生成这些块3，开口形成在掩膜层尤其是光敏树脂掩膜中，然后在掩膜的开口填充材料4。当该掩膜由树脂制成时，通常通过通常被称为“剥离”的剥除方法来去除掩膜。
然后，形成基于半导体材料或半金属的薄层7，半导体材料或半金属优选地为范德瓦尔斯或二维(2D)型，可想到从薄层7生成晶体管的沟道结构。纳米厚度的薄层7通过在模制块3上生长而生成。“纳米”指的是小于10纳米的厚度。
通常，薄层7具有小于3nm的厚度。
薄层7尤其由晶体状二维材料(2D)(例如，石墨烯)的1个至10个原子单层构成，或者由基于硫族化物和过渡金属的材料的二维材料(2D)的1个至10个分子单层构成。
“原子单层”指的是片层(在其它方面被称为层)，其中，厚度由单个原子构成。“分子单层”指的是片层(在其它方面被称为层)，其中，厚度由单个分子构成，该层由通过共价键结合在一起的分子的重复图案形成。
优选地，薄层包括晶体状二维材料(尤其是二维半导体(还被称为2D半导体))的最多5个原子或分子单层。
有利地，沉积在块3上的薄层7是原子单层或分子单层。
例如，薄层7可由由石墨烯制成的原子单层形成，该原子单层即二维片层，该二维片层由碳原子组成、具有单个碳原子的厚度。
根据另一示例，薄层7可由过渡金属硫族化合物的分子单层(即MoS2或WS2或WSe2或MoSe2分子的二维片层)形成，从而形成2D晶体，该2D晶体具有对应于单个分子的厚度。
例如通过CVD(化学气相沉积)执行薄层7的生长。例如，当形成石墨烯层时，可在介于900℃至1200℃之间的温度执行该生长。替代地，薄层7可通过PVD(物理气相沉积)形成。
在图1B和图2B中示出的示例中，薄层覆盖模制块3并在块3的顶表面3a和侧表面3b、3c上延伸。根据替代实施例(未示出)，还能够想到仅在块3的一部分上生成薄层7，尤其是想到在块3的侧面上生成薄层7而遮蔽这些模制块3的其它区域。
优选地，想到模制块3采用适合于用于薄层7生长的催化剂的材料4。
例如，在寻求生长石墨烯的薄层7的情况下，可想到铜或铂块3。根据另一示例，当寻求形成MoS2或WS2的薄层7时，可想到由二氧化硅(SiO2)或金或甚至蓝宝石制成的块3。当寻求生长WSe2或MoSe2的薄层时，块3的材料4可以是SiO2。
块3的材料4的选择还可取决于如下材料，基于该材料想到进一步的被称为“保持块”的元件，保持块旨在在模制块3的至少部分去除之后支撑薄层7。
有利地，保持块9、10对应于源电极和漏电极。因此，优选地选择材料4，材料4可用作薄层7的催化剂，并且可选择性地与想到的形成源电极和漏电极的材料相关地去除。
在图2C中示出的实施例示例中，形成源极块9和漏极块10，源极块9和漏极块10在模制块3的端部用作保持块。在此处，源极块9和漏极块10接合数个模制块3的端部。
源极块9和漏极块10基于导电材料8，如上所述，导电材料8适合于经受模制块3的选择性蚀刻。例如，在模制块3基于铜或蓝宝石或SiO2的情况下，可想到基于金或铂生成块9、10。根据另一示例，可形成基于铂或金的模制块3，而块9、10基于钛。
在图1C和图2D中，示出随后的形成掩膜13的步骤。掩膜13通常是树脂掩膜并可通过旋转涂覆生成。通常，掩膜被沉积以覆盖模制块3以及源极块9和漏极块10。
然后，去除掩膜13厚度。
当掩膜是树脂时，例如使用尤其是ICP(电感耦合等离子体)或RIE(反应离子蚀刻)型的等离子蚀刻执行掩膜13的部分去除。
在图1D和图2E中示出的示例中，执行该去除以再次去除模制块3的顶部部分，还去除模制块3的该部分的水平处的薄层7。因此暴露形成模制块3的材料4。
然后，如图1E所示，执行模制块3的去除。在该实施例示例中，模制块3是旨在完全被去除的牺牲块。通过相对于在此处形成源电极和漏电极的保持块9、10的材料8选择性地蚀刻材料4，执行该去除。通常通过将该结构浸入蚀刻溶液中，执行块3的蚀刻。
适合于使用的蚀刻溶液的示例在下文中给出的表格中列出，溶液分别与催化剂材料4以及块9、10的材料8的不同示例相关联，材料8适合于经受模制块3的选择性蚀刻。
因此，根据特定实施例示例，当想到铂模制块3以生长石墨烯薄层7时，用于去除模制块3的蚀刻溶液可以是王水溶液，换句话说，盐酸和硝酸的混合物。为了能够经受这种蚀刻，在这种情况下，可想到生成钛块9、10。
在去除模制块3时，位于模制块3的端部的块9、10能够确保薄层7的未去除部分7a的机械强度。
在图2F中给出的实施例示例示出了蚀刻之后的结构，想到块9、10形成适合于保持薄层7的部分7a的源极区和漏极区，薄层7的部分7a竖直地延伸，换句话说，沿着与衬底1的主平面成不同于零的角度(例如大约90°)的方向延伸。
然后可去除掩膜13的其余部分。例如，当掩膜13由树脂制成时，通常通过浸入溶液中然后进行干燥来执行该去除。
在图1F中，表示掩膜13去除之后的结构。薄层7的剩余的竖直部分7a形成鳍，想到该鳍生成晶体管的沟道结构。鳍7a的临界尺寸Dc2对应于薄层7的厚度。
由于通过块9、10保持鳍7a，所以可有利地想到极其小的临界尺寸的鳍7a。因此，当薄层7以原子(或分子)单层的形式沉积时，因此可获得约为原子(或分子)的尺寸的临界尺寸Dc2。还可想到具有大高宽比Dc2/H[换句话说，临界尺寸Dc2与高度H(平行于z轴线测量的尺寸)之比]同时保持良好的机械强度的鳍。鳍7a的分布间隔取决于针对模制块3最初想到的间隔和模制块3的临界尺寸Dc1。
然后，在鳍7a上生成周围栅极。为此，首先沉积介电材料(例如，二氧化硅或HfO2)的层16。然后，鳍7a上覆盖有栅极材料，例如诸如金的金属(图1G)。
对于某些应用，尤其是传感器的用途，可能需要去除鳍的给定区域的高度处的栅极叠层的某些部分，因此暴露通道结构的区域。
然后，可想到生成接触和连接的步骤(未示出)。
根据上面描述的方法的示例的替代实施例，在暴露模制块3的顶部部分之后，可执行树脂掩膜13的去除(图3A)。因此，在去除模制块3(图3B)之前，去除掩膜13。
在上面描述的实施例示例中的一个或另一个示例中，模制块3形成模具，其中薄层7基本上是凸起的再现。因此，尤其通过改变模制块3的形状(不一定是平行六面体)，能够生成具有与上面描述的形状不同的形状的鳍。
在上面描述的实施例示例中的一个或另一个示例中，模制块3完全被去除。替代地，可想到模制块的部分去除。优选地，当保留模制块的一部分时，想到这些块采用介电材料，以尤其通过鳍结构优先进行传导。
在上面描述的示例中的一个或另一个示例中，保持块9、10有利地具有形成源电极和漏电极的进一步的功能。还能够想到在形成保持块9、10之后生成这些电极。
如上所述的晶体管可用在各种类型的电路，例如集成电路、处理器、逻辑电路中。
使用上面描述的类型的方法生成的finFET晶体管的示例在图4中示出。栅极叠层16、18仅保留在鳍7a的中央部分上，而位于中央部分与源极块9和漏极块10之间的端部区域7a1被暴露。
这种结构可用作例如检测结构的实施例的基础，该检测结构用于具有提高的检测灵敏度和减小的尺寸的化学和/或生物传感器。
鳍7a的暴露区域7a1可因此用于容纳至少一个还被称为“功能化层”的捕获层22，捕获层22基于适合于吸收和/或吸附至少一个待检测的化学或生物物质和/或与至少一个待检测的化学或生物物质发生反应的材料。
待检测的化学或生物元素适合于被捕获层22吸收或吸附或者与捕获层22发生反应，从而导致通道结构的电性能改变。
当鳍7a薄时，尤其提高检测灵敏度。
基于2D晶体(例如，MoS2或石墨烯)的鳍具有非常高的表面积-体积比，同时具有非常良好的电性能，这使得设置有这种结构的晶体管用在高灵敏度传感器中尤其有利。
各种类型的捕获层及其相关的应用通过示例的方式在下文的表格中列出。
根据特定实施例示例，其中，传感器是气体传感器，则可想到由多孔材料(例如，多孔氧化铝或多孔硅)制成的捕获层22。根据另一特定实施例示例，其中，传感器专用于非生物分子检测，则可想到由聚合物例如甲基丙烯酸甲酯制成的捕获层22。
考虑到在上文描述了形成沟道结构的鳍7a的尺寸及其实施例，这种晶体管尤其适合于检测非常小量的生物和/或化学元素，尤其是以对应于数ppb或数百ppb(十亿分之几)的浓度存在的化合物。
如上所述的方法可适合于生成图6中示出的类型的结构，在该方法中，鳍的临界尺寸取决于二维材料薄层的厚度，鳍的布置取决于其上形成有该鳍的至少一个模制块的形状和布置。
该结构包括朝向彼此不平行的不同方向的数个鳍7a、7’a。在图6的特定示例中，该结构包括垂直于衬底(其平面平行于平面[O；x；y]，衬底未表示出来)设置且彼此正交的鳍7a、7’a。鳍7a、7’a在交汇点或交点接合。鳍7a、7’a分别连接到电极91、92并通过电极91、92机械地固定。

Claims (13)

1.用于生成晶体管的方法，在所述晶体管中，沟道结构包括一个或多个鳍，所述方法包括如下步骤：
-在衬底(1)上形成一个或多个被称为模制块(3)的块，
-在一个或多个模制块上形成薄层(7)，所述薄层基于给定的半导体或半金属材料，并由二维晶体的一个至十个原子或分子单层构成，然后
-形成一个或多个保持块(9，10)，所述一个或多个保持块(9，10)分别位于所述模制块(3)的一个或多个端部，然后
-形成覆盖所述模制块(3)和所述保持块(9，10)的掩膜(13)，
-部分地去除所述掩膜(13)，去除一定厚度的所述掩膜(13)以暴露所述模制块(3)的顶部部分和所述保持块(9，10)，以及去除所述模制块(3)的顶部部分的高度处的所述薄层，
-去除所述一个或多个模制块，同时保留所述薄层的在所述模制块的至少一个侧面上延伸的一个或多个部分(7a)，所述一个或多个保留的部分(7a)形成一个或多个鳍，所述一个或多个鳍适合于形成所述晶体管的沟道结构，通过相对于所述一个或多个保持块(9，10)的材料选择性地蚀刻来执行所述模制块(3)的去除，所述一个或多个保持块(9，10)适合于在所述一个或多个模制块去除期间确保所述一个或多个鳍的机械强度，然后
-去除所述掩膜(13)的其余部分，然后
-在所述一个或多个鳍处生成栅电极。
2.根据权利要求1所述的方法，其中，所述薄层(7)通过催化生长形成，所述一个或多个模制块(3)基于用于使所述给定的半导体或半金属材料生长的催化材料。
3.根据权利要求1所述的方法，其中，所述保持块(9，10)是源电极和漏电极。
4.根据权利要求3所述的方法，其中，所述源电极和漏电极基于导电材料制成。
5.根据权利要求1所述的方法，其中，所述一个或多个模制块由介电材料制成。
6.根据权利要求1所述的方法，其中，所述薄层(7)的给定的半导体或半金属材料是石墨烯或金属硫族化合物。
7.根据权利要求1所述的方法，其中，所述栅电极是通过形成包括至少一个栅极介电层和至少一个栅极材料层的栅极叠层而生成的周围栅电极，所述方法进一步包括局部去除所述周围栅电极的一个或多个区域，以暴露所述一个或多个鳍的一个或多个给定区域。
8.根据权利要求7所述的方法，其中，在进行所述局部去除以去除所述栅极叠层的区域之后，基于适合于吸收和/或吸附至少一种化学物质的材料的至少一个捕获层(22)能形成在所述一个或多个鳍的暴露的给定区域上。
9.根据权利要求1所述的方法，其中，使用等离子蚀刻执行一定厚度的所述掩膜(13)的部分去除和所述模制块(3)的顶部部分的高度处的所述薄层的去除。
10.根据权利要求1所述的方法，其中，所述栅电极是周围栅电极。
11.根据权利要求5所述的方法，其中，所述介电材料是SiO2。
12.根据权利要求6所述的方法，其中，所述金属硫族化合物是MoS2或WS2或WSe2或MoSe2。
13.用于制造化学或生物传感器的方法，所述化学或生物传感器设置有至少一个晶体管，所述至少一个晶体管包括根据权利要求1所述的方法生成的晶体管。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110018851A (ko) * 2009-08-18 2011-02-24 세종대학교산학협력단 탄소 나노구조물 패턴 및 이의 제조 방법, 그리고 탄소 나노구조물 박막 트랜지스터 및 그의 제조 방법
WO2014197857A1 (en) * 2013-06-07 2014-12-11 The Regents Of The University Of California Additive-fin field effect transistor

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413802B1 (en) 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
KR100739656B1 (ko) * 2006-06-08 2007-07-13 삼성전자주식회사 반도체 장치의 제조 방법
US8216894B2 (en) 2008-06-17 2012-07-10 Nxp B.V. FinFET method and device
US7993986B2 (en) * 2008-08-29 2011-08-09 Advanced Micro Devices, Inc. Sidewall graphene devices for 3-D electronics
US20130214332A1 (en) * 2011-08-26 2013-08-22 Diagtronix, Inc. Nanogrid channel fin-fet transistor and biosensor
US8815739B2 (en) 2012-07-10 2014-08-26 Globalfoundries Inc. FinFET device with a graphene gate electrode and methods of forming same
US9678036B2 (en) 2013-03-15 2017-06-13 The Regents Of The University Of California Graphene-based gas and bio sensor with high sensitivity and selectivity
US8999821B2 (en) * 2013-08-19 2015-04-07 Applied Materials, Inc. Fin formation by epitaxial deposition
US9711647B2 (en) * 2014-06-13 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Thin-sheet FinFET device
US9368493B2 (en) * 2014-07-08 2016-06-14 Globalfoundries Inc. Method and structure to suppress FinFET heating
KR102455433B1 (ko) * 2015-07-03 2022-10-17 삼성전자주식회사 수직 정렬된 2차원 물질을 포함하는 소자 및 수직 정렬된 2차원 물질의 형성방법
US9589958B1 (en) * 2016-01-22 2017-03-07 International Business Machines Corporation Pitch scalable active area patterning structure and process for multi-channel finFET technologies
US9842931B1 (en) * 2016-06-09 2017-12-12 International Business Machines Corporation Self-aligned shallow trench isolation and doping for vertical fin transistors
US9704990B1 (en) * 2016-09-19 2017-07-11 International Business Machines Corporation Vertical FET with strained channel

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110018851A (ko) * 2009-08-18 2011-02-24 세종대학교산학협력단 탄소 나노구조물 패턴 및 이의 제조 방법, 그리고 탄소 나노구조물 박막 트랜지스터 및 그의 제조 방법
WO2014197857A1 (en) * 2013-06-07 2014-12-11 The Regents Of The University Of California Additive-fin field effect transistor

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