CN111435834B - Capacitive load and load short circuit identification method for direct current solid state power controller - Google Patents
Capacitive load and load short circuit identification method for direct current solid state power controller Download PDFInfo
- Publication number
- CN111435834B CN111435834B CN201910029072.1A CN201910029072A CN111435834B CN 111435834 B CN111435834 B CN 111435834B CN 201910029072 A CN201910029072 A CN 201910029072A CN 111435834 B CN111435834 B CN 111435834B
- Authority
- CN
- China
- Prior art keywords
- load
- short
- circuit
- current
- logic unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Landscapes
- Emergency Protection Circuit Devices (AREA)
Abstract
The invention relates to a capacitive load and load short circuit identification system and method for a direct current solid state power controller, comprising a singlechip, a logic unit, a hardware comparison circuit, a main loop, a current limiting loop, a sampling resistor, a freewheeling diode and a load, wherein the main loop is composed of an enhancement type metal oxide semiconductor field effect transistor MOSFET1, the current limiting loop is composed of an enhancement type metal oxide semiconductor field effect transistor MOSFET2 and a current limiting resistor, and the main loop and the enhancement type metal oxide semiconductor field effect transistor MOSFET in the current limiting loop jointly form a direct current solid state power switch. And according to the current characteristics of the capacitive load when the capacitive load is started and the capacitive load is in short circuit, the switching control is carried out on the main loop and the current limiting circuit, and the on-off control and the short circuit protection functions of the capacitive load with large capacitance are realized.
Description
Technical Field
The invention relates to a capacitive load and load short circuit identification method for a direct current solid state power controller.
Background
With the development of power electronics technology, aircraft are gradually developed towards multi-electric and all-electric aircraft. The aircraft designed by adopting the multi-electric mode has the great performance and functional advantages of light aircraft weight, high energy utilization rate, high system reliability, low guarantee requirement, strong self-detection function and the like, and meanwhile, the internal layout design of the aircraft can be greatly simplified. The core principle and technology of the intelligent power supply system comprise a high-voltage direct-current power generation technology, a distributed intelligent power distribution technology, a high-power electric power action technology and the like.
The application of the distributed intelligent power distribution technology has important significance for the development of the multi-electric aircraft, and the technical development level of the distributed intelligent power distribution technology relates to the final performance and the function of the electric system work of the multi-electric aircraft. The distributed intelligent power distribution system adopts a Solid State Power Controller (SSPC) to carry out load power consumption management, and has the capability of automatic management of airborne electric energy sources. The distributed power distribution technology adopts a high-speed bus control mode to replace a discrete control signal wire in a traditional power distribution system, and performs power supply control and protection on electric equipment through a solid-state power controller. With the development of multi-electric aircraft, the load type of the on-board equipment is also more and more complex, so that higher requirements are put on the load adaptability of the solid-state power controller.
Disclosure of Invention
The invention aims to solve the technical problem of providing a capacitive load and load short circuit identification system and method for a direct current solid state power controller, and the power supply control and protection of a large capacitive load in distributed intelligent power distribution are realized.
In the power circuit control of the traditional direct current solid state power controller, in order to meet the load compatibility requirement of the direct current solid state power controller and reduce electromagnetic interference generated when the load is turned on and off, the on-off control of the load is generally realized by adopting a soft switching technology of slow on and slow off. The slow turn-on is used for the turn-on of the capacitive load and the slow turn-off is used for the turn-off of the inductive load. With this control scheme, the capacitive load carrying capability of the DC solid state power controller depends on the power tube on time. Because the power tube is in a semi-conducting state in the switching-on and switching-off processes of the power tube, larger switching loss exists. Therefore, the requirements on the power tube are high, the power tube is generally applied to a direct current solid state power controller with smaller requirements on capacitive load capacity, and the control and protection on a larger capacitive load are difficult to realize.
In order to solve the technical problems, the invention provides a capacitive load and load short circuit identification method for a direct current solid state power controller, which can realize the control and protection functions of a large capacitive load, and the method comprises the following steps:
the method is characterized in that:
a) The direct current solid state power controller comprises a singlechip, a logic unit, a hardware comparison circuit, a main loop, a current limiting loop, a sampling resistor, a freewheeling diode and a load. The main loop is composed of an enhancement type metal oxide semiconductor field effect transistor (MOSFET 1), and the current limiting loop is composed of an enhancement type metal oxide semiconductor field effect transistor (MOSFET 2) and a current limiting resistor.
b) During capacitive load turn-on, a large current spike is generated in the power loop. When the load current is greater than the short circuit threshold I1, the logic unit controls MOSFET1 in the main loop to be turned off, while MOSFET2 in the current limiting loop is turned on. The load current is used for carrying out current-limiting charging on the capacitive load through the MOSFET2 in the current-limiting loop by the current-limiting resistor. The switching of the main loop and the current limiting loop is controlled by a logic unit.
c) By utilizing the characteristics that the current of the capacitive load is reduced in an exponential waveform when the RC current-limiting charging is performed and the current is kept unchanged when the load is in short circuit to the ground, two current comparison points are arranged when the current-limiting loop works. At time t1, the load current is compared to a short circuit threshold I1. This case mainly considers the situation when the load is directly shorted to ground; at time t2, the load current is compared to a short circuit threshold I2. This case mainly considers the case where there is a low impedance path between the load and ground; t1 and t2 are determined according to the safe operating area of the MOSFET2 in the current-limiting loop. When the load current is smaller than the short-circuit threshold value in the two comparison steps, judging that the load is a capacitive load, cutting off the current-limiting loop at the time t3, and simultaneously opening the main loop to finish the opening process of the whole capacitive load. Otherwise, immediately executing short-circuit protection, and cutting off the current-limiting loop and the main loop.
d) The MOSFETs in the main loop and the current-limiting loop have short on-off time, small switching loss of the MOSFETs, and small electric stress, and the reliability of the solid-state power controller is improved.
According to the characteristics of capacitive load and load short-circuit current, the invention realizes the control and short-circuit protection functions of the capacitive load with large capacitance of the direct current solid state power controller through the switching control of the main loop and the current limiting circuit. The DC solid-state power controller obtains larger load carrying capacity of the capacitive load.
Drawings
The present invention will be described in detail below with reference to the accompanying drawings and examples.
Fig. 1 is a block diagram of a power circuit and control for a dc solid state power controller in accordance with the present invention.
Fig. 2 is a flow chart of a capacitive load and load short circuit identification method for a dc solid state power controller of the present invention.
Fig. 3 is a short-circuit protection waveform when the load current is continuously greater than the short-circuit threshold I1.
Fig. 4 is a short-circuit protection waveform when a low-impedance path exists between the load and ground of the present invention.
Fig. 5 is a current waveform when the load of the present invention is a load.
Fig. 6 is a waveform of a load current when the capacitive load capacity value of the present invention is exceeded.
Detailed Description
The invention relates to a capacitive load and load short circuit identification method for a direct current solid state power controller, which is used for switching control of a main loop and a current limiting circuit through specific logic according to characteristics of capacitive load and load short circuit current, so as to realize control and short circuit protection functions of a large capacitive load. The capacitive load starting and load short circuit electric stress born by the main loop power tube is reduced, and the capacitive load carrying capacity and hardware reliability of the direct current solid state power controller are improved.
In the distributed intelligent power distribution system of the multi-electric aircraft, the direct-current solid-state power controller is required to have larger load carrying capacity of a capacitive load, and the multiple requirement on load short-circuit protection current is very high, and the rated current is generally 8-10 times. The short-circuit protection time is within hundreds of microseconds, and the automatic reclosing function is realized after the short circuit. The method can be adopted for the direct current solid state power controller with high capacity capacitive load requirement, short circuit protection time and high current threshold.
As shown in fig. 1, a block diagram of a power circuit and control for a dc solid state power controller in accordance with the present invention is shown. The device comprises a singlechip, a logic unit, a hardware comparison circuit, a main loop, a current limiting loop, a sampling resistor, a freewheeling diode and a load. The main loop is composed of an enhancement type metal oxide semiconductor field effect transistor MOSFET and the current limiting loop is composed of an enhancement type metal oxide semiconductor field effect transistor MOSFET and a current limiting resistor. The main loop and the enhancement type metal oxide semiconductor field effect transistor MOSFET in the current limiting loop form a direct current solid state power switch together to realize on-off control of a load.
As shown in fig. 2, a flow chart of a capacitive load and load short circuit identification method for a dc solid state power controller includes the steps of:
step 1: the singlechip receives an external opening instruction through the communication bus and the channel is not in a short circuit and overload protection state.
Step 2: the singlechip outputs a discrete on signal to the logic unit, and the logic unit outputs a driving signal to turn on a field effect transistor (MOSFET 1) in a main loop of the solid-state power controller.
Step 3: the sampling resistor converts the load current into a voltage signal, and the load current is compared with a short-circuit threshold I1 through a hardware comparison circuit. If the load current is smaller than the short-circuit threshold value I1, executing the step 4, otherwise executing the step 5.
Step 4: the load continues to be normally turned on, and the step 3 is continuously executed.
Step 5: the load current is greater than the short circuit threshold I1, and the comparator output signal is sent to the logic unit and latched, and the delay logic in the logic unit is started.
Step 6: the logic unit outputs a driving signal to close the main loop power tube and simultaneously open the current-limiting loop power tube.
Step 7: and delaying to t1, and comparing the load current with a short-circuit threshold I1 through a hardware comparison circuit. If the load current is greater than the short circuit threshold I1, step 12 is performed. Otherwise, step 8 is performed.
Step 8: and delaying to t2, and outputting an excitation signal to a hardware comparison circuit by the logic unit to change the short circuit threshold I1 into the short circuit threshold I2.
Step 9: the load current is compared with a short-circuit threshold I2 by a hardware comparison circuit. If the load current is less than the short-circuit threshold I2, step 10 is performed, otherwise step 13 is performed.
Step 10: at times t1 and t2, the load current is less than the short circuit threshold, and the load is judged to be a capacitive load. And (3) delaying to t3, cutting off the current-limiting loop, and simultaneously opening the main loop to finish the opening process of the whole capacitive load.
Step 11: the delay logic in the logic unit resumes the initial state, cancels the excitation signal output, and the short circuit threshold value I2 resumes to the short circuit threshold value I1.
Step 12: and judging that the load is short-circuited, closing the main loop and the current-limiting loop simultaneously by the logic unit to perform immediate short-circuit protection, latching a short-circuit signal and sending the short-circuit signal to an external interrupt pin of the singlechip to perform reclosing timing.
Step 13: and judging that the load is short-circuited, canceling the output of the excitation signal by the logic unit, and recovering the short-circuit threshold I2 to be the short-circuit threshold I1.
Step 14: the singlechip receives an external interrupt signal and enters an external interrupt service routine.
Step 15: the number of interrupts is recorded in the external interrupt service routine and an internal timer is started.
Step 16: judging whether the singlechip enters an external interrupt service routine for the first time, if so, executing step 17, otherwise, judging that the singlechip is short-circuited again, and executing step 20.
Step 17: and after the timer in the singlechip times a time interval reaching the reclosing requirement, outputting an unlocking signal to the logic unit to unlock the short circuit signal, and opening the main loop to reclose.
Step 18: and after reclosing, comparing the load current with a short-circuit threshold I1 through a hardware comparison circuit. If the load current is greater than the short-circuit threshold I1, step 12 is performed, otherwise step 19 is performed.
Step 19: the SCM clears the record of the interruption times, and the load is normally opened. And (3) continuously executing the step (3) to monitor the load current.
Step 20: the singlechip reports and latches the short-circuit state through the communication bus, sends a closing instruction to the logic unit, closes the load, and delays logic in the logic unit to restore the initial state, and waits for receiving a reset command to clear the short-circuit state.
Step 21: and (3) clearing the record of the interruption times by the singlechip, and jumping to the step (1) to finish the discrimination process of the whole capacitive load and the load short circuit.
Examples
The load current comparison time in the present invention will be further described by taking a certain type of dc solid state power controller as an example.
1. And judging the meaning at the time t 1.
When the direct grounding short circuit occurs, the load current is larger than the short circuit threshold I1, and after the hardware comparison circuit detects that the load current is larger than the short circuit threshold I1, the hardware comparison circuit outputs a signal to the logic unit, cuts off the main loop and simultaneously opens the current limiting loop. Because the current limiting resistor exists in the current limiting loop, the current is maintained at the limiting current set by the current limiting resistor, and under the limiting current, if the selected MOS tube can work for 1ms according to the SOA curve (safe operating area) of the MOS tube, in order to meet the design allowance, the derating design is carried out, the t1 is selected to be about 500us, and the load is immediately protected. The short circuit protection waveforms are shown in fig. 3.
2. And judging the meaning at the time t 2.
When a low impedance path exists between the load and ground, the load current exceeds the short circuit threshold I1, and the logic unit cuts off the main loop while opening the current limiting loop. After switching to the current limiting loop, the load current is smaller than the short-circuit threshold I1 but is close to the short-circuit threshold I1 because the current limiting resistor and the load resistor are in series connection. The current does not meet the protection condition at time t1, and the load is continuously turned on. Therefore, the judgment is selected to be carried out again at the time t2, and the load is subjected to short-circuit protection. the choice of t2 mainly considers the SOA curve (safe operating area) of the MOS tube under the current condition, and the derating design is carried out, and the time t2 is about a few ms. The short-circuit protection waveforms in this case are shown in fig. 4.
3. Meaning at time t 3.
t3 is designed mainly to meet the requirement of capacitive load charging, and the time is 4 times of the capacitive load charging time constant. After the capacitive load is charged to time t3, the voltage of the capacitive load reaches 98.17% of the power input voltage. Since the capacitive load is not fully charged, after the current limiting loop is switched to the main loop, the voltage difference between the power input and the capacitive load voltage is reduced on the sampling resistor, and a small current peak is generated. The capacitive load band carrier shape is shown in fig. 5. If the capacitance of the loaded capacitive load exceeds the limit, the protection is performed at time t2, and the waveform is shown in fig. 6.
Through verification, after the invention is adopted in the system, the direct current solid state power controller can meet the load demand of a large capacitive load. Compared with the prior art, the beneficial effects are as follows: the capacitive load starting and load short circuit electric stress born by the main loop power tube is reduced, and the capacitive load carrying capacity and hardware reliability of the direct current solid state power controller are improved.
Claims (1)
1. The capacitive load and load short circuit identification method for the direct current solid state power controller is based on the design of a capacitive load and load short circuit identification system, the capacitive load and load short circuit identification system comprises a singlechip, a logic unit, a hardware comparison circuit, a main loop, a current limiting loop, a sampling resistor, a freewheeling diode and a load, wherein the main loop is composed of a field effect transistor MOSFET1, the current limiting loop is composed of a field effect transistor MOSFET2 and a current limiting resistor, the field effect transistor MOSFET1 and the field effect transistor MOSFET2 jointly form a direct current solid state power switch to realize the on-off control of the load,
step 1, a singlechip receives an external opening instruction through a communication bus, and a channel is not in a short circuit and overload protection state;
step 2, the singlechip outputs a discrete opening signal to the logic unit, and the logic unit outputs a driving signal to open a field effect transistor MOSFET1 in the main loop;
step 3, the sampling resistor converts the load current into a voltage signal, and the load current is compared with a short-circuit threshold I1 through a hardware comparison circuit; if the load current is smaller than the short-circuit threshold I1, executing the step 4, otherwise executing the step 5;
step 4, the load is continuously and normally opened, and the step 3 is continuously executed;
step 5, the load current is larger than the short-circuit threshold I1, the output signal of the comparator is sent to the logic unit and is latched, and delay logic in the logic unit is started;
step 6, the logic unit outputs a driving signal to turn off the field effect transistor MOSFET1 in the main loop and turn on the field effect transistor MOSFET2 in the current limiting loop;
step 7, delaying until t1, and comparing the load current with a short-circuit threshold I1 through a hardware comparison circuit; if the load current is greater than the short-circuit threshold I1, executing step 12; otherwise, executing the step 8;
step 8, delaying until t2, and outputting an excitation signal to a hardware comparison circuit by a logic unit to change the short circuit threshold I1 into a short circuit threshold I2;
step 9, comparing the load current with a short-circuit threshold I2 through a hardware comparison circuit;
if the load current is smaller than the short-circuit threshold I2, executing the step 10, otherwise executing the step 13;
step 10, judging that the load is a capacitive load when the load current is smaller than a short-circuit threshold value at the time t1 and the time t2; delaying to t3, cutting off the current-limiting loop and simultaneously opening the main loop to finish the opening process of the whole capacitive load;
step 11, the delay logic in the logic unit restores the initial state, the output of the excitation signal is canceled, and the short circuit threshold I2 is restored to be the short circuit threshold I1;
step 12, judging that the load is short-circuited, closing the main loop and the current-limiting loop simultaneously by the logic unit to perform immediate short-circuit protection, latching a short-circuit signal and sending the short-circuit signal to an external interrupt pin of the singlechip to perform reclosing timing;
step 13, judging that the load is short-circuited, canceling the output of the excitation signal by the logic unit, and recovering the short-circuit threshold I2 to be the short-circuit threshold I1;
step 14, the singlechip receives an external interrupt signal and enters an external interrupt service routine;
step 15, recording the interrupt times in an external interrupt service routine, and starting an internal timer;
step 16, judging whether the singlechip enters an external interrupt service routine for the first time, if yes, executing step 17, otherwise, judging that the singlechip is short-circuited again, and executing step 20;
step 17, after the timer in the singlechip counts the time interval reaching the reclosing requirement, outputting an unlocking signal to the logic unit to unlock the short-circuit signal, and opening the main loop to reclose;
step 18, comparing the load current with a short-circuit threshold I1 through a hardware comparison circuit after reclosing;
if the load current is greater than the short-circuit threshold I1, executing step 12, otherwise executing step 19;
step 19, the singlechip clears the record of the interruption times, and the load is normally opened;
continuously executing the step 3 to monitor the load current;
step 20, the singlechip reports and latches a short-circuit state through a communication bus, sends a closing instruction to a logic unit, closes a load, and delays logic in the logic unit to restore an initial state, and waits for receiving a reset command to clear the short-circuit state;
and 21, clearing the interrupt frequency record by the singlechip, and jumping to the step 1 to finish the judging process of the whole capacitive load and the load short circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910029072.1A CN111435834B (en) | 2019-01-12 | 2019-01-12 | Capacitive load and load short circuit identification method for direct current solid state power controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910029072.1A CN111435834B (en) | 2019-01-12 | 2019-01-12 | Capacitive load and load short circuit identification method for direct current solid state power controller |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111435834A CN111435834A (en) | 2020-07-21 |
CN111435834B true CN111435834B (en) | 2023-07-28 |
Family
ID=71580573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910029072.1A Active CN111435834B (en) | 2019-01-12 | 2019-01-12 | Capacitive load and load short circuit identification method for direct current solid state power controller |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111435834B (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112491031A (en) * | 2020-12-10 | 2021-03-12 | 汉中一零一航空电子设备有限公司 | Airborne direct-current high-voltage positive and negative power supply power distribution control and overload protection system |
CN113891521B (en) * | 2021-11-05 | 2023-09-19 | 深圳市角度控光智能照明技术有限公司 | PWM chopping dimming redundant circuit and chopping dimming method thereof |
CN114421438B (en) * | 2022-01-11 | 2023-12-01 | 南京开关厂有限公司 | Predictive fault protection device and method for direct current solid state circuit breaker |
CN115561560B (en) * | 2022-10-21 | 2023-09-22 | 南京信息工程大学 | Pure hardware implementation control circuit and control method for power device aging test |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4955069A (en) * | 1989-03-02 | 1990-09-04 | Ionescu Adrian F | A.C. power controller with short circuit and overload protection |
JP2005312099A (en) * | 2004-04-16 | 2005-11-04 | Auto Network Gijutsu Kenkyusho:Kk | Intelligent power device and its load short circuit protection method |
CN102571053A (en) * | 2012-01-16 | 2012-07-11 | 南京航空航天大学 | Control method for alternate current solid power switch and switch device |
CN103166168A (en) * | 2011-12-19 | 2013-06-19 | 上海航空电器有限公司 | High-voltage direct current solid state power controller |
-
2019
- 2019-01-12 CN CN201910029072.1A patent/CN111435834B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4955069A (en) * | 1989-03-02 | 1990-09-04 | Ionescu Adrian F | A.C. power controller with short circuit and overload protection |
JP2005312099A (en) * | 2004-04-16 | 2005-11-04 | Auto Network Gijutsu Kenkyusho:Kk | Intelligent power device and its load short circuit protection method |
CN103166168A (en) * | 2011-12-19 | 2013-06-19 | 上海航空电器有限公司 | High-voltage direct current solid state power controller |
CN102571053A (en) * | 2012-01-16 | 2012-07-11 | 南京航空航天大学 | Control method for alternate current solid power switch and switch device |
Also Published As
Publication number | Publication date |
---|---|
CN111435834A (en) | 2020-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111435834B (en) | Capacitive load and load short circuit identification method for direct current solid state power controller | |
US10096989B2 (en) | High-voltage DC current breaker and high-voltage DC current breaking method | |
EP2398146B1 (en) | High power DC SSPC with capability of soft turn-on to large capacitive loads | |
CN103427809B (en) | The protective circuit of insulated gate bipolar transistor | |
CN101965669B (en) | Electronic DC circuit breaker | |
US10193544B2 (en) | Minimizing ringing in wide band gap semiconductor devices | |
CN103166168A (en) | High-voltage direct current solid state power controller | |
CN109375087A (en) | A kind of protection circuit and method with high speed detection IGBT short trouble | |
CN105932864A (en) | Intelligent IGBT (insulated gate bipolar transistor) constant-current driving device | |
US11095284B2 (en) | Minimizing ringing in wide band gap semiconductor devices | |
CN110365196A (en) | Three level integral type SiC-Mosfet drive systems and drive control method | |
KR20130040657A (en) | Apparatus and method for protecting supply modulator | |
US20230132537A1 (en) | An undervoltage protection circuit for a dc/dc converter and method thereof | |
CN110572011B (en) | IGBT drive circuit soft switching device with short-circuit protection | |
CN115714527A (en) | Large capacitive load starting method in high-voltage direct current solid-state power controller | |
CN110768221A (en) | Adaptive reclosing method for overhead flexible direct-current power grid | |
CN205829454U (en) | A kind of intelligentized IGBT constant current driving device | |
CN203840311U (en) | Solid state power controller | |
CN104393571A (en) | IGBT module over-current protection system | |
CN209748179U (en) | rail transit IGBT full-time protection driver | |
CN204424877U (en) | A kind of IGBT module Over Current Protection System | |
CN203747633U (en) | IGBT driving circuit | |
Kurniawan et al. | Experiment result of high frequency switching SiC mosfet gate driver | |
CN204761017U (en) | Electric automobile power battery contactor protection device | |
CN118264088A (en) | Capacitive load carrying circuit and method in high-voltage direct-current solid-state power controller |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |