CN118264088A - Capacitive load carrying circuit and method in high-voltage direct-current solid-state power controller - Google Patents

Abstract

The invention discloses a capacitive load carrying circuit and a capacitive load carrying method in a high-voltage direct-current solid-state power controller. The circuit comprises: the device comprises a power input, a controller main loop, a controller current-limiting loop, a sampling resistor, a freewheeling diode, a capacitive load, a power ground terminal, a singlechip, a logic unit, a current comparison unit and a second comparison unit. The invention has the beneficial effects that: the accuracy of judging the capacitive load and the short circuit is improved, the electric stress born by the main loop power tube when the capacitive load is started and the capacitive load is in short circuit is reduced, and the capacitive load carrying capacity, load adaptability and hardware reliability of the high-voltage direct-current solid-state power controller are improved.

Description

Capacitive load carrying circuit and method in high-voltage direct-current solid-state power controller

Technical Field

The invention relates to a capacitive load carrying circuit and a capacitive load carrying method in a high-voltage direct-current solid-state power controller.

Background

With the development of power electronics technology, aircraft are gradually developed towards multi-electric and all-electric aircraft. Among them, the distributed intelligent power distribution system is a key technology of the multi-electric aircraft, and the state of the art relates to the final performance and function of the operation of the electrical system of the multi-electric aircraft. The distributed intelligent power distribution system generally adopts a Solid State Power Controller (SSPC) to carry out capacitive load electricity management, and has the capacity of automatic management of airborne electric energy sources. Because the high-voltage direct-current power supply system has the advantages of light weight and high efficiency, uninterrupted power supply and redundant power supply are easy to realize, the power supply system can be more suitable for the power requirements of high-technology electric equipment such as an electric transmission system and the like, and the transition to a multi-power and full-power aircraft is facilitated. Multiple electric aircraft power supplies are also increasingly employing high voltage dc power supply systems. As the type of capacitive load of on-board devices becomes more and more complex, higher demands are placed on the capacitive load adaptability of solid state power controllers.

Taking the capacitive load as an example, since the capacitive load has a larger current at the moment of switching on, the current is similar to the current at the moment of short circuit. In order to meet the load requirement of the capacitive load, there are two main ways to realize: firstly, the capacitive load carrying requirement is met by adopting a mode of controlling the on time of the MOS tube. The defects are that: in the switching-on and switching-off processes of the MOS transistor, the MOS transistor is in a semi-conducting state, and large switching loss exists. Control and protection for large capacitive loads is difficult to achieve. Second, the power loop of the solid-state power controller is controlled by adopting a main loop and a current-limiting loop. When the capacitive load is detected to be larger than the short circuit threshold, the main loop is closed, the current limiting loop is opened at the same time, and the capacitive load is charged in a current limiting mode through the current limiting resistor on the current limiting loop, for example, the Chinese invention application CN111435834A. The disadvantage is that for high voltage solid state power controllers above 270V, this approach, due to the limited charging time, the capacitive load cannot be fully charged, and the voltage difference between the power input and the capacitive load (typically tens of V) will be added to the sampling resistor after switching to the main loop, resulting in the detected capacitive load current again exceeding the short circuit threshold, resulting in reporting a short circuit trip.

Disclosure of Invention

The invention aims to solve the technical problems in the prior art and provides a novel capacitive load carrying circuit and a capacitive load carrying method in a high-voltage direct-current solid-state power controller.

In order to achieve the purpose, the technical scheme of the invention is as follows: a capacitive load circuit in a high voltage dc solid state power controller, comprising: the device comprises a power input, a controller main loop, a controller current-limiting loop, a sampling resistor, a freewheeling diode, a capacitive load, a power ground terminal, a singlechip, a logic unit, a current comparison unit and a second comparison unit. When the capacitive load is loaded or the power output is short-circuited to the ground, the load current and the load terminal voltage are detected simultaneously. The current comparison circuit and the voltage comparison circuit output current comparison signals and voltage comparison signals to the logic unit, and the logic combination is used for judging the short circuit and the capacitive load together to control the opening and closing of the main loop and the current limiting loop.

And when the load current is smaller than the set short circuit threshold value at the time t1 and the time t2, delaying until the time t 3. And then the voltage comparison circuit is used for judging the voltage Vab at two ends of the MOSFET and the load voltage Vbc, judging whether the RC charge needs to be finished in advance and filling the capacitive load through the main loop. When Vab is smaller than Vbc, the load is judged to be capacitive, the current limiting loop is closed, the main loop is opened, the output signal of the current comparison circuit is shielded to the time t4 through the logic unit, and the capacitive load is filled by the MOSFET of the main loop. At this time, the capacitive load is carried successfully; when Vab is larger than Vbc, judging that the capacitive load is not present, and delaying until the time t4, closing the current-limiting loop, and opening the main loop. And if the load current is larger than the short circuit threshold value, immediately executing short circuit protection, and cutting off the current limiting loop and the main loop. If the load current is smaller than the short-circuit threshold value after the main loop is switched, the main loop is always connected, and the load loading is successful.

When the power input voltage is low, if the load is directly short-circuited to ground, the short-circuit protection can be identified and performed.

Compared with the prior art, the invention has the beneficial effects that: according to the characteristics of capacitive load and capacitive load short-circuit current, capacitive load current and voltage signals are collected, the output signals are sent to a logic unit through a current and second comparison unit to carry out logic judgment, switching control is carried out on a main loop and a current limiting circuit, and the control and short-circuit protection functions of the direct current solid state power controller with large capacitive load value are achieved. The direct-current solid-state power controller can obtain larger load carrying capacity, reduce the electric stress born by the main loop power tube when the load is started and the load is short-circuited, and improve the load carrying capacity and hardware reliability of the direct-current solid-state power controller.

Drawings

Fig. 1 is a schematic diagram of a capacitive load carrying circuit in a high voltage dc solid state power controller according to the present invention.

Fig. 2 is a flow chart of a capacitive load loading method in the high voltage dc solid state power controller of the present invention.

Fig. 3 is a waveform diagram of the short-circuit protection when the load current is continuously greater than the short-circuit threshold I1.

Fig. 4 is a waveform diagram of the short-circuit protection of the present invention when a low impedance path exists between the load and ground.

Fig. 5 is a waveform diagram of the short-circuit protection of the load when the load is short-circuited to ground when the power input is low voltage.

Fig. 6 is a current waveform diagram of the load of the present invention when the load is a capacitive load.

Fig. 7 is a waveform diagram of a load current when the capacitance of the capacitive load exceeds the limit of the present invention.

Detailed Description

The invention will be described in further detail below with reference to the drawings by means of specific embodiments. The description of these embodiments is provided to assist understanding of the present invention, but is not to be construed as limiting the present invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

Referring to fig. 1, a capacitive load carrying circuit in a high voltage (270V or more) dc solid state power controller is shown, which can be used in the field of distributed intelligent power distribution systems for aircraft, ships, and combat vehicles.

The capacitive load carrying circuit includes: the device comprises a power input, a controller main loop, a controller current-limiting loop, a sampling resistor, a freewheeling diode, a capacitive load, a power ground terminal, a singlechip, a logic unit, a current comparison unit and a second comparison unit.

The controller main loop includes: a transistor MOSFET1.

The controller current limiting loop comprises: transistor MOSFET2, current limiting resistor.

The transistor MOSFET1 is connected in series between the power input and the power output. The transistor MOSFET2 and the current limiting resistor are also connected in series between the power input and the power output. The sampling resistor and the capacitive load are connected in series between the power output and the power ground.

In this embodiment, the power input is connected to the first terminal of the transistor MOSFET1 and the first terminal of the current limiting resistor, respectively. The second end of the current limiting resistor is connected with the first end of the transistor MOSFET 2. The second terminal of the transistor MOSFET1 and the second terminal of the transistor MOSFET2 are both connected to the power output. The power output is connected to a first end of the sampling resistor. The second end of the sampling resistor is connected with the first end of the capacitive load. A second end of the capacitive load is connected to the power ground.

The sampling resistor is used for sampling the passing current of the capacitive load.

The first comparison unit is used for comparing the passing current of the capacitive load with a short-circuit threshold current.

A first output of the logic unit is connected to a control terminal of the transistor MOSFET1 of the controller main loop. The first output of the logic unit is for outputting a first control signal. The transistor MOSFET1 is selectively turned on or off according to the first control signal.

A second output of the logic unit is connected to the control terminal of the transistor MOSFET2 of the controller current limiting loop. A second output of the logic unit is for outputting a second control signal. The transistor MOSFET2 is selectively turned on or off according to the second control signal.

The singlechip is connected with the logic unit. The logic unit is respectively connected with the control end of the transistor MOSFET1, the control end of the transistor MOSFET2, the first comparison unit and the second comparison unit.

The second comparing unit is configured to compare the voltage across the transistor MOSFET1 with the voltage across the capacitive load.

The logic unit judges the short circuit and the capacitive load according to the judging result of the first comparing unit and the judging result of the second comparing unit and determines that the transistor MOSFET1 and the transistor MOSFET2 are turned on or turned off according to the judging result.

And detecting the capacitive load current and the capacitive load terminal voltage simultaneously when the capacitive load is loaded or the power output is short-circuited to the ground. The current comparison unit and the second comparison unit output a current comparison signal and a voltage comparison signal, the current comparison signal and the voltage comparison signal are sent to the logic unit, and the short circuit and the capacitive load are judged together through logic combination to control the opening and closing of the main loop and the current limiting loop.

By utilizing the characteristics that the capacitive load decreases in an exponential waveform of the RC current-limiting charging current, increases in an exponential waveform of the voltage waveform and does not change in current and voltage when the capacitive load is in short circuit to the ground, two current comparison points are arranged when the current-limiting loop works. At time t1, the capacitive load current is compared to a short circuit threshold I1. This case mainly considers the case when the capacitive load is directly shorted to ground; at time t2, the capacitive load current is compared to a short circuit threshold I2.

This case mainly considers the case where there is a low impedance path between the capacitive load and ground; t1 and t2 are determined according to the safe operating area of the MOSFET2 in the current-limiting loop. When the capacitive load current is smaller than the short-circuit threshold value in the twice comparison, charging is continuously carried out on the current-limiting loop; the type of the capacitive load is again determined at time t3 by the change in the voltage of the capacitive load. If the capacitive load is judged, the current comparison unit signal is shielded, and the capacitive load is filled by the main loop MOSFET. Eliminating the signal of the shielding current comparing unit when the time t4 is reached; if the capacitive load is judged to be non-capacitive load, the current-limiting loop is closed and the main loop is opened after time delay reaches t 4.

When the power input voltage is low, short-circuit protection can be identified and performed if the capacitive load is directly short-circuited to ground.

According to the characteristics of capacitive load and short-circuited capacitive load current and capacitive load voltage, the control and short-circuit protection functions of the capacitive load with large capacitance are realized through the switching control of the main loop and the current limiting circuit. Compared with the prior art, the beneficial effects are as follows: the capacitive load capacity, the capacitive load adaptability and the hardware reliability of the 270V high-voltage direct-current solid-state power controller are improved.

Referring to fig. 2, a capacitive load loading method in a hvdc solid state power controller is shown. The method comprises the following steps:

Step S1, the singlechip receives an external opening instruction. The opening instruction is transmitted to the singlechip through a communication bus. The opening instruction is used for requesting the singlechip to open the main loop of the controller.

And S2, the singlechip controls the transistor MOSFET1 of the controller main loop to be conducted and controls the transistor MOSFET2 of the controller current-limiting loop to be turned off through the logic unit, so that the controller main loop is communicated with the power input and the power output.

Step S3, the first comparing unit compares the passing current of the capacitive load with the magnitude of the short-circuit threshold current I1: if the capacitive load passing current is greater than the short-circuit threshold current I1, entering a step S5; if not, the process proceeds to step S4.

And S4, normally switching on the capacitive load. And returning to the step S3.

And S5, the first comparison unit sends the comparison result to the logic unit for latching. Delay logic within the logic unit is enabled.

Step S6, opening the controller current limiting loop, and closing the controller main loop: the first control signal is configured as an off signal and the second control signal is configured as an on signal such that the transistor MOSFET1 of the controller main loop is off and the transistor MOSFET2 of the controller current limiting loop is on.

Step S7, delaying until t1, where the first comparing unit compares the passing current of the capacitive load with the short-circuit threshold I1 again: if the capacitive load passing current is greater than the short-circuit threshold current I, where i=i1, then step S14 is entered; if not, the process proceeds to step S8.

And S8, delaying until t2, wherein the short-circuit threshold current I is replaced by I2 from I1. Wherein I1 > I2. The logic unit outputs an excitation signal to the first comparing unit, and when the first comparing unit receives the excitation signal from the first comparing unit, the first comparing unit configures the short-circuit threshold current I to be I2.

Step S9, the first comparing unit compares the passing current of the capacitive load with the short-circuit threshold current I (i.e. i=i2): if the capacitive load passing current is greater than the short-circuit threshold current I, proceeding to step S15; if not, the process proceeds to step S10.

Step S10, delaying until t3, comparing the voltage Vab across the transistor MOSFET1 in the main loop with the voltage Vbc across the capacitive load: if Vab < Vbc, go to step S11; if not, the process proceeds to step S13.

And S11, at the time t3, opening the main loop of the controller, closing the current-limiting loop of the controller, fully charging the capacitive load by the power input, shielding the output of the first comparison unit to the time t4, and normally opening the capacitive load.

Step S12, the delay logic in the logic unit is restored to an initial state, the output of the excitation signal is canceled, and the step S3 is returned;

Step S13, delay until t4, open the said controller main loop, close the said controller current-limiting loop, enter step S12, if the capacitive load current exceeds the said current threshold I1 again, report the short circuit. Step 12 is then performed.

Step S14, closing the controller main loop and the controller current limiting loop, and performing short-circuit protection on the capacitive load: at the moment, the capacitive load is judged to be short circuit, and meanwhile, a short circuit signal is latched and sent to an external interrupt pin of the singlechip for reclosing timing. Step S16 is entered.

And S15, canceling the excitation signal. The short-circuit threshold current I is replaced by I1 by I2. And returning to the step 14.

Step S16, the singlechip receives an external interrupt signal and enters an external interrupt service routine. Then step S17 is performed.

Step S17, recording the interrupt times in the external interrupt service program, and starting an internal timer. Then step S18 is performed;

step S18, judging whether the singlechip enters an external interrupt service routine for the first time: if yes, go to step S19; if not, judging that the circuit is short-circuited again, and executing the step S23;

Step S19, after the timer in the singlechip counts the time interval reaching the reclosing requirement, outputting an unlocking signal to the logic unit to unlock the short-circuit signal, opening the main loop to reclose, and then executing step S20;

step S20, after reclosing, the capacitive load current is compared with the short-circuit threshold I1 again by the current comparing unit. If the capacitive load current is greater than the short-circuit threshold value I1, executing the step S14, otherwise executing the step S21;

step S21, the singlechip clears the record of the interruption times, the capacitive load is normally turned on, and the step S3 is returned;

And S22, the singlechip clears the record of the interruption times, returns to the step S1, and completes the discrimination process of the whole capacitive load and the capacitive load short circuit. Step 1 is then performed.

And S23, reporting and latching a short-circuit state by the singlechip through the communication bus, sending a closing instruction to the logic unit, closing the capacitive load, recovering the initial state by delay logic in the logic unit, waiting for receiving a reset command to clear the short-circuit state, and returning to the step S22.

Examples

The moment of capacitive load current comparison in the present invention will be further described below by taking a certain type of high-voltage dc solid-state power controller as an example.

1. And judging the meaning at the time t 1.

When the direct grounding short circuit occurs, the capacitive load current is larger than the short circuit threshold value I1, and after the current comparison unit detects that the capacitive load current is larger than the short circuit threshold value I1, the current comparison unit outputs a signal to the logic unit, cuts off the main loop and simultaneously opens the current limiting loop. Because the current limiting resistor exists in the current limiting loop, the current is maintained at the limiting current set by the current limiting resistor, and under the limiting current, if the selected MOS tube can work for 1ms according to the SOA curve (safe operating area) of the MOS tube, in order to meet the design allowance, the derating design is carried out, the t1 is selected to be about 500us, and the capacitive load is immediately protected. The short circuit protection waveforms are shown in fig. 3.

2. And judging the meaning at the time t 2.

When a low impedance path exists between the capacitive load and ground, the capacitive load current exceeds a short circuit threshold I1, and the logic unit cuts off the main loop while opening the current limiting loop. After switching to the current limiting loop, the current limiting resistor and the capacitive load resistor are in series connection, so that the capacitive load current is smaller than the short circuit threshold I1, but is close to the short circuit threshold I1. The current does not meet the protection condition at time t1 and the capacitive load is continuously on. Therefore, the judgment is selected to be carried out again at the time t2, and the capacitive load is short-circuit protected. the choice of t2 mainly considers the SOA curve (safe operating area) of the MOS tube under the current condition, and the derating design is carried out, and the time t2 is about a few ms. The short-circuit protection waveforms in this case are shown in fig. 4.

3. Meaning at time t 3.

Because the current-limiting loop adopts the RC circuit to carry out current-limiting charging on the capacitive load, when the capacitive load is a resistive capacitive load, the current-limiting resistor and the capacitive load resistor can carry out voltage division, so that the capacitive load cannot be charged to the power input voltage. t3 is designed mainly to finish RC current limiting charging in advance, and the capacitive load is filled by using a low-impedance path of the main loop. And comparing the voltage of the capacitive load with the voltage at two ends of the MOSFET through a second comparison unit at the time t3, and judging the type of the capacitive load again. If the voltage Vbc of the capacitive load is larger than the voltage Vab at two ends of the MOSFET, the capacitive load is judged, the current limiting loop is closed at the time t3, the main loop is opened, the output signal of the current comparison unit is shielded until the time t4, and the capacitive load is fully filled by the MOSFET of the main loop. When Vbc is smaller than Vab, judging that the capacitive load is not applied, and delaying until the time t4, closing the current-limiting loop and opening the main loop. And if the capacitive load current is larger than the short circuit threshold value, immediately executing short circuit protection, and cutting off the current limiting loop and the main loop. If the capacitive load current is less than the short circuit threshold after switching to the main loop, the main loop is always on.

4. Meaning at time t 4.

The meaning of the t4 design is used for controlling and protecting the solid state power controller when the capacitive load is in a special condition (such as a short circuit of the capacitive load to the ground when the low power voltage is input). The protection waveform is shown in fig. 5. If the capacitive load is judged to be a non-capacitive load at the time t3, the current-limiting loop is closed and the main loop is opened after time delay to the time t 4. And if the capacitive load current is larger than the short circuit threshold value, immediately executing short circuit protection, and cutting off the current limiting loop and the main loop. If the capacitive load current is less than the short circuit threshold after switching to the main loop, the main loop is always on.

After verification, the direct current solid state power controller can meet the load demand of a large capacitive load after the invention is adopted in the system, and the judgment of the capacitive load and the short circuit can be completed when the capacitive load is short-circuited to ground during low-power voltage input. Compared with the prior art, the beneficial effects are as follows: the capacitive load capacity, the capacitive load adaptability and the hardware reliability of the 270V high-voltage direct-current solid-state power controller are improved.

While only embodiments of the invention have been shown and described in detail, it is not intended that the scope of the invention be limited thereby. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (2)

1. A capacitive load circuit in a high voltage dc solid state power controller, comprising: the device comprises a power input, a controller main loop, a controller current-limiting loop, a sampling resistor, a freewheeling diode, a capacitive load, a power ground terminal, a singlechip, a logic unit, a current comparison unit and a second comparison unit; the controller main loop includes: a transistor MOSFET1; the controller current limiting loop comprises: a transistor MOSFET2, a current limiting resistor; the transistor MOSFET1 is connected in series between the power input and the power output, the transistor MOSFET2 and the current limiting resistor are also connected in series between the power input and the power output, and the sampling resistor and the capacitive load are connected in series between the power output and the power ground; the sampling resistor is used for sampling the passing current of the capacitive load; the first comparison unit is used for comparing the passing current of the capacitive load with a short-circuit threshold current; the first output of the logic unit is connected with the control end of the transistor MOSFET1 of the controller main loop, the first output of the logic unit is used for outputting a first control signal, and the transistor MOSFET1 is selectively turned on or turned off according to the first control signal; the second output of the logic unit is connected with the control end of the transistor MOSFET2 of the current-limiting loop of the controller, the second output of the logic unit is used for outputting a second control signal, and the transistor MOSFET2 is selectively turned on or turned off according to the second control signal; the singlechip is connected with the logic unit, and the logic unit is respectively connected with the control end of the transistor MOSFET1, the control end of the transistor MOSFET2, the first comparison unit and the second comparison unit; the second comparing unit is used for comparing the voltage at two ends of the transistor MOSFET1 with the voltage at two ends of the capacitive load; the logic unit judges the short circuit and the capacitive load according to the judging result of the first comparing unit and the judging result of the second comparing unit and determines that the transistor MOSFET1 and the transistor MOSFET2 are turned on or turned off according to the judging result.

2. A method for loading a capacitive load in a high voltage dc solid state power controller based on the capacitive load loading circuit of claim 1, the method comprising:

Step S1, the singlechip receives an external opening instruction, wherein the opening instruction is transmitted to the singlechip through a communication bus and is used for requesting the singlechip to open the main loop of the controller;

Step S2, the singlechip controls the transistor MOSFET1 of the main loop of the controller to be conducted and the transistor MOSFET2 of the current-limiting loop of the controller to be turned off through the logic unit, so that the main loop of the controller is communicated with the power input and the power output;

Step S3, the first comparing unit compares the passing current of the capacitive load with the magnitude of the short-circuit threshold current I1: if the capacitive load passing current is greater than the short-circuit threshold current I1, entering a step S5; if not, entering step S4;

step S4, the capacitive load is normally turned on; returning to the step S3;

step S5, the first comparison unit sends the comparison result to the logic unit for latching, and delay logic in the logic unit is started;

Step S6, opening the controller current limiting loop, and closing the controller main loop: the first control signal is configured as an off signal and the second control signal is configured as an on signal such that the transistor MOSFET1 of the controller main loop is off and the transistor MOSFET2 of the controller current limiting loop is on;

Step S7, delaying until t1, where the first comparing unit compares the passing current of the capacitive load with the short-circuit threshold I1 again: if the capacitive load passing current is greater than the short-circuit threshold current I, where i=i1, then step S14 is entered; if not, entering step S8;

Step S8, delaying until t2, wherein the short-circuit threshold current I is replaced by I2 from I1, wherein I1 is more than I2; the logic unit outputs an excitation signal to the first comparison unit, and when the first comparison unit receives the excitation signal from the first comparison unit, the first comparison unit configures the short-circuit threshold current I to be I2;

step S9, the first comparing unit compares the passing current of the capacitive load with the short-circuit threshold current I (i.e. i=i2): if the capacitive load passing current is greater than the short-circuit threshold current I, proceeding to step S15; if not, the step S10 is carried out;

Step S10, delaying until t3, comparing the voltage Vab across the transistor MOSFET1 in the main loop with the voltage Vbc across the capacitive load: if Vab < Vbc, go to step S11; if not, the step S13 is carried out;

Step S11, at the time t3, opening the main loop of the controller, closing the current-limiting loop of the controller, fully charging the capacitive load by the power input, shielding the output of the first comparison unit to the time t4, and normally opening the capacitive load;

Step S12, the delay logic in the logic unit is restored to an initial state, the output of the excitation signal is canceled, and the step S3 is returned;

Step S13, delay until t4, open the said controller main loop, close the said controller current-limiting loop, enter step S12, if the capacitive load current exceeds the said current threshold I1 again, report the short circuit, then carry out step 12;

Step S14, closing the controller main loop and the controller current limiting loop, and performing short-circuit protection on the capacitive load: at the moment, the capacitive load is judged to be short circuit, and meanwhile, a short circuit signal is latched and sent to an external interrupt pin of the singlechip for reclosing timing; step S16 is entered;

Step S15, canceling the excitation signal; the short-circuit threshold current I is replaced by I1 from I2, and the step S14 is returned;

step S16, the singlechip receives an external interrupt signal to enter an external interrupt service routine, and then step S17 is executed;

step S17, recording the interrupt times in an external interrupt service routine, starting an internal timer, and then executing step S18;

step S18, judging whether the singlechip enters an external interrupt service routine for the first time: if yes, go to step S19; if not, judging that the circuit is short-circuited again, and executing the step S23;

Step S19, after the timer in the singlechip counts the time interval reaching the reclosing requirement, outputting an unlocking signal to the logic unit to unlock the short-circuit signal, opening the main loop to reclose, and then executing step S20;

Step S20, after reclosing, comparing the capacitive load current with a short-circuit threshold I1 through a current comparison unit again; if the capacitive load current is greater than the short-circuit threshold value I1, executing the step S14, otherwise executing the step S21;

step S21, the singlechip clears the record of the interruption times, the capacitive load is normally turned on, and the step S3 is returned;

Step S22, the singlechip clears the record of the interruption times, returns to step S1, and completes the discrimination process of the whole capacitive load and the capacitive load short circuit;

And S23, reporting and latching a short-circuit state by the singlechip through the communication bus, sending a closing instruction to the logic unit, closing the capacitive load, recovering the initial state by delay logic in the logic unit, waiting for receiving a reset command to clear the short-circuit state, and returning to the step S22.