CN111430293A - Method for manufacturing shallow trench isolation structure - Google Patents
Method for manufacturing shallow trench isolation structure Download PDFInfo
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- CN111430293A CN111430293A CN202010351962.7A CN202010351962A CN111430293A CN 111430293 A CN111430293 A CN 111430293A CN 202010351962 A CN202010351962 A CN 202010351962A CN 111430293 A CN111430293 A CN 111430293A
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- 238000002955 isolation Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims description 54
- 229910052796 boron Inorganic materials 0.000 claims abstract description 107
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 239000007789 gas Substances 0.000 claims abstract description 53
- 238000000137 annealing Methods 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000001301 oxygen Substances 0.000 claims abstract description 13
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 29
- -1 boron halide Chemical class 0.000 claims description 22
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 14
- 230000008569 process Effects 0.000 description 21
- 238000005468 ion implantation Methods 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- YMEKEHSRPZAOGO-UHFFFAOYSA-N boron triiodide Chemical compound IB(I)I YMEKEHSRPZAOGO-UHFFFAOYSA-N 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-M Bromide Chemical compound [Br-] CPELXLSAUQHCOX-UHFFFAOYSA-M 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229940006460 bromide ion Drugs 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- XMBWDFGMSWQBCA-UHFFFAOYSA-M iodide Chemical compound [I-] XMBWDFGMSWQBCA-UHFFFAOYSA-M 0.000 description 1
- 229940006461 iodide ion Drugs 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000002277 temperature effect Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The embodiment of the invention provides a manufacturing method of a Shallow Trench Isolation (STI) structure, which provides a substrate structure; the base structure comprises at least a substrate; etching the substrate structure to remove part of the substrate structure, thereby forming a groove in the substrate structure; annealing the substrate structure with the groove in the first gas atmosphere to dope boron on the side wall and the bottom of the groove; the first gas comprises a boron source-containing gas and oxygen; an insulating layer is formed in the boron-doped trench. Therefore, the effect of better improving the double hump phenomenon in the Id-Vg curve can be achieved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a shallow trench isolation structure.
Background
In semiconductor Integrated Circuit (IC) devices, Shallow Trench Isolation (STI) structures are typically used as isolation regions to enable the various discrete circuit elements included in the IC device to operate independently. In a Metal-oxide semiconductor Field Effect Transistor (MOS) device prepared based on a shallow trench isolation process, as shown in fig. 1, in the width direction of the MOS device, a gate covers a part of an STI structure, and under the condition of applying a gate voltage (Vg), an electric Field at the edge of the gate is terminated at the side of a channel, so that the electric Field at the edge of the channel, which is close to the STI structure, is increased, and the depletion layer at the edge of the channel is deeper due to the electric Field, so that the edge of the channel is turned on in advance, and a double hump (Id-Vg curved double hump) phenomenon appears on an Id-Vg curve. At this time, the threshold voltages of the MOS devices are not uniform at different positions, and the leakage current of the MOS devices is also increased.
In the related art, boron doping is performed on STI by ion implantation to improve the double hump phenomenon in the Id-Vg curve, however, the improvement effect is limited.
Disclosure of Invention
In order to solve the related technical problems, embodiments of the present invention provide a method for manufacturing an STI structure, which can achieve a better effect of improving a double hump phenomenon in an Id-Vg curve.
The technical scheme of the embodiment of the invention is realized as follows:
the embodiment of the invention provides a manufacturing method of an STI structure, which comprises the following steps:
providing a substrate structure; the base structure comprises at least a substrate;
etching the substrate structure to remove part of the substrate structure, thereby forming a groove in the substrate structure;
annealing the substrate structure with the groove in the first gas atmosphere to dope boron on the side wall and the bottom of the groove; the first gas comprises a boron source-containing gas and oxygen;
an insulating layer is formed in the boron-doped trench.
In the above aspect, the boron source-containing gas includes: a boron halide gas.
In the above scheme, the boron halide gas includes: boron tribromide.
In the above scheme, the method further comprises:
and controlling the flow rate of the introduced first gas, the annealing temperature and the annealing duration so as to enable the boron doping depth on the side wall and the bottom of the groove to meet the preset depth condition.
In the scheme, the flow rate of the introduced first gas during annealing is 0.1L/min-2L/min, the annealing temperature is 600-1000 ℃, and the annealing time duration is 2 s-60 min.
In the above scheme, the method further comprises:
annealing the substrate structure with the groove formed in the first gas atmosphere, and then forming a barrier layer in the groove doped with boron, wherein the barrier layer covers the side wall and the bottom of the groove;
and forming the insulating layer in the groove with the barrier layer.
In the above scheme, the material of the barrier layer includes silicon nitride.
In the above aspect, the step of providing a substrate structure includes:
providing a substrate;
an oxide layer and a nitride layer are sequentially formed on the substrate.
In the above scheme, the material of the oxide layer includes silicon dioxide, and the material of the nitride layer includes silicon nitride.
In the foregoing aspect, the step of forming the insulating layer in the boron-doped trench includes:
filling an isolation material into the groove subjected to boron doping; the isolation material comprises silicon dioxide;
and carrying out planarization treatment on the filled isolation material to form the insulating layer.
The STI structure manufacturing method provided by the embodiment of the invention provides a substrate structure; the base structure comprises at least a substrate; etching the substrate structure to remove part of the substrate structure, thereby forming a groove in the substrate structure; annealing the substrate structure with the groove in the first gas atmosphere to dope boron on the side wall and the bottom of the groove; the first gas comprises a boron source-containing gas and oxygen; an insulating layer is formed in the boron-doped trench. In the embodiment of the invention, when the side wall and the bottom of the trench of the STI structure are doped with boron, a boron doped region is formed in the preset depth from the side wall of the trench of the STI structure to the substrate in a mode of annealing the substrate structure formed with the trench in the atmosphere of gas containing a boron source and oxygen, the boron doped region is positioned in the edge region of the trench, and the doped boron ions can improve the problem of early conduction of the edge region of the trench, so that the effect of improving the double hump phenomenon in the Id-Vg curve is achieved. Meanwhile, the boron doping mode provided by the embodiment of the invention is isotropic doping, compared with an ion implantation mode in the related technology, the boron doping on the side wall and the bottom of the groove is more uniform, the full coverage of the doped boron ions on the side wall of the groove of the STI structure can be realized, and the effect of better improving the double hump phenomenon in an Id-Vg curve can be achieved
Drawings
FIG. 1 is a schematic cross-sectional view of a gate, a trench and an STI structure in the width direction of a MOS device;
FIGS. 2 a-2 e are schematic cross-sectional views of STI structure fabrication methods provided in the related art at different stages of fabrication;
FIG. 3 is a diagram illustrating the Id-Vg curve of a MOS device with a double hump phenomenon varying with bias voltage in the related art;
FIG. 4 is a schematic diagram of the location of the AA corner in a MOS device;
FIG. 5 is a schematic flow chart illustrating an implementation of a method for fabricating an STI structure according to an embodiment of the present invention;
fig. 6a to 6e are schematic cross-sectional structures of different stages of a method for fabricating an STI structure according to an embodiment of the invention.
Description of reference numerals:
1-a substrate; 2-an oxide layer; a 3-nitride layer; 4-a trench of the STI structure; a boron doped region in a trench of the 4' -STI structure; 5-an isolating material; 6-insulating layer.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the following will describe specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.
IC devices are typically fabricated on a substrate and include a plurality of discrete circuit elements. In order to enable each discrete circuit element to function independently, it is necessary to first fabricate the substrate as an Active Area (AA) isolated from each other, and then fabricate discrete circuit elements in the AA. STI structures are used to isolate AA. Typical discrete circuit elements are MOS devices. The structure of the MOS device comprises: AA. A source, a drain and a gate; AA is positioned in the substrate, the grid electrode is positioned above the AA, the AA on two sides of the grid electrode is respectively subjected to ion implantation to form a source electrode and a drain electrode, and PN junctions are formed at the interfaces between the source electrode and the substrate and between the drain electrode and the substrate. After the MOS device is applied with voltage, a conductive channel is formed below the grid due to the action of an electric field. Fig. 1 shows a cross-sectional structure diagram of a gate, a channel and an STI structure in the width direction of a MOS device, which has been described above and causes a double hump phenomenon in an Id-Vg curve.
In the related art, the method for improving the double hump phenomenon includes: the STI is doped with boron through ion implantation, so that a boron doped region is formed in the preset depth from the side wall of the groove of the STI structure to the substrate, the boron doped region is positioned in the edge region of the channel, and the doped boron ions can solve the problem that the edge region of the channel is conducted in advance, thereby achieving the effect of improving the double hump phenomenon of the Id-Vg curve.
In the related art, the steps of the method for fabricating the STI structure are as follows:
first, referring to fig. 2a, an oxide layer 2 and a nitride layer 3 are sequentially formed on a substrate 1; next, referring to fig. 2b, a patterning process is performed through a photolithography process and an etching process to form a trench 4 of an STI structure in the substrate 1 via the nitride layer 3 and the oxide layer 2; next, referring to fig. 2c, boron doping is performed on the sidewall and the bottom surface of the trench 4 through an ion implantation process; next, referring to fig. 2d, filling of an isolation material 5 is performed in the boron doped STI trench 4; finally, referring to fig. 2e, the filled isolation material 5 is planarized to obtain an insulating layer 6 and an STI structure is formed. The substrate 1 may include a silicon substrate, among others. The nitride layer 3 and the oxide layer 2 may be used as a mask layer for etching to form the STI trenches 4 and as a stop layer for a subsequent planarization process, which may optionally be removed or remain after filling to complete the STI structure. The STI isolation material 5 is preferably an oxide insulating material, and the planarization process is preferably a Chemical Mechanical Polishing (CMP) process.
It should be noted that, in the example application, the trench 4 formed by the etching process has a large top dimension and a small bottom dimension, that is, the sidewall of the trench 4 is a slope, and when boron doping is performed on the sidewall of the trench 4 by the ion implantation process, when the implanted ions bombard the sidewall and the bottom of the trench 4 in a direction perpendicular to the bottom of the trench 4, the boron doping on the sidewall of the trench 4 near the top is less, or even no boron doping.
Meanwhile, fig. 3 shows a set of Id-Vg curves of a MOS device with a double hump phenomenon as a function of bias voltage (english may be expressed as body bias). Further analysis of the Id-Vg curve revealed: when the bias voltage (Vb) is low, the channel edge region can be opened, the Id-Vg curve is not smooth, and two humps exist, which indicates that leakage current can increase in the voltage threshold region and errors can be caused in modeling. When the bias is increased, the depletion region expands downward, causing the channel edge region to close, thereby smoothing the Id-Vg curve. That is, when the bias voltage is low, the processing of the AA corner area (here, the AA corner area is as the dotted circle area in fig. 4) is particularly critical. In order to smooth the Id-Vg curve at low bias voltage, it is necessary to improve the AA etching process to make the AA corner region smoother, or improve the STI doping process to make the AA corner region capable of receiving boron ion implantation. In practical application, it is often difficult to improve the AA etching process to make the AA corner regions smoother.
From the above analysis, it can be seen that, in the related art, when the STI is doped with boron by ion implantation, as the sidewall of the trench 4 of the STI structure becomes steeper and steeper as the width of the trench 4 decreases, the bombardment difficulty becomes greater and less boron ions are available for bombarding the corner area of AA, so that the improvement effect on the double hump phenomenon is limited.
In the related art, the method for improving the double hump phenomenon further comprises the following steps: adding an STI silicon nitride liner layer, or growing gate oxide layers with different thicknesses for multiple times, and the like. However, these methods require additional masks or other processing steps, which are costly.
Based on this, in various embodiments of the present invention, when boron doping is performed on the sidewall and the bottom of the trench of the STI structure, a boron doped region is formed in a preset depth from the sidewall of the trench of the STI structure to the substrate in a manner of annealing the substrate structure formed with the trench in an atmosphere containing a boron-containing source gas and oxygen, the boron doped region is located in a channel edge region, and the doped boron ions can improve the problem of early conduction of the channel edge region, thereby achieving an effect of improving a double hump phenomenon in an Id-Vg curve. Meanwhile, the boron doping mode provided by the embodiment of the invention is isotropic doping, compared with the ion implantation mode in the related technology, the boron doping on the side wall and the bottom of the groove is more uniform, and the full coverage of the doped boron ions on the side wall of the groove of the STI structure can be realized, so that the better improvement effect in the related technology is achieved. On the other hand, compared with the related art in which an STI silicon nitride liner layer is added or gate oxide layers with different thicknesses are grown for multiple times, the boron doping method in the embodiment of the invention does not need to add extra process steps such as a mask and the like, so that the effect of better improving the double hump phenomenon can be achieved on the premise of not adding extra process steps.
An embodiment of the present invention provides a method for manufacturing an STI structure, and fig. 5 is a schematic flow chart illustrating an implementation of the method for manufacturing an STI structure according to the embodiment of the present invention. As shown in fig. 5, the method comprises the steps of:
step 501: providing a substrate structure; the base structure comprises at least a substrate;
step 502: etching the substrate structure to remove part of the substrate structure, thereby forming a groove in the substrate structure;
step 503: annealing the substrate structure with the groove in the first gas atmosphere to dope boron on the side wall and the bottom of the groove; the first gas comprises a boron source-containing gas and oxygen;
step 504: an insulating layer is formed in the boron-doped trench.
Embodiments of the invention are described in further detail below with reference to schematic cross-sectional views of device structures during fabrication (fig. 6a-6 e).
In step 501, as shown in fig. 6a, the base structure at least comprises: a substrate 1. In practice, the substrate 1 may comprise at least one elemental semiconductor material, such as silicon (Si) or germanium (Ge), or other semiconductor materials known in the art.
In some embodiments, the step of providing a base structure comprises:
providing a substrate 1;
an oxide layer 2 and a nitride layer 3 are sequentially formed on the substrate 1.
In practice, the oxide layer 2 and the nitride layer 3 formed on the substrate in sequence may be formed by Chemical Vapor Deposition (CVD) or Atomic layer Deposition (A L D, Atomic L a layer Deposition), or the like.
Wherein, in some embodiments, the material of the oxide layer 2 comprises silicon dioxide, and the material of the nitride layer 3 comprises silicon nitride.
In step 502, as shown in fig. 6b, in practical applications, when the base structure only includes the substrate 1, a mask layer needs to be formed on the substrate first, and then etching is performed by using the mask layer, so as to form the trench 4. When the oxide layer 2 and the nitride layer 3 are included in the substrate structure, the oxide layer 2 and the nitride layer 3 may be used as a mask layer for etching to form the STI trench 4.
In practical application, the etching may be dry etching, wherein an etching gas containing a fluorine source is used in the step of dry etching. In some embodiments, the dry etching may be plasma etching, and the etching gas may be CF4Or CHF3Or other etching gases known in the art that may be used to etch the base structure.
The inventors found that in the related art, boron doping is performed on the side wall of the trench of the STI structure by ion implantation because the ion implantation is performed in an anisotropic manner, i.e., the gate ions doped on the plane perpendicular to the ion implantation direction are the most, while the gate ions doped on the other planes not perpendicular to the ion implantation direction are relatively less, so that the boron doping on the side wall of the trench of the STI structure is difficult to achieve full coverage, and especially in the AA corner region, the boron doping is very little. Based on this, in the embodiment of the present invention, isotropic doping is performed on the sidewall of the trench of the STI structure by annealing under a specific atmosphere and a specific temperature condition, so that full coverage of boron doping on the sidewall of the trench of the STI structure is achieved.
Research aiming at specific atmosphere and temperature shows that boron halide can be used as a boron impurity source in a substrate (such as a silicon substrate). In practical application, boron tribromide (BBr)3) For example, the chemical equation for the reaction of boron tribromide, oxygen and silicon is as follows:
4BBr3(g)+3O2(g)→2B2O3(l)+6Br2(g)
2B2O3(l)+3Si(s)→4B(s)+3SiO2(s)
as can be seen from the above chemical reaction, boron tribromide can be replaced by oxygen (O)2) Oxidation to diboron trioxide (B)2O3) The diboron trioxide can then be reacted with silicon to give boron. In addition, the generated silicon dioxide is also the same as the insulating layer material formed in the trench of the STI structure, and an additional process is not needed for removing. Meanwhile, in order to facilitate the reaction, it is necessary to perform the above reaction in a high temperature environment.
Based on this, in step 503, the substrate structure formed with the trench 4 may be annealed in an atmosphere containing a boron-containing source gas and oxygen to perform isotropic boron doping on the sidewall and the bottom of the trench 4, so as to achieve full coverage of boron doping on the sidewall of the trench of the STI structure. A schematic diagram of the isotropic boron doping of the sidewalls and bottom of the trench 4 is shown in fig. 6 c.
It should be noted that, during the boron doping, a masking process is required for an exposed region of a substrate, such as a silicon substrate, which does not need to be doped with boron. Such as the oxide layer 2 and the nitride layer 3 on the upper surface of the substrate, may be applied to the masked upper surface of the substrate.
In some embodiments, the boron source-containing gas comprises: a boron halide gas.
In practical application, bromide ion (Br) in boron tribromide in boron halide—) And iodide ion (I) in boron triiodide—) Is more oxidizing than oxygen (O)2) Is weakly oxidizing, and thus, both boron tribromide and boron triiodide can be oxidized to diboron trioxide (B)2O3) Thereby realizing boron doping of the substrate.
Preferably, the boron source-containing gas comprises: boron tribromide.
In practice, the molar ratio of the boron halide gas to the oxygen gas in the first gas may be between 4:3 and 3: 3.
Preferably, the molar ratio of the boron halide gas to the oxygen gas is 4: 3.
In practical applications, the purpose of boron doping the sidewall of the trench 4 of the STI structure is to form a boron doped region 4 '(where the boron doped region 4' is shown in fig. 6 d) in a preset depth from the sidewall of the trench 4 of the STI structure to the substrate 1, and in order to prevent the channel edge region from turning on in advance, the depth of the boron doped region 4 'needs to be controlled so that the boron doped region 4' includes the channel edge region. Meanwhile, the depth of the boron doped region 4' cannot be too deep, and should be controlled so as not to affect other parameters on the substrate.
Based on this, in some embodiments, the method further comprises:
and controlling the flow rate of the introduced first gas, the annealing temperature and the annealing duration so as to enable the boron doping depth on the side wall and the bottom of the groove to meet the preset depth condition.
In some embodiments, the flow rate of the first gas introduced during annealing is 0.1L/min-2L/min, the annealing temperature is 600 ℃ to 1000 ℃, and the annealing time is 2 s-60 min.
In some embodiments, the first gas may be introduced at a slower flow rate, such as 0.1L/min, at a lower annealing temperature, such as 600 deg.C, for a longer annealing time, such as 60 min.
In some embodiments, the first gas may be introduced at a faster flow rate, such as 2L/min, where a higher annealing temperature, such as 1000 deg.C, may be used, and a shorter annealing duration, such as 2 seconds, may be used.
In other embodiments, the first gas may be introduced at an intermediate flow rate, such as 0.5L/min, at which time an appropriate annealing temperature, such as 700 deg.C, may be used, and for an appropriate annealing duration, such as 40 min.
In other embodiments, the first gas may be introduced at an intermediate flow rate, such as 1L/min, where an appropriate annealing temperature, such as 800 deg.C, may be used, and an appropriate annealing duration, such as 10min may be used.
In other embodiments, the first gas may be introduced at an intermediate flow rate, such as 1.5L/min, where an appropriate annealing temperature, such as 900 deg.C, may be used, and an appropriate annealing duration, such as 1min, may be used.
In practice, the combination of the flow rate of the first gas, the annealing temperature and the annealing time is not limited to the above-mentioned embodiments, and those skilled in the art will understand that the flow rate of the first gas, the annealing temperature and the annealing time can be adjusted within a reasonable range.
In step 504, an insulating layer 6 is formed mainly in the boron doped trench 4, as shown in fig. 6 e.
In some embodiments, the step of forming the insulating layer 6 in the boron-doped trench includes:
filling an isolation material into the groove in the boron-doped groove; the isolation material comprises silicon dioxide;
the filled isolation material is subjected to planarization processing to form the insulating layer 6.
In practice, the isolation material may be CVD or a L D, etc. the deposited isolation material fills the shallow trenches and is deposited on the nitride layer 3.
Wherein, in some embodiments, the step of planarizing the filled isolation material comprises:
the top surface of the filled isolation material is planarized by a CMP process.
In practical applications, the nitride layer 3 may be used as a stop layer for the CMP process when performing the planarization process.
In practical application, after the STI structure is formed, due to the high temperature effect of the thermal treatment processes such as thermal oxidation and annealing in the subsequent process, boron ions in the boron doped region 4 'may diffuse into the shallow trench isolation structure, thereby causing boron loss in the boron doped region 4'. When the boron loss is serious, a double hump phenomenon occurs. At this time, a barrier layer may be formed in the boron-doped trench to block the possible gate diffusion.
Based on this, in some embodiments, the method further comprises:
annealing the substrate structure with the groove formed in the first gas atmosphere, and then forming a barrier layer in the groove doped with boron, wherein the barrier layer covers the side wall and the bottom of the groove;
the insulating layer 6 is formed in the trench in which the barrier layer is formed.
Wherein, in some embodiments, the material of the barrier layer comprises silicon nitride.
In practical application, the barrier layer is used for locking boron ions in the boron doping region 4 'in a sealing mode, and the concentration of the boron ions in the boron doping region 4' is kept, so that the barrier layer can prevent the boron ions injected into the boron doping region 4 'from diffusing into the shallow trench isolation in the subsequent annealing process, the concentration of the boron ions in the boron doping region 4' is kept, and the double hump phenomenon caused by the reduction of the concentration of the boron ions is avoided.
The STI structure manufacturing method provided by the embodiment of the invention provides a substrate structure; the base structure comprises at least a substrate; etching the substrate structure to remove part of the substrate structure, thereby forming a groove in the substrate structure; annealing the substrate structure with the groove in the first gas atmosphere to dope boron on the side wall and the bottom of the groove; the first gas comprises a boron source-containing gas and oxygen; an insulating layer is formed in the boron-doped trench. In the embodiment of the invention, when the side wall and the bottom of the trench of the STI structure are doped with boron, a boron doped region is formed in the preset depth from the side wall of the trench of the STI structure to the substrate in a mode of annealing the substrate structure formed with the trench in the atmosphere of gas containing a boron source and oxygen, the boron doped region is positioned in the edge region of the trench, and the doped boron ions can improve the problem of early conduction of the edge region of the trench, so that the effect of improving the double hump phenomenon in the Id-Vg curve is achieved. Meanwhile, the boron doping mode provided by the embodiment of the invention is isotropic doping, compared with the ion implantation mode in the related technology, the boron doping on the side wall and the bottom of the groove is more uniform, and the full coverage of the doped boron ions on the side wall of the groove of the STI structure can be realized, so that the better improvement effect in the related technology is achieved.
On the other hand, compared with the related art in which an STI silicon nitride liner layer is added or gate oxide layers with different thicknesses are grown for multiple times, the boron doping method in the embodiment of the invention does not need to add extra process steps such as a mask and the like, so that the effect of better improving the double hump phenomenon can be achieved on the premise of not adding extra process steps.
In addition, the STI structure manufacturing method implemented by the invention is simple and feasible, and can be suitable for any MOS process using the STI structure. The double hump phenomenon is improved, and the leakage current can be reduced, so that the isolation effect among the separated circuit elements in the IC device is improved.
It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (10)
1. A method for manufacturing a shallow trench isolation structure is characterized by comprising the following steps:
providing a substrate structure; the base structure comprises at least a substrate;
etching the substrate structure to remove part of the substrate structure, thereby forming a groove in the substrate structure;
annealing the substrate structure with the groove in the first gas atmosphere to dope boron on the side wall and the bottom of the groove; the first gas comprises a boron source-containing gas and oxygen;
an insulating layer is formed in the boron-doped trench.
2. The method of claim 1, wherein the boron source-containing gas comprises: a boron halide gas.
3. The method of claim 2, wherein the boron halide gas comprises: boron tribromide.
4. The method of claim 1, further comprising:
and controlling the flow rate of the introduced first gas, the annealing temperature and the annealing duration so as to enable the boron doping depth on the side wall and the bottom of the groove to meet the preset depth condition.
5. The method as claimed in claim 4, wherein the flow rate of the first gas is 0.1L/min-2L/min, the temperature of the annealing is 600 ℃ to 1000 ℃, and the time of the annealing is 2 s-60 min.
6. The method of claim 1, further comprising:
annealing the substrate structure with the groove formed in the first gas atmosphere, and then forming a barrier layer in the groove doped with boron, wherein the barrier layer covers the side wall and the bottom of the groove;
and forming the insulating layer in the groove with the barrier layer.
7. The method of claim 6, wherein the material of the barrier layer comprises silicon nitride.
8. The method of claim 1, wherein the step of providing a base structure comprises:
providing a substrate;
an oxide layer and a nitride layer are sequentially formed on the substrate.
9. The method of claim 8, wherein the material of the oxide layer comprises silicon dioxide and the material of the nitride layer comprises silicon nitride.
10. The method of claim 1, wherein the step of forming an insulating layer in the boron-doped trench comprises:
filling an isolation material into the groove subjected to boron doping; the isolation material comprises silicon dioxide;
and carrying out planarization treatment on the filled isolation material to form the insulating layer.
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Application publication date: 20200717 |