CN111416585A - CMOS transconductance unit circuit based on self-adaptive bias - Google Patents
CMOS transconductance unit circuit based on self-adaptive bias Download PDFInfo
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Abstract
The invention discloses a self-adaptive bias-based CMOS transconductance unit circuit, which provides relatively constant bias current for a transconductance unit main body circuit in a wide voltage range, and utilizes a relatively large voltage convolution space which is self-adaptively adjusted and reserved for grid voltage, wherein the bias voltage Vbias1 selects a relatively low value to enable a current source I1a to be just saturated, so that a PMOS tube M4a and a PMOS tube M5a can expand some input voltage ranges after entering a linear region along with the rise of input voltage until the PMOS tube M7a also enters the linear region.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to a CMOS transconductance unit circuit based on self-adaptive bias.
Background
With the rapid progress of CMOS manufacturing technology, the feature size of the device is continuously reduced, and the power supply voltage is also continuously reduced, so that the common mode input voltage of the transconductance unit implemented by using the classical differential pair is limited. In general, a source degeneration resistor is introduced into a differential structure to improve the linearity of a transconductance unit, on the basis of which the transconductance of an input MOS pair transistor is enhanced and the degeneration depth is increased, the linearity of the transconductance unit can be further improved, but the problem that the common-mode voltage range is limited is also faced. In modern wireless receiver design, the requirement on the input range of a transconductance unit is high, because a filter and a variable gain amplifier in a commonly adopted image rejection receiver based on a complex signal processing principle need to process signals and image signals simultaneously, which puts high input dynamic range requirements on the filter and the variable gain amplifier, namely, the common-mode input voltage range is wide and the linearity is high.
As shown in fig. 1, a conventional circuit structure of a high linearity transconductance unit based on the source degeneration-transconductance boosting principle is adopted, and a source voltage of a transistor M1 follows a change of an input voltage, so that the input voltage is converted into a current on a resistor R1+ R1, and most of the current is absorbed by the transistor M2 and mirrored to an output terminal through a current mirror circuit composed of transistors M2 and M3. The equivalent transconductance of the transconductance cell is equal to about 1/R1.
As shown in FIG. 2, the source voltage of the M1 transistor is equal to the input voltage, so that the input voltage can be loaded onto the resistor R1+ R1 to be converted into a current, and the current is buffered to the output terminal by the M1 transistor. The structure has much larger power consumption and circuit scale, and does not meet the requirements of increasingly complex and huge system on chip on low power consumption and compact area of a basic signal processing module (here, a transconductance unit).
The maximum common mode input voltage of the transconductance cells shown in fig. 1 and 2 can be expressed as: VDD-Vddsat-VGS 1, wherein VDD represents the power voltage, VGS1 represents the gate-source voltage of the M1 transistor, and Vddsat represents the saturation voltage drop of the current source (the M4 transistor in FIG. 1 is actually the current source). At present, the power supply voltage of the mainstream CMOS manufacturing process is reduced to 1.2V or even lower, the threshold voltage and the drain-source saturation voltage drop can not be reduced in proportion, and therefore, the space reserved for the input voltage is smaller and smaller. In fact, the common-mode input voltage does not reach this theoretical value (VDD-Vdsat-VGS1), because when the voltage drop of the current source (M4 in fig. 1 and IB1 in fig. 2) approaches Vdsat, its output impedance has begun to decrease greatly, resulting in a smaller equivalent resistance at the source of the input transistor M1 and thus a larger equivalent transconductance.
The applicant of the present patent has previously improved the above-mentioned problem (Z L201721486242.1 — a wide input voltage range and high linearity CMOS transconductance cell circuit), and the present patent is further optimized such that the current source (M4 transistor in fig. 1 and IB1 in fig. 2) connected to the resistor R1 has a lower dependence on the input voltage swing, which is achieved by the adaptive bias circuit.
Disclosure of Invention
The invention aims to provide a CMOS transconductance unit circuit based on self-adaptive bias, which can obtain a wider voltage input range and is very important characteristic for a nano-scale CMOS process, and simultaneously provides a transconductance main body circuit with very stable bias current, namely the bias current has very small dependence on input voltage, and the CMOS transconductance unit circuit is favorable for improving linearity.
The technical scheme of the invention is as follows: a CMOS transconductance unit circuit based on self-adaptive bias comprises a transconductance unit main body circuit and a self-adaptive bias current source;
the main circuit of the transconductance unit comprises a PMOS tube M1a, a PMOS tube M2a, a PMOS tube M3a, a PMOS tube M1b, a PMOS tube M2b, a PMOS tube M3b, a resistor 2R1, a current source I1a and a current source I1 b; the self-adaptive bias current source comprises a PMOS tube M4a, a PMOS tube M5a matched with a PMOS tube M4a, a PMOS tube M6a, a PMOS tube M7a, a PMOS tube M4b, a PMOS tube M5b matched with a PMOS tube M4b, a PMOS tube M6b, a PMOS tube M7b, a current source I2a, a current source I3a, a current source I2b and a current source I3b, wherein the PMOS tube M1a is mirror-symmetrical to the PMOS tube M1b, the PMOS tube M2a is mirror-symmetrical to the PMOS tube M2b, the PMOS tube M3a is mirror-symmetrical to the PMOS tube M3b, the PMOS tube M4a is mirror-symmetrical to the PMOS tube M4b, the PMOS tube M5a is mirror-symmetrical to the PMOS tube M5b, the PMOS tube M6a is mirror-symmetrical to the PMOS tube M6b, and the PMOS tube M7a is mirror-symmetrical to the PMOS tube M7 b;
the source electrode of the PMOS transistor M4a, the source electrode of the PMOS transistor M5a, the source electrode of the PMOS transistor M4b, the source electrode of the PMOS transistor M5b, the input end of the current source I3a and the input end of the current source I3b are all connected with a power supply VDD; the source electrode of the PMOS transistor M2a, the source electrode of the PMOS transistor M3a, the source electrode of the PMOS transistor M2b, the source electrode of the PMOS transistor M3b, the output end of the current source I1a, the output end of the current source I2a, the output end of the current source I1b and the output end of the current source I2b are all grounded;
the grid electrode of the PMOS transistor M4a is connected with the grid electrode of the PMOS transistor M5a and is connected with the drain electrode of the PMOS transistor M7a and the output end of the current source I3 a; the drain electrode of the PMOS tube M5a is connected with the source electrode of the PMOS tube M6a, the grid electrode of the PMOS tube M6a is connected with the grid electrode of the PMOS tube M1a and the input voltage Vin +, and the drain electrode of the PMOS tube M6a is connected with the source electrode of the PMOS tube M7a and the input end of the current source I2 a; the source electrode of the PMOS tube M1a is connected with the drain electrode of the PMOS tube M2a and the drain electrode of the PMOS tube M4a, the drain electrode of the PMOS tube M1a is connected with the input end of a current source I1a, the grid electrode of the PMOS tube M2a and the grid electrode of the PMOS tube M3a, and the drain electrode of the PMOS tube M3a is a current output end Iout +;
the grid electrode of the PMOS transistor M4b is connected with the grid electrode of the PMOS transistor M5b and is connected with the drain electrode of the PMOS transistor M7b and the output end of the current source I3 b; the drain electrode of the PMOS tube M5b is connected with the source electrode of the PMOS tube M6b, the grid electrode of the PMOS tube M6b is connected with the grid electrode of the PMOS tube M1b and the input voltage Vin-, and the drain electrode of the PMOS tube M6b is connected with the source electrode of the PMOS tube M7b and the input end of the current source I2 b; the source electrode of the PMOS tube M1b is connected with the drain electrode of the PMOS tube M2b and the drain electrode of the PMOS tube M4b, the drain electrode of the PMOS tube M1b is connected with the input end of a current source I1b, the grid electrode of the PMOS tube M2b and the grid electrode of the PMOS tube M3b, and the drain electrode of the PMOS tube M3b is a current output end Iout-;
a resistor 2R1 is arranged between a connection path of the PMOS tube M1a and the PMOS tube M4a and a connection path of the PMOS tube M1b and the PMOS tube M4b, and meanwhile, a grid electrode of the PMOS tube M7a and a grid electrode of the PMOS tube M7b are connected with a bias voltage Vbias 1.
As a preferable technical solution, the size ratio of the PMOS transistor M1a to the PMOS transistor M6a is equal to the ratio of the difference between the bias current of the current source I1a and the bias current of the current source I2a and the current source I3a, so as to ensure that the source voltage of the PMOS transistor M6a follows the source voltage change of the PMOS transistor M1 a.
As a preferable technical solution, the size ratio of the PMOS transistor M1b to the PMOS transistor M6b is equal to the ratio of the difference between the bias current of the current source I1b and the bias current of the current source I2b and the current source I3b, so as to ensure that the source voltage of the PMOS transistor M6b follows the source voltage change of the PMOS transistor M1 b.
The invention has the advantages that:
1. the CMOS transconductance unit circuit based on the self-adaptive bias can obtain a wider voltage input range, is very important for a nano-scale CMOS process, and simultaneously provides very stable bias current for the transconductance main body circuit, namely the bias current has very small dependence on input voltage, thereby being beneficial to improving the linearity.
Drawings
The invention is further described with reference to the following figures and examples:
fig. 1 is a circuit structure diagram of a high linearity transconductance unit based on a source degeneration-transconductance boosting principle;
FIG. 2 is a circuit block diagram of a more sophisticated implementation of a high linearity transconductance cell;
FIG. 3 is a circuit diagram of a CMOS transconductance unit based on adaptive bias according to the present invention;
fig. 4 is a simulation curve of the relationship between the equivalent transconductance and the input common mode voltage at an ac frequency of 1MHz according to the present invention and a comparison diagram with the conventional structure.
Detailed Description
Example (b): referring to fig. 3, a CMOS transconductance cell circuit based on adaptive bias includes a transconductance cell main circuit and an adaptive bias current source; the main circuit of the transconductance unit comprises a PMOS tube M1a, a PMOS tube M2a, a PMOS tube M3a, a PMOS tube M1b, a PMOS tube M2b, a PMOS tube M3b, a resistor 2R1, a current source I1a and a current source I1 b; the self-adaptive bias current source comprises a PMOS tube M4a, a PMOS tube M5a matched with a PMOS tube M4a, a PMOS tube M6a, a PMOS tube M7a, a PMOS tube M4b, a PMOS tube M5b matched with a PMOS tube M4b, a PMOS tube M6b, a PMOS tube M7b, a current source I2a, a current source I3a, a current source I2b and a current source I3b, wherein the PMOS tube M1a is mirror-symmetrical to the PMOS tube M1b, the PMOS tube M2a is mirror-symmetrical to the PMOS tube M2b, the PMOS tube M3a is mirror-symmetrical to the PMOS tube M3b, the PMOS tube M4a is mirror-symmetrical to the PMOS tube M4b, the PMOS tube M5a is mirror-symmetrical to the PMOS tube M5b, the PMOS tube M6a is mirror-symmetrical to the PMOS tube M6b, and the PMOS tube M7a is mirror-symmetrical to the PMOS tube M7 b;
the source electrode of the PMOS transistor M4a, the source electrode of the PMOS transistor M5a, the source electrode of the PMOS transistor M4b, the source electrode of the PMOS transistor M5b, the input end of the current source I3a and the input end of the current source I3b are all connected with a power supply VDD; the source electrode of the PMOS transistor M2a, the source electrode of the PMOS transistor M3a, the source electrode of the PMOS transistor M2b, the source electrode of the PMOS transistor M3b, the output end of the current source I1a, the output end of the current source I2a, the output end of the current source I1b and the output end of the current source I2b are all grounded;
the grid electrode of the PMOS transistor M4a is connected with the grid electrode of the PMOS transistor M5a and is connected with the drain electrode of the PMOS transistor M7a and the output end of the current source I3 a; the drain electrode of the PMOS tube M5a is connected with the source electrode of the PMOS tube M6a, the grid electrode of the PMOS tube M6a is connected with the grid electrode of the PMOS tube M1a and the input voltage Vin +, and the drain electrode of the PMOS tube M6a is connected with the source electrode of the PMOS tube M7a and the input end of the current source I2 a; the source electrode of the PMOS tube M1a is connected with the drain electrode of the PMOS tube M2a and the drain electrode of the PMOS tube M4a, the drain electrode of the PMOS tube M1a is connected with the input end of a current source I1a, the grid electrode of the PMOS tube M2a and the grid electrode of the PMOS tube M3a, and the drain electrode of the PMOS tube M3a is a current output end Iout +;
the grid electrode of the PMOS transistor M4b is connected with the grid electrode of the PMOS transistor M5b and is connected with the drain electrode of the PMOS transistor M7b and the output end of the current source I3 b; the drain electrode of the PMOS tube M5b is connected with the source electrode of the PMOS tube M6b, the grid electrode of the PMOS tube M6b is connected with the grid electrode of the PMOS tube M1b and the input voltage Vin-, and the drain electrode of the PMOS tube M6b is connected with the source electrode of the PMOS tube M7b and the input end of the current source I2 b; the source electrode of the PMOS tube M1b is connected with the drain electrode of the PMOS tube M2b and the drain electrode of the PMOS tube M4b, the drain electrode of the PMOS tube M1b is connected with the input end of a current source I1b, the grid electrode of the PMOS tube M2b and the grid electrode of the PMOS tube M3b, and the drain electrode of the PMOS tube M3b is a current output end Iout-;
a resistor 2R1 is arranged between a connection path of the PMOS tube M1a and the PMOS tube M4a and a connection path of the PMOS tube M1b and the PMOS tube M4b, and meanwhile, a grid electrode of the PMOS tube M7a and a grid electrode of the PMOS tube M7b are connected with a bias voltage Vbias 1.
The size ratio of the PMOS transistor M1a to the PMOS transistor M6a is equal to the ratio of the difference between the bias current of the current source I1a and the bias current of the current source I2a and the current source I3a, so as to ensure that the source voltage of the PMOS transistor M6a changes along with the source voltage of the PMOS transistor M1 a.
The size ratio of the PMOS transistor M1b to the PMOS transistor M6b is equal to the ratio of the difference between the bias current of the current source I1b and the bias current of the current source I2b and the current source I3b, so as to ensure that the source voltage of the PMOS transistor M6b changes along with the source voltage of the PMOS transistor M1 b.
The working principle of the invention is as follows: the source voltage of the PMOS transistor M6a (or the PMOS transistor M6b) of the present invention follows the source voltage change of the PMOS transistor M1a (or the PMOS transistor M1b), and further, as long as the PMOS transistor M4a (or the PMOS transistor M4b) is matched with the PMOS transistor M5a (or the PMOS transistor M5b), the bias current output by the PMOS transistor M4a (or the PMOS transistor M4b) is not affected by the drain voltage change (i.e., the input voltage change), because the gate voltage of the PMOS transistor M5a (or the PMOS transistor M5b) is automatically adjusted to make the bias current equal to the bias current of the current source I2a (or I2b), that is: as long as the NMOS transistor implementing the current source I2a (or the current source I2b) does not enter the linear region, the bias current of the PMOS transistor M4a (or the PMOS transistor M4b) is not affected by the input voltage variation.
As the input voltage increases, the PMOS transistor M4a and the PMOS transistor M5a first enter a linear region, and the gate voltages of the PMOS transistor M4a and the PMOS transistor M5a start to decrease significantly, but as long as the PMOS transistor M7a (or the PMOS transistor M7b) does not enter the linear region, the output voltage of I2a (i.e., the source voltage of the PMOS transistor M7a) is substantially constant, and I2a can still maintain a constant bias current, and further, the PMOS transistor M4a can still provide a constant bias current.
With further increase of the input voltage, the gate voltages of the PMOS transistor M4a and the PMOS transistor M5a drop sharply, so that the PMOS transistor M7a (or the PMOS transistor M7b) enters a linear region, the source voltage of the PMOS transistor M7a starts to drop significantly, so that the output current of I2a drops, and at this time, the PMOS transistor M4a can no longer provide a constant bias current. The invention fully utilizes the stage that the MOS tube initially enters the linear region, thereby obtaining a wider input voltage range.
From the viewpoint of small signals, since the common-gate stage (the PMOS transistor M7a) has a forward amplification effect, the voltage fluctuation amplitude of the gate voltage adaptive adjustment of the PMOS transistor M5a (or the PMOS transistor M5b) is very small, and the voltage fluctuation amplitude conducted to the source of the PMOS transistor M7a is very small, and the influence on the current source I2a is very small (compared with the previous patent Z L201721486242.1, a wide input voltage range and high linearity CMOS transconductance unit circuit), i.e., the PMOS transistor M4a can provide a more constant bias current.
Compared with the traditional high-linearity transconductance unit based on the source degeneration-transconductance boosting principle, the high-linearity transconductance unit builds a circuit under the 45nm CMOS process and the 1.2V power supply voltage and performs amplitude-frequency response simulation of equivalent transconductance. The larger the common mode input voltage range corresponding to the equivalent transconductance of the common mode input voltage transformer is kept unchanged, the wider the voltage input range is. The common mode input voltage was swept at an ac frequency of 1MHz to obtain figure 4.
Fig. 4 is a simulation curve (dashed line in the figure) of the relationship between the equivalent transconductance and the input common mode voltage at the ac frequency of 1MHz in the present invention, and is compared with the conventional structure (the solid line in the figure represents that the cascode current source is used to provide the bias current for the main circuit of the transconductance unit, and the dashed line in the figure represents that the single MOS transistor current source is used to provide the bias current for the main circuit of the transconductance unit). Simulation results show that the lower limit of the common mode input voltage range of the invention is the same as that of the conventional structure, and the upper limit of the common mode input voltage range is improved by about 120mV (the power supply voltage is 1.2V) compared with that of the conventional structure.
The equivalent transconductance of the conventional structure using a single MOS transistor current source to provide bias current for the main circuit of the transconductance cell is higher (dashed line in fig. 4) because the output impedance of the bias current source is very limited, and the parallel connection with R1 reduces the impedance seen by the source of the PMOS transistor M1a to ground. However, there is a large dependence of the output impedance of the bias current source on the input voltage, which leads to non-linear distortion.
From the above, the present invention has the characteristics of wide input voltage range and high linearity.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (3)
1. A CMOS transconductance unit circuit based on self-adaptive bias is characterized by comprising a transconductance unit main body circuit and a self-adaptive bias current source;
the main circuit of the transconductance unit comprises a PMOS tube M1a, a PMOS tube M2a, a PMOS tube M3a, a PMOS tube M1b, a PMOS tube M2b, a PMOS tube M3b, a resistor 2R1, a current source I1a and a current source I1 b; the self-adaptive bias current source comprises a PMOS tube M4a, a PMOS tube M5a matched with a PMOS tube M4a, a PMOS tube M6a, a PMOS tube M7a, a PMOS tube M4b, a PMOS tube M5b matched with a PMOS tube M4b, a PMOS tube M6b, a PMOS tube M7b, a current source I2a, a current source I3a, a current source I2b and a current source I3b, wherein the PMOS tube M1a is mirror-symmetrical to the PMOS tube M1b, the PMOS tube M2a is mirror-symmetrical to the PMOS tube M2b, the PMOS tube M3a is mirror-symmetrical to the PMOS tube M3b, the PMOS tube M4a is mirror-symmetrical to the PMOS tube M4b, the PMOS tube M5a is mirror-symmetrical to the PMOS tube M5b, the PMOS tube M6a is mirror-symmetrical to the PMOS tube M6b, and the PMOS tube M7a is mirror-symmetrical to the PMOS tube M7 b;
the source electrode of the PMOS transistor M4a, the source electrode of the PMOS transistor M5a, the source electrode of the PMOS transistor M4b, the source electrode of the PMOS transistor M5b, the input end of the current source I3a and the input end of the current source I3b are all connected with a power supply VDD; the source electrode of the PMOS transistor M2a, the source electrode of the PMOS transistor M3a, the source electrode of the PMOS transistor M2b, the source electrode of the PMOS transistor M3b, the output end of the current source I1a, the output end of the current source I2a, the output end of the current source I1b and the output end of the current source I2b are all grounded;
the grid electrode of the PMOS transistor M4a is connected with the grid electrode of the PMOS transistor M5a and is connected with the drain electrode of the PMOS transistor M7a and the output end of the current source I3 a; the drain electrode of the PMOS tube M5a is connected with the source electrode of the PMOS tube M6a, the grid electrode of the PMOS tube M6a is connected with the grid electrode of the PMOS tube M1a and the input voltage Vin +, and the drain electrode of the PMOS tube M6a is connected with the source electrode of the PMOS tube M7a and the input end of the current source I2 a; the source electrode of the PMOS tube M1a is connected with the drain electrode of the PMOS tube M2a and the drain electrode of the PMOS tube M4a, the drain electrode of the PMOS tube M1a is connected with the input end of a current source I1a, the grid electrode of the PMOS tube M2a and the grid electrode of the PMOS tube M3a, and the drain electrode of the PMOS tube M3a is a current output end Iout +;
the grid electrode of the PMOS transistor M4b is connected with the grid electrode of the PMOS transistor M5b and is connected with the drain electrode of the PMOS transistor M7b and the output end of the current source I3 b; the drain electrode of the PMOS tube M5b is connected with the source electrode of the PMOS tube M6b, the grid electrode of the PMOS tube M6b is connected with the grid electrode of the PMOS tube M1b and the input voltage Vin-, and the drain electrode of the PMOS tube M6b is connected with the source electrode of the PMOS tube M7b and the input end of the current source I2 b; the source electrode of the PMOS tube M1b is connected with the drain electrode of the PMOS tube M2b and the drain electrode of the PMOS tube M4b, the drain electrode of the PMOS tube M1b is connected with the input end of a current source I1b, the grid electrode of the PMOS tube M2b and the grid electrode of the PMOS tube M3b, and the drain electrode of the PMOS tube M3b is a current output end Iout-;
a resistor 2R1 is arranged between a connection path of the PMOS tube M1a and the PMOS tube M4a and a connection path of the PMOS tube M1b and the PMOS tube M4b, and meanwhile, a grid electrode of the PMOS tube M7a and a grid electrode of the PMOS tube M7b are connected with a bias voltage Vbias 1.
2. The adaptive bias based CMOS transconductance cell circuit of claim 1, wherein a size ratio of said PMOS transistor M1a to PMOS transistor M6a is equal to a ratio of a difference between a bias current of current source I1a and a bias current of current source I2a and current source I3 a.
3. The adaptive bias based CMOS transconductance cell circuit of claim 1, wherein a size ratio of said PMOS transistor M1b to PMOS transistor M6b is equal to a ratio of a difference between a bias current of current source I1b and a bias current of current source I2b and current source I3 b.
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