CN111415691B - SRAM memory cell - Google Patents
SRAM memory cell Download PDFInfo
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- CN111415691B CN111415691B CN202010134136.7A CN202010134136A CN111415691B CN 111415691 B CN111415691 B CN 111415691B CN 202010134136 A CN202010134136 A CN 202010134136A CN 111415691 B CN111415691 B CN 111415691B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
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Abstract
The present invention relates to a semiconductor integrated circuit, and more particularly, to an SRAM memory cell. The device comprises a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first transmission tube and a second transmission tube; the first end of the first transmission tube is connected with a first bit line, and the other end of the first transmission tube is connected with a first storage node; the first end of the second transmission tube is connected with a second bit line, and the other end of the second transmission tube is connected with a second storage node; the first storage node is also connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the second NMOS tube; the invention can solve the problems of low static noise margin and high leakage power consumption in the related technology, improves the static noise margin to improve the yield of the SRAM storage unit, reduces the leakage power consumption in the static mode, and is further more suitable for the application of ultra-low leakage.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to an SRAM memory cell.
Background
The continued advancement of integrated circuit technology nodes presents a number of challenges to the reliability of the chip, one of which is the impact of process variations on circuit performance.
Fig. 1 is a conventional 6-tube SRAM memory cell, which includes a first NOMS transmission tube and a second NMOS transmission tube, wherein the source and drain of the first NOMS transmission tube are respectively connected to a bit line BL and a storage node Q, the source and drain of the second NOMS transmission tube are respectively connected to a bit line BLB and a storage node QN, a first inverter and a second inverter are connected and interlocked between the storage node Q and the storage node QN, and the first inverter 101 and the second inverter 102 have the same structure and are all CMOS inverters formed by connecting an NMOS tube and a PMOS tube.
The traditional 6-pipe storage unit is relatively large in leakage power consumption, and is not suitable for applications with high requirements on the leakage power consumption, such as wearable equipment, internet of things applications and the like.
Disclosure of Invention
The invention provides an SRAM memory cell, which can solve the problems of low static noise margin and high leakage power consumption in the related technology.
The invention provides an SRAM storage unit, which comprises a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first transmission tube and a second transmission tube;
the first end of the first transmission tube is connected with a first bit line, and the other end of the first transmission tube is connected with a first storage node; the first end of the second transmission pipe is connected with a second bit line, and the other end of the second transmission pipe is connected with a second storage node;
the first storage node is also connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the second NMOS tube;
the second storage node is also connected with the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the sixth PMOS tube, the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the first NMOS tube;
the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and the drain electrode of the third PMOS tube;
and the source electrode of the fourth PMOS tube is connected with a power supply, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube and the drain electrode of the sixth PMOS tube.
Optionally, the first end of the first transmission tube is one of a source electrode and a drain electrode of the first transmission tube, the other first end of the first transmission tube is the other of the source electrode and the drain electrode of the first transmission tube, and the grid electrode of the first transmission tube is a control end;
the first end of the second transmission tube is one of a source electrode and a drain electrode of the second transmission tube, the other first end of the second transmission tube is the other of the source electrode and the drain electrode of the second transmission tube, and the grid electrode of the second transmission tube is a control end.
Alternatively, the potentials of the first storage node and the second storage node can be flipped between 0 and 1, respectively, and the potentials of the first storage node and the second storage node are opposite.
Optionally, if the potential of the first storage node is 0 and the potential of the second storage node is 1 in the initial state, when performing the write 1 operation on the SRAM memory cell, the word line is set to a low level, the first bit line is set to a high level, and the second bit line is set to a low level.
Optionally, after performing the write 1 operation on the SRAM memory cell, the SRAM memory cell stores information as 1, the potential of the first storage node is 1, and the potential of the second storage node is 0.
Optionally, when performing the write 0 operation on the SRAM memory cell, if the potential of the first storage node is 1 and the potential of the second storage node is 0 before performing the write 0 operation, the word line is set to a low level, the first bit line is set to a low level, and the second bit line is set to a high level when performing the write 0 operation on the SRAM memory cell.
Optionally, after performing the operation of writing 0 to the SRAM memory cell, the SRAM memory cell stores information as 0, the potential of the first storage node is 0, and the potential of the second storage node is 1.
The technical scheme of the invention at least comprises the following advantages: the invention can improve the read static noise margin of the circuit, so that the invention is not easy to generate errors in the read process, thereby improving the yield of the SRAM storage unit. In addition, as the PMOS tube of the process used in comparison is higher than the NMOS tube threshold voltage, the first transmission tube and the second transmission tube both adopt the PMOS tube structure, so that the number of NMOS tubes in the storage unit structure is reduced by two, the leakage power consumption of the invention in a static mode can be reduced, and the invention is further suitable for ultra-low leakage application, such as wearable equipment and Internet of things application.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a conventional 6-tube SRAM memory cell in the related art;
FIG. 2 is a circuit diagram of a conventional 10-pipe SRAM memory cell in the related art;
FIG. 3 is a circuit diagram of an SRAM memory cell in accordance with one embodiment of the present invention;
FIG. 4 is a waveform diagram illustrating basic functions of a memory cell of an SRAM according to one embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Because the leakage power consumption of the 6-tube SRAM memory cell is relatively large, the 6-tube SRAM memory cell is not suitable for applications with high requirements on the leakage power consumption, such as wearable equipment, internet of things applications and the like. As shown in FIG. 2, the main structure of the conventional 10-tube SRAM memory cell comprises a double cross-coupled latch structure, has high read static noise margin, but still has the defect of high leakage power consumption.
The invention provides an SRAM memory cell, referring to FIG. 3, comprising a first NMOS tube N1, a second NMOS tube N2, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a first transmission tube P7 and a second transmission tube P8.
A first end of the first transmission pipe P7 is connected with a first bit line BL, and the other end of the first transmission pipe P7 is connected with a first storage node Q; the first end of the second transmission pipe P8 is connected to the second bit line BLB, and the other end of the second transmission pipe P8 is connected to the second storage node QN.
The first storage node Q is further connected to the drain of the first NMOS transistor N1, the drain of the second PMOS transistor P2, the gate of the third PMOS transistor P3, the gate of the fourth PMOS transistor P4, the gate of the fifth PMOS transistor P5, and the gate of the second NMOS transistor N2.
The second storage node QN is further connected to the drain of the second NMOS transistor N2, the drain of the fifth PMOS transistor P5, the gate of the sixth PMOS transistor P6, the gate of the first PMOS transistor P1, the gate of the second PMOS transistor P2, and the gate of the first NMOS transistor N1, where the source of the first NMOS transistor N1 is grounded, and the source of the second NMOS transistor N2 is grounded.
The first storage node Q is connected to the first bit line BL through a first transfer pipe P7, and the second storage node QN is connected to the second bit line BLB through a second transfer pipe P8.
The source electrode of the first PMOS tube P1 is connected with a power supply, the drain electrode of the first PMOS tube P1 is connected with the source electrode of the second PMOS tube P2 and the drain electrode of the third PMOS tube P3, and the source electrode of the third PMOS tube P3 is grounded.
The source electrode of the fourth PMOS tube P4 is connected with a power supply, the drain electrode of the fourth PMOS tube P4 is connected with the source electrode of the fifth PMOS tube P5 and the drain electrode of the sixth PMOS tube P6, and the source electrode of the sixth PMOS tube P6 is grounded.
The first end of the first transmission pipe P7 is one pole of the source electrode or the drain electrode of the first transmission pipe P7, the other first end of the first transmission pipe P7 is the other pole of the source electrode or the drain electrode of the first transmission pipe P7, the grid electrode of the first transmission pipe P7 is a control end and is connected to the word line WL.
The first end of the second transmission pipe P8 is one of the source electrode and the drain electrode of the second transmission pipe P8, the other first end of the second transmission pipe P8 is the other one of the source electrode and the drain electrode of the second transmission pipe P8, and the gate electrode of the second transmission pipe P8 is the control end and is connected to the word line WL.
The potentials of the first storage node Q and the second storage node QN can be flipped between 0 and 1, respectively, and the potentials of the first storage node Q and the second storage node QN are opposite and mutually inverted storage nodes.
Because the threshold voltage of the PMOS tube is higher than that of the NMOS tube in the process used in comparison, the first transmission tube P7 and the second transmission tube P8 both adopt the structure of the PMOS tube, so that the number of the NMOS tubes in the storage unit structure is reduced by two, the leakage power consumption of the invention in a static mode can be reduced, and the invention is further suitable for ultra-low leakage application, such as wearable equipment, internet of things application and the like.
The working principle of the SRAM memory cell provided by the present invention is as follows, referring to fig. 4:
when writing 1: if the potential of the first storage node Q is 0 and the potential of the second storage node QN is 1 in the initial state, the word line WL is set to a low level, the first bit line BL is set to a high level, the second bit line BLB is set to a low level, and the first transmission pipe P7 and the second transmission pipe P8 are turned on when the SRAM memory cell is subjected to the write 1 operation. After performing a write 1 operation on the SRAM memory cell, the SRAM memory cell stores information of 1, the potential of the first storage node Q is 1, and the potential of the second storage node QN is 0.
Since the SRAM memory cell stores information of 1, the potential of the first storage node Q is 1, and the potential of the second storage node QN is 0; before performing a read 1 operation, the first bit line BL is set to a low level, and the second bit line BLB is set to a low level; when the read 1 operation is performed, the word line WL is set to a low level, so that the first transfer pipe P7 and the second transfer pipe P8 are turned on, the potential of the second storage node QN is 0, the potential 1 of the first storage node Q will cause the first bit line BL to be pulled up, and when the potential difference between the first bit line BL and the second bit line BLB reaches a certain level, the first bit line BL and the second bit line BLB will be read and amplified by the sense amplifier, and then the data 1 will be read.
When writing 0: if the potential of the first storage node Q is 1 and the potential of the second storage node QN is 0 before the write 0 operation, the word line WL is set to a low level, the first bit line BL is set to a low level, and the second bit line BLB is set to a high level when the write 0 operation is performed on the SRAM memory cell. After performing a write 0 operation on the SRAM memory cell, the SRAM memory cell stores information of 0, the potential of the first storage node Q is 0, and the potential of the second storage node QN is 1.
Since the SRAM memory cell stores information of 0, the potential of the first storage node Q is 0 and the potential of the second storage node QN is 1; before performing a read 0 operation, the first bit line BL is set to a low level, and the second bit line BLB is set to a low level; when the read 0 operation is performed, the word line WL is set to a low level, so that the first transfer tube P7 and the second transfer tube P8 are turned on, the potential of the first storage node Q is 0, the potential 1 of the second storage node QN causes the second bit line BLB to be pulled up, and when the potential difference between the first bit line BL and the second bit line BLB reaches a certain level, the first bit line BL and the second bit line BLB are read and amplified by the sense amplifier, and then the data 0 is read.
Table one: waveform diagram of read-write function under 1.2V standard voltage
As can be seen from Table 1, the present invention provides SRAM cells with the greatest read static noise margin compared to the other 2 cells. In contrast, the static noise margin of the SRAM memory cell provided by the invention is 2.79 times and 2.25 times that of the traditional 6-tube SRAM memory cell (refer to FIG. 1) and the traditional 10-tube SRAM memory cell (refer to FIG. 2), respectively, which means that the invention is least prone to error in the reading process, and the yield of the SRAM memory cell is improved.
In addition, since the PMOS transistors of the process used in the comparison are higher than the NMOS transistors in threshold voltage, the first transmission transistor P7 and the second transmission transistor P8 both adopt PMOS transistor structures, so that the number of NMOS transistors in the memory cell structure is reduced by two, and the leakage power consumption of the invention in the static mode can be reduced, thereby being suitable for ultra-low leakage applications, such as wearable equipment, internet of things applications and the like.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (7)
1. The SRAM storage unit is characterized by comprising a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first transmission tube and a second transmission tube;
the first end of the first transmission tube is connected with a first bit line, and the other end of the first transmission tube is connected with a first storage node; the first end of the second transmission pipe is connected with a second bit line, and the other end of the second transmission pipe is connected with a second storage node;
the first storage node is also connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the second NMOS tube;
the second storage node is also connected with the drain electrode of the second NMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the sixth PMOS tube, the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the first NMOS tube;
the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and the drain electrode of the third PMOS tube;
the source electrode of the fourth PMOS tube is connected with a power supply, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube and the drain electrode of the sixth PMOS tube;
the source electrode of the third PMOS tube, the source electrode of the sixth PMOS tube, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are all grounded;
the control end of the first transmission tube and the control end of the second transmission tube are both connected with word lines.
2. The SRAM memory cell of claim 1, wherein the first transfer tube and the second transfer tube are PMOS tubes, a first end of the first transfer tube is one of a source or a drain of the first transfer tube, the other end of the first transfer tube is the other of the source or the drain of the first transfer tube, and a gate of the first transfer tube is a control end;
the first end of the second transmission tube is one electrode of a source electrode or a drain electrode of the second transmission tube, the other end of the second transmission tube is the other electrode of the source electrode or the drain electrode of the second transmission tube, and the grid electrode of the second transmission tube is a control end.
3. The SRAM memory cell of claim 1, wherein the potentials of the first storage node and the second storage node are capable of toggling between 0 and 1, respectively, and wherein the potentials of the first storage node and the second storage node are opposite.
4. The SRAM memory cell of claim 1 wherein when a write 1 operation is performed on said SRAM memory cell if the potential of the first storage node is 0 and the potential of said second storage node is 1 in the initial state, the word line is set to a low level, the first bit line is set to a high level, and the second bit line is set to a low level.
5. The SRAM memory cell of claim 4 wherein after a write 1 operation is performed on the SRAM memory cell, the SRAM memory cell stores information of 1, the potential of the first storage node is 1, and the potential of the second storage node is 0.
6. The SRAM memory cell of claim 1 wherein when the SRAM memory cell is subjected to a write 0 operation, if the potential of the first storage node is 1 and the potential of the second storage node is 0 prior to the write 0 operation, the word line is set low, the first bit line is set low, and the second bit line is set high.
7. The SRAM memory cell of claim 1 wherein after a write 0 operation is performed on the SRAM memory cell, the SRAM memory cell stores information of 0, the potential of the first storage node is 0, and the potential of the second storage node is 1.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766494A (en) * | 2018-05-30 | 2018-11-06 | 电子科技大学 | A kind of SRAM memory cell circuit with high read noise tolerance |
| WO2019059591A1 (en) * | 2017-09-22 | 2019-03-28 | 경북대학교 산학협력단 | Ultra-low voltage memory device and operating method therefor |
| CN109887535A (en) * | 2019-01-08 | 2019-06-14 | 上海华虹宏力半导体制造有限公司 | The memory cell structure of SRAM |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019059591A1 (en) * | 2017-09-22 | 2019-03-28 | 경북대학교 산학협력단 | Ultra-low voltage memory device and operating method therefor |
| CN108766494A (en) * | 2018-05-30 | 2018-11-06 | 电子科技大学 | A kind of SRAM memory cell circuit with high read noise tolerance |
| CN109887535A (en) * | 2019-01-08 | 2019-06-14 | 上海华虹宏力半导体制造有限公司 | The memory cell structure of SRAM |
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