CN111404413A - Zero common mode voltage modulation algorithm for parallel inverter system - Google Patents

Zero common mode voltage modulation algorithm for parallel inverter system Download PDF

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CN111404413A
CN111404413A CN202010324116.6A CN202010324116A CN111404413A CN 111404413 A CN111404413 A CN 111404413A CN 202010324116 A CN202010324116 A CN 202010324116A CN 111404413 A CN111404413 A CN 111404413A
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voltage
vector
zero
sector
inverter
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杨凯
张伟健
王兴
郑逸飞
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Huazhong University of Science and Technology
Shenzhen Huazhong University of Science and Technology Research Institute
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Huazhong University of Science and Technology
Shenzhen Huazhong University of Science and Technology Research Institute
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/123—Suppression of common mode voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/493—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode the static converters being arranged for operation in parallel

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Abstract

The invention discloses a zero common mode voltage modulation algorithm for a parallel inverter system, which comprises the following steps: step 1, performing voltage vector modeling on each inverter according to a parallel topological structure of two inverters in a parallel inverter system; step 2, selecting a system voltage vector V with zero common mode voltage characteristiccm0(ii) a Step 3, according to the system voltage vector Vcm0Determining six sectors; step 4, judging the sector position of the reference voltage vector, thereby determining three system voltage vectors of the synthesized reference voltage vector; step 5, calculating the time of system voltage vector action according to the volt-second balance principle; and 6, determining the modulation sequence of the system voltage vector. The invention enables the output voltages of two inverters in the parallel inverter system to be mutually matched, ensures that the common-mode voltage of the system is zero at any time,the common mode voltage of the parallel inverter system is well suppressed.

Description

Zero common mode voltage modulation algorithm for parallel inverter system
Technical Field
The invention belongs to the technical field of inverters, and particularly relates to a zero common-mode voltage modulation algorithm for a parallel inverter system.
Background
The two-level voltage source type three-phase inverter is a three-phase inverter topology which is mature in technology and most widely applied at present. The inverter system with the inverters connected in parallel through the specific filter inductor has the advantages of multiple control degrees of freedom, high reliability, convenience in modular design and the like, and is widely applied to occasions of high-capacity inverters.
Among the modulation algorithms of the inverter system, a seven-segment svpwm (space Vector Pulse width modulation) is the most widely applied modulation method at present. The modulation method forms a modulation scheme by using the principle that a voltage vector meets volt-second balance from the angle of synthesizing a circular magnetic field of the alternating current motor, and has the advantages of clear physical significance, high direct current voltage utilization rate and low output current harmonic content. But it has a maximum value of VdcThe high frequency common mode voltage of/2 is a serious harm to the system.
Aiming at a parallel inverter structure with more freedom degrees, the carrier phase-shifting SVPWM is further improved on the basis of the common seven-section SVPWM, the effect of specific harmonic cancellation is achieved by setting different inverter carrier phases, lower output current THD is obtained, and meanwhile, the common-mode voltage peak value is also suppressed to Vdc6, but the common mode voltage cannot be completely eliminated. Therefore, the existing modulation methods are not suitable for some applications sensitive to common mode voltage.
Disclosure of Invention
Aiming at least one defect or improvement requirement in the prior art, the invention provides a zero common mode voltage modulation algorithm for a parallel inverter system, and the common mode voltage of the inverter system is effectively eliminated on the premise of meeting volt-second balance through the mutual matching of output voltage vectors of two inverters.
To achieve the above object, according to a first aspect of the present invention, there is provided a zero common mode voltage modulation algorithm for a parallel inverter system, comprising:
step 1, performing voltage vector modeling on each inverter according to two inverter parallel topological structures in a parallel inverter system;
step 2, selecting a system voltage vector V with zero common mode voltage characteristiccm0；
Step 3, according to the system voltage vector Vcm0The non-zero vector in (1) determines six sectors;
step 4, determining a sector where the reference voltage vector is located, and determining three system voltage vectors for synthesizing the reference voltage vector according to the located sector;
step 5, determining the action time of three system voltage vectors for synthesizing the reference voltage vector, so that the action effect of the three system voltage vectors for synthesizing the reference voltage vector is the same as the action effect of the reference voltage vector;
and 6, determining the modulation sequence of the three system voltage vectors for synthesizing the reference voltage vector.
Preferably, in step 1, the voltage vector generated by each inverter module includes: v '0 [000], V' 1[100], V '2 [110], V' 3[010], V '4 [011], V' 5[001], V '6 [101], V' 7[111 ].
Preferably, the system voltage vector Vcm0Comprises the following steps: non-zero vectors V7, V8, V9, V10, V11, V12 and zero vector V00, wherein V7 is a vector consisting of V '1 and V' 2, V8 is a vector consisting of V '2 and V' 3, V9 is a vector consisting of V '3 and V' 4, V10 is a vector consisting of V '4 and V' 5, V11 is a vector consisting of V '5 and V' 6, and V12 is a vector consisting of V '6 and V' 1.
Preferably, the step 2 is specifically:
combining the voltage vectors generated by each inverter in the step 1 to obtain all system voltage vectors;
calculating system common mode voltage, and selecting system voltage vector V with zero common mode voltage characteristic from all system voltage vectorscm0The formula for calculating the common mode voltage of the system is as follows:
Figure BDA0002462540860000021
wherein, VcmIs the system common mode voltage, VAN1、VBN1、VCN1Respectively represents ABC three-phase voltage, V of one inverter in parallel inverters by taking neutral point voltage of a direct current bus as referenceAN2、VBN2、VCN2Respectively represent ABC three-phase voltage of another inverter in the parallel inverters by taking the midpoint voltage of the direct-current bus as reference.
Preferably, the step 3 is specifically:
the space plane is divided into six sectors by non-zero vectors V7, V8, V9, V10, V11 and V12, two adjacent non-zero vectors form one sector, a sector formed by V7 and V12 is a first sector, a sector formed by V7 and V8 is a second sector, a sector formed by V8 and V9 is a third sector, a sector formed by V9 and V10 is a fourth sector, a sector formed by V10 and V11 is a fifth sector, and a sector formed by V11 and V12 is a sixth sector.
Preferably, the step 4 specifically includes:
and judging the sector where the reference voltage vector is located according to the amplitude and the phase of the reference voltage vector, selecting two adjacent non-zero vectors forming the sector where the reference voltage vector is located as two system voltage vectors for synthesizing the reference voltage vector, and selecting a zero vector V00 as a third system voltage vector for synthesizing the reference voltage vector.
Preferably, the system voltage vector modulation order is determined according to the sector where the reference voltage is located.
Preferably, the system voltage vector modulation order is such that a centrally asymmetric PWM wave is output to drive the inverter.
Preferably, the common mode voltage of the parallel inverter system is always zero.
Preferably, the parallel inverter system is characterized in that the two three-phase two-level voltage source type inverters are connected in parallel through a filter inductor;
the type of a switching tube adopted by the three-phase two-level voltage source type inverter is IGBT;
the filter inductor is a single-phase inductor, a three-phase inductor, a two-phase coupling inductor or a three-phase common-mode inductor.
Generally speaking, the SVPWM voltage vector modeling method improves a voltage vector model of the traditional SVPWM, carries out system voltage vector modeling aiming at a parallel system of two-level voltage source type inverters, and selects a vector with zero common-mode voltage characteristic from all system voltage vectors, so that the output voltage vectors of the two inverters are mutually matched at each modulation moment, and the effect that the common-mode voltage of the system is always zero is achieved. In addition, the invention further optimizes the switching sequence, adopts the PWM wave with asymmetric center to drive the inverter, generates more voltage vectors in one modulation period, has finer modulation process and lower total harmonic content of output current.
Drawings
FIG. 1 is a schematic diagram of a vector modulation algorithm according to an embodiment of the present invention;
FIG. 2 is a hardware topology of a parallel inverter system of an embodiment of the present invention;
FIG. 3 is a voltage vector distribution diagram for a parallel inverter system according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a sector of a reference voltage according to an embodiment of the present invention;
FIG. 5 is a prior art SVPWM modulated common mode voltage waveform;
FIG. 6 is a common mode voltage waveform of prior art carrier phase shift SVPWM modulation;
fig. 7 is a common mode voltage waveform of the vector modulation algorithm according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Fig. 2 is a hardware topology of a parallel inverter system according to an embodiment of the present invention. As shown in the figure, the system adopts a structure that two common two-level voltage source type three-phase inverters are connected in parallel through a filter inductor, and the output end of each inverter is connected with the filter inductor to limit the circulating current between modules. The switching tube type adopted by the three-phase two-level voltage source type inverter is IGBT. The selection of the filter inductor can be selected according to actual requirements, and can be a single-phase inductor or a three-phase inductor, a coupling inductor specially used for inhibiting circulating current, or a three-phase common mode inductor. It should be noted that the latter two kinds of coupled inductors have better effect of suppressing the circulating current, but for the analysis of the common mode voltage, the coupled inductor can be removed and regarded as a common inductor, so for the convenience of analysis, the following analysis all regards it as the same common inductor. For convenience of analysis, the upper inverter in the figure is numbered as VSI1, and the lower one is numbered as VSI 2.
A zero common mode voltage modulation algorithm for a parallel inverter system according to an embodiment of the present invention, as shown in fig. 1, includes:
step 1, voltage vector modeling is carried out on each inverter according to two inverter parallel system topologies in a parallel inverter system.
Still follow the analysis method of traditional seven-segment SVPWM, define every three-phase two-level voltage source inverter at any moment, every bridge arm switching state function is:
Figure BDA0002462540860000051
wherein x represents ABC three phases, y represents inverter 1 or 2, and SxyRepresenting the switching state of the x-phase of inverter y. Thus, at any time, the state of the inverter 1 can be represented as [ S ]a1Sa2Sa3]Then, all the switching states of the inverter 1 are obtained as V' 0[000]],V＇1[100],V＇2[110],V＇3[010],V＇4[011],V＇5[001],V＇6[101],V＇7[111]. The switching state of the inverter 2 is similar to that of the inverter 1 and will not be described in detail.
Step 2, selecting a system voltage vector V with zero common mode voltage characteristiccm0。
At any time, since the inverter 1 and the inverter 2 are independent, 64 switching state combinations are common to both, as shown in the following table.
Figure BDA0002462540860000052
The vectors in the table are all the system voltage vectors that can be generated by the combination of the two inverters. Because the system structure adopts two inverters to be connected in parallel, the system vector is obtained by vector synthesis of the voltage vectors of the two inverters. Fig. 3 shows the distribution of all system voltage vectors.
Then, the common mode voltage formed by each system voltage vector is calculated according to a common mode voltage calculation formula, which is as follows:
Figure BDA0002462540860000053
wherein VcmIs the system common mode voltage, VAN1、VBN1、VCN1Respectively represent ABC three-phase voltage and V of the inverter 1 by taking the midpoint voltage of the direct current bus as referenceAN2、VBN2、VCN2Respectively represent ABC three-phase voltage of the inverter 2 by taking the midpoint voltage of the direct-current bus as a reference.
And finally, selecting system voltage vectors which can enable the common-mode voltage of the system to be 0, wherein the system voltage vectors are respectively a non-zero vector V7, a non-zero vector V8, a non-zero vector V9, a non-zero vector V10, a non-zero vector V11, a non-zero vector V12 and a non-zero vector V00. Wherein V7 is the vector composed of V '1 and V' 2, V8 is the vector composed of V '2 and V' 3, V9 is the vector composed of V '3 and V' 4, V10 is the vector composed of V '4 and V' 5, V11 is the vector composed of V '5 and V' 6, and V12 is the vector composed of V '6 and V' 1. The zero vector V00 is represented as a vector with zero effect in one cycle, and there are various combinations, as shown in the above table. It should be noted that the common mode voltage formed by the vector V0 is also 0, but it causes serious circulating current and is not adopted by the present invention.
Step 3, according to the system voltage vector V obtained in the step 2cm0The non-zero vector in (a) determines six sectors.
The space plane is divided into 6 sectors by adopting the 6 non-zero vectors obtained in the step 2, two adjacent non-zero vectors form one sector, a sector formed by V7 and V12 is a first sector, a sector formed by V7 and V8 is a second sector, a sector formed by V8 and V9 is a third sector, a sector formed by V9 and V10 is a fourth sector, a sector formed by V10 and V11 is a fifth sector, and a sector formed by V11 and V12 is a sixth sector. Vector partitioning is shown in fig. 4.
And 4, judging the sector where the reference voltage vector is located, and determining three system voltage vectors for synthesizing the reference voltage vector according to the located sector.
And judging the sector where the reference voltage vector is located according to the amplitude and the phase angle of the reference voltage vector. As shown in FIG. 4, first, the reference voltage vector V is determinedrefIf the amplitude exceeds the hexagon formed by the end points of the six system voltage vectors in the figure, the reference vector exceeds the maximum modulation range of the inverter, modulation is not carried out, and errors are reported, if the amplitude does not exceed the hexagon, the sector where the reference vector is located is determined through the phase information of the reference vector, taking the situation shown in figure 3 as an example, the reference voltage is projected according to an αβ coordinate system shown in the figure, and the phase angle is calculated, and the calculation formula is as follows:
Figure BDA0002462540860000061
wherein, VrefαAnd VrefβAre respectively a reference voltage VrefIn the projection on axis αβ, θ is the phase angle of the reference voltage vector, it can be seen that the angle of the reference voltage is 15 ° and belongs to the first sector, so the three system vectors of the resultant reference voltage vector are the adjacent non-zero vectors V7 and V12 of the first sector, and the zero vector V00.
And 5, determining the action time of the three system voltage vectors of the synthesized reference voltage vector according to the volt-second balance principle, so that the action effect of the three system voltage vectors of the synthesized reference voltage vector is the same as the action effect of the reference voltage vector.
The voltage-second balance principle is that in one modulation period, the action effect of the reference voltage is equivalent to the action effect of three system voltage vectors, the three system vectors of the reference vector and the synthetic reference vector are respectively projected into αβ systems, and the action time of each system voltage vector is calculated by solving the following equation system.
Figure BDA0002462540860000071
Wherein, V1α、V2α、V3αAre respectively a synthetic reference vector VrefThe projection of the three system vectors on the α axis V1β、V2β、V3βAre respectively a synthetic reference vector VrefProjection of the three system vectors on the β axis, T1、T2、T3Are respectively a synthetic reference vector VrefTime of three system vectors; t issIs one modulation period.
And 6, determining the modulation sequence of the three system voltage vectors of the synthesized reference voltage vector.
The order of vector modulation of the system voltage is determined according to the sector number of the reference voltage, as shown in the following table:
Figure BDA0002462540860000072
Figure BDA0002462540860000081
the system voltage vector modulation sequence enables the inverter to be driven by the output of the PWM wave with asymmetric center, a larger number of voltage vectors are generated in one modulation period, the modulation process is finer, and the total harmonic content of the output current is lower.
The following table shows the inverter system parameters used in the embodiments of the present invention, and the corresponding simulation verification is performed by using MAT L AB/SIMU L INK software.
Parameters of inverter system Value of parameter
Switching tube type IGBT
Filter inductor type Single-phase inductor
Switching frequency 1000Hz
Filter inductance value 1mH
Load inductance value 1mH
Resistance value of load 10Ω
Value of DC voltage 200V
The common seven-segment SVPWM, the carrier phase-shift SVPWM and the modulation scheme provided by the invention are respectively verified by simulation experiments, and the common-mode voltage waveforms of the three schemes under the same modulation ratio are compared, so that the following can be found: FIG. 5 shows a seven-segment SVPWM modulation method with a peak value VdcA high frequency common mode voltage of/2 (100V); FIG. 6 is a carrier phase shift SVPWM modulation method that suppresses the common mode voltage peak to Vdc6 (33V); fig. 7 shows the modulation method proposed by the present invention, in which the common-mode voltage is always zero, so that the common-mode voltage of the system is well suppressed.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A zero common mode voltage modulation algorithm for a parallel inverter system, comprising:
step 1, performing voltage vector modeling on each inverter according to two inverter parallel topological structures in a parallel inverter system;
step 2, selecting a system voltage vector V with zero common mode voltage characteristiccm0；
Step 3, according to the system voltage vector Vcm0The non-zero vector in (1) determines six sectors;
step 4, determining a sector where the reference voltage vector is located, and determining three system voltage vectors for synthesizing the reference voltage vector according to the located sector;
step 5, determining the action time of three system voltage vectors for synthesizing the reference voltage vector, so that the action effect of the three system voltage vectors for synthesizing the reference voltage vector is the same as the action effect of the reference voltage vector;
and 6, determining the modulation sequence of the three system voltage vectors for synthesizing the reference voltage vector.
2. A zero common mode voltage modulation algorithm for parallel inverter systems according to claim 1, wherein in step 1, the voltage vector generated by each inverter module comprises:
V＇0[000],V＇1[100],V＇2[110],V＇3[010],V＇4[011],V＇5[001],V＇6[101],V＇7[111]。
3. the zero common mode voltage modulation algorithm for parallel inverter system of claim 2 wherein the system voltage vector Vcm0Comprises the following steps: non-zero vectors V7, V8, V9, V10, V11, V12 and zero vectorsAmount V00, wherein V7 is the vector consisting of V '1 and V' 2, V8 is the vector consisting of V '2 and V' 3, V9 is the vector consisting of V '3 and V' 4, V10 is the vector consisting of V '4 and V' 5, V11 is the vector consisting of V '5 and V' 6, and V12 is the vector consisting of V '6 and V' 1.
4. A zero common mode voltage modulation algorithm for parallel inverter systems according to any of claims 1 to 3, characterized in that said step 2 is in particular:
combining the voltage vectors generated by each inverter in the step 1 to obtain all system voltage vectors;
calculating system common mode voltage, and selecting system voltage vector V with zero common mode voltage characteristic from all system voltage vectorscm0The formula for calculating the common mode voltage of the system is as follows:
Figure FDA0002462540850000021
wherein, VcmIs the system common mode voltage, VAN1、VBN1、VCN1Respectively represents ABC three-phase voltage, V of one inverter in parallel inverters by taking neutral point voltage of a direct current bus as referenceAN2、VBN2、VCN2Respectively represent ABC three-phase voltage of another inverter in the parallel inverters by taking the midpoint voltage of the direct-current bus as reference.
5. A zero common mode voltage modulation algorithm for parallel inverter systems according to claim 3, wherein the step 3 is specifically:
the space plane is divided into six sectors by non-zero vectors V7, V8, V9, V10, V11 and V12, two adjacent non-zero vectors form one sector, a sector formed by V7 and V12 is a first sector, a sector formed by V7 and V8 is a second sector, a sector formed by V8 and V9 is a third sector, a sector formed by V9 and V10 is a fourth sector, a sector formed by V10 and V11 is a fifth sector, and a sector formed by V11 and V12 is a sixth sector.
6. The zero common mode voltage modulation algorithm for the parallel inverter system according to claim 5, wherein the step 4 is specifically:
and judging the sector where the reference voltage vector is located according to the amplitude and the phase of the reference voltage vector, selecting two adjacent non-zero vectors forming the sector where the reference voltage vector is located as two system voltage vectors for synthesizing the reference voltage vector, and selecting a zero vector V00 as a third system voltage vector for synthesizing the reference voltage vector.
7. A zero common mode voltage modulation algorithm for parallel inverter systems according to any one of claims 1 to 3, wherein the system voltage vector modulation order is determined according to the sector where the reference voltage is located.
8. A zero common mode voltage modulation algorithm for parallel inverter systems according to any of claims 1 to 3 wherein the system voltage vector modulation order is such that a PWM wave with an asymmetrical center of output is used to drive the inverter.
9. A zero common-mode voltage modulation algorithm for parallel inverter systems according to any of claims 1 to 3, characterized in that the common-mode voltage of the parallel inverter systems is always zero.
10. A zero common mode voltage modulation algorithm for parallel inverter system according to any one of claims 1 to 3, wherein the parallel inverter system is a structure in which two three-phase two-level voltage source type inverters are connected in parallel through a filter inductor;
the type of a switching tube adopted by the three-phase two-level voltage source type inverter is IGBT;
the filter inductor is a single-phase inductor, a three-phase inductor, a two-phase coupling inductor or a three-phase common-mode inductor.
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EP4084309A1 (en) * 2021-04-29 2022-11-02 Applied Micro Electronics "AME" B.V. Elimination of common-mode voltages for ac/dc converters with interleaved switching
CN116780930A (en) * 2023-06-20 2023-09-19 南京理工大学 Switch time sequence optimization design for zero sequence circulation suppression and common mode voltage elimination of two parallel converters and carrier modulation implementation method thereof
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CN112803818A (en) * 2020-12-30 2021-05-14 西安工业大学 Common-mode voltage elimination method based on parallel driver topological structure
CN112803818B (en) * 2020-12-30 2022-10-04 西安工业大学 Common-mode voltage elimination method based on parallel driver topological structure
CN112821737A (en) * 2021-02-03 2021-05-18 华中科技大学 Zero common mode voltage control circuit based on parallel inverter reduces circulating current
CN113114032A (en) * 2021-04-28 2021-07-13 西安工业大学 SVPWM common mode voltage suppression method based on synthetic mode change
EP4084309A1 (en) * 2021-04-29 2022-11-02 Applied Micro Electronics "AME" B.V. Elimination of common-mode voltages for ac/dc converters with interleaved switching
CN116780930A (en) * 2023-06-20 2023-09-19 南京理工大学 Switch time sequence optimization design for zero sequence circulation suppression and common mode voltage elimination of two parallel converters and carrier modulation implementation method thereof
CN116780930B (en) * 2023-06-20 2023-12-01 南京理工大学 Switch time sequence optimization design of two parallel converters and carrier modulation method thereof
CN117394744A (en) * 2023-12-13 2024-01-12 深圳大学 Common-mode voltage suppression method
CN117394744B (en) * 2023-12-13 2024-02-20 深圳大学 Common-mode voltage suppression method

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