CN111403411A - Three-dimensional memory and forming method thereof - Google Patents

Three-dimensional memory and forming method thereof Download PDF

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Publication number
CN111403411A
CN111403411A CN202010228715.8A CN202010228715A CN111403411A CN 111403411 A CN111403411 A CN 111403411A CN 202010228715 A CN202010228715 A CN 202010228715A CN 111403411 A CN111403411 A CN 111403411A
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charge storage
sublayer
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channel hole
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CN111403411B (en
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王恩博
卢峰
张富山
曾凡清
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a forming method thereof. The method for forming the three-dimensional memory comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a stacked structure, a channel hole, an epitaxial layer and a charge storage layer; forming a first processing layer on the surface of the side wall of the charge storage layer and forming a second processing layer on the surface of the bottom wall of the charge storage layer, wherein the first processing layer has etching selectivity relative to the second processing layer and the charge storage layer; removing the second processing layer to expose the charge storage layer; and removing the charge storage layer at the bottom of the channel hole to expose the epitaxial layer. The invention avoids the damage to the charge storage layer on the side wall of the channel hole and improves the electrical property of the core area of the three-dimensional memory.

Description

Three-dimensional memory and forming method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a forming method thereof.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to solve the difficulties encountered by flat flash memories and to pursue lower production costs of unit memory cells, various three-dimensional (3D) flash memory structures, such as 3D NOR (3D NOR) flash memory and 3D NAND (3D NAND) flash memory, have come into force.
The 3D NAND memory is based on the small volume and the large capacity, the design concept of the three-dimensional mode layer-by-layer stacking height integration of the storage units is adopted, the memory with high unit area storage density and high-efficiency storage unit performance is produced, and the mainstream process of the design and production of the emerging memory is formed.
In the current manufacturing process of the 3D NAND memory, a sidewall punch-through phenomenon often occurs in a memory function layer formed in a trench hole, thereby affecting the electrical performance of a core region of the three-dimensional memory, and even resulting in the rejection of the whole three-dimensional memory in a severe case.
Therefore, how to improve the electrical performance of the core region of the three-dimensional memory and ensure the integrity of the morphology of the memory function layer is a technical problem to be solved at present.
Disclosure of Invention
The invention provides a three-dimensional memory and a forming method thereof, which are used for solving the problem of poor performance of the conventional three-dimensional memory.
In order to solve the above problems, the present invention provides a method for forming a three-dimensional memory, comprising the steps of:
providing a substrate, wherein the substrate comprises a substrate, a stacking structure positioned on the surface of the substrate, a channel hole penetrating through the stacking structure, an epitaxial layer positioned on the surface of the substrate and exposed at the bottom of the channel hole, and a charge storage layer covering the inner wall of the channel hole and the surface of the epitaxial layer;
forming a first processing layer on the surface of the side wall of the charge storage layer and forming a second processing layer on the surface of the bottom wall of the charge storage layer, wherein the first processing layer has etching selectivity relative to the second processing layer and the charge storage layer;
selectively removing the second processing layer by adopting a wet etching process to expose the charge storage layer;
and removing the charge storage layer at the bottom of the channel hole by adopting a wet etching process to expose the epitaxial layer.
Optionally, the specific steps of forming a first processing layer on the surface of the sidewall of the charge storage layer and forming a second processing layer on the surface of the bottom wall of the charge storage layer include:
forming a protective layer on the surfaces of the side wall and the bottom wall of the charge storage layer;
modifying the protective layer on the side wall of the charge storage layer and/or the bottom wall of the charge storage layer to form the first processed layer and the second processed layer.
Optionally, the protective layer is a single-layer structure; or,
the protective layer is of a multilayer structure which is sequentially overlapped along the radial direction of the channel hole.
Optionally, the specific steps of forming the protection layer on the surface of the sidewall and the bottom wall of the charge storage layer include:
forming a first sublayer on the surfaces of the side wall and the bottom wall of the charge storage layer;
forming a second sublayer covering the surface of the first sublayer, wherein the second sublayer has etching selectivity relative to the first sublayer;
and forming a third sublayer covering the surface of the second sublayer, wherein the third sublayer has etching selectivity relative to the second sublayer, and the protective layer comprising the first sublayer, the second sublayer and the third sublayer is formed.
Optionally, the specific step of modifying the protective layer on the sidewall of the charge storage layer and/or the bottom wall of the charge storage layer includes:
modifying the third sub-layer on the sidewalls of the second sub-layer and/or the bottom wall of the second sub-layer to form the first treated layer on the sidewalls of the second sub-layer and the second treated layer on the bottom wall of the second sub-layer.
Optionally, the specific steps of forming the first processed layer on the sidewall of the second sublayer and the second processed layer on the bottom wall of the second sublayer include:
implanting doping elements into the third sub-layer on the bottom wall of the second sub-layer to form the second processing layer;
and oxidizing the third sub-layer on the side wall of the second sub-layer to form the first processing layer.
Optionally, the third sublayer is made of polysilicon;
the doping element is nitrogen.
Optionally, the specific step of exposing the charge storage layer includes:
and selectively removing the second processing layer, the second sublayer positioned on the bottom wall of the charge storage layer and the first sublayer positioned on the bottom wall of the charge storage layer by adopting a wet etching process, and exposing the charge storage layer.
Optionally, the charge storage layer includes a blocking layer covering the side wall of the channel hole and the surface of the epitaxial layer, a charge trapping layer covering the surface of the blocking layer, and a tunneling layer covering the surface of the charge trapping layer; the first processing layer is made of the same material as the tunneling layer; the specific step of removing the charge storage layer at the bottom of the channel hole further includes:
and simultaneously removing the first processing layer and the tunneling layer on the bottom wall of the channel hole by adopting a wet etching process, and exposing the charge trapping layer and the second sublayer on the side wall of the charge storage layer.
Optionally, the second sublayer is the same material as the charge trapping layer; the specific step of removing the charge storage layer at the bottom of the channel hole further includes:
and simultaneously removing the second sublayer and the charge trapping layer on the bottom wall of the channel hole by adopting a wet etching process, and exposing the blocking layer and the first sublayer on the side wall of the charge storage layer.
Optionally, the barrier layer has an etching selectivity with respect to the first sublayer; the specific step of removing the charge storage layer at the bottom of the channel hole further includes:
removing the barrier layer on the bottom wall of the channel hole by adopting a wet etching process to expose the epitaxial layer;
and removing the first sub-layer by adopting a wet etching process.
In order to solve the above problem, the present invention also provides a three-dimensional memory, including:
the substrate comprises a substrate, a stacked structure positioned on the surface of the substrate, a channel hole penetrating through the stacked structure, and an epitaxial layer positioned on the surface of the substrate and exposed to the bottom of the channel hole;
the charge storage layer covers in the inner wall in channel hole, just the bottom of charge storage layer has one and exposes the opening of epitaxial layer, the opening is in the lateral wall of charge storage layer covers first processing layer, after charge storage layer diapire covers the second processing layer, get rid of the second processing layer with channel hole bottom the charge storage layer is formed, first processing layer for the second processing layer with the charge storage layer all has the sculpture selectivity.
Optionally, the second processing layer is made of a polysilicon material doped with nitrogen, and the first processing layer is made of an oxide material.
Optionally, the first processing layer is a single-layer structure or a multilayer structure sequentially stacked along a radial direction of the channel hole;
the second processing layer is of a single-layer structure or a multi-layer structure which is sequentially overlapped along the radial direction of the channel hole.
Optionally, a first sublayer and a second sublayer are respectively arranged between the charge storage layer and the first processing layer and between the charge storage layer and the second processing layer, the second sublayer is located on one side of the first sublayer, which is far away from the charge storage layer, and the second sublayer has etching selectivity relative to the first sublayer.
Optionally, the charge storage layer includes a blocking layer, a charge trapping layer and a tunneling layer, which are sequentially stacked along a radial direction of the channel hole;
the first handle layer is of the same material as the tunneling layer such that the tunneling layer and the first handle layer can be removed simultaneously during formation of the opening.
Optionally, the second sub-layer is of the same material as the charge trapping layer, such that the charge trapping layer and the second sub-layer can be removed simultaneously during the formation of the opening.
Optionally, the barrier layer has an etch selectivity with respect to the first sublayer.
Optionally, the material of the first sub-layer is a polysilicon material.
According to the three-dimensional memory and the forming method thereof provided by the invention, the first processing layer and the second processing layer are respectively formed on the surface and the side wall of the charge storage layer in the channel hole, the first processing layer and the second processing layer are controlled to have etching selectivity relative to each other, and the first processing layer also has etching selectivity relative to the charge storage layer, so that the second processing layer and the charge storage layer at the bottom of the channel hole can be removed through process selectivity in subsequent processes, the damage to the charge storage layer on the side wall of the channel hole is avoided, the integrity of the morphology of the side wall of the charge storage layer is ensured, the electrical property of a core area of the three-dimensional memory is improved, and the yield of the three-dimensional memory is improved.
Drawings
FIG. 1 is a flow chart of a method for forming a three-dimensional memory according to an embodiment of the present invention;
fig. 2A-2H are schematic cross-sectional views of the main processes of an embodiment of the present invention in forming a three-dimensional memory.
Detailed Description
The following describes in detail a specific embodiment of a three-dimensional memory and a method for forming the same according to the present invention with reference to the accompanying drawings.
After a channel hole is formed in a core area of a 3D NAND memory through etching, an epitaxial layer is formed at the bottom of the channel hole in a long mode, then a charge storage layer is formed on the inner wall of the channel hole, then the bottom of the charge storage layer is opened through a dry etching process, the epitaxial layer is exposed, and finally a channel layer is formed on the surfaces of the charge storage layer and the epitaxial layer, so that the channel layer is electrically connected with the epitaxial layer. The channel layer and the charge storage layer jointly serve as a channel function layer. However, during the process of opening the bottom of the charge storage layer by using a dry etching process, the bombardment of plasma is very likely to cause the breakdown of the charge storage layer on the sidewall of the channel hole, thereby causing the reduction of the electrical performance of the core region and even the rejection of the memory. This phenomenon is more pronounced in three-dimensional memories having a dual-stack channel hole structure, which has alignment mark misalignment issues.
In order to reduce the risk of the charge storage layer on the sidewall of the trench hole being broken down, the present embodiment provides a method for forming a three-dimensional memory, fig. 1 is a flow chart of a method for forming a three-dimensional memory according to an embodiment of the present invention, and fig. 2A to 2H are schematic process cross-sectional views of a process for forming a three-dimensional memory according to an embodiment of the present invention. The three-dimensional memory described in this embodiment may be, but is not limited to, a 3D NAND memory, such as a 3D NAND memory having a dual stack channel hole structure. As shown in fig. 1 and fig. 2A to fig. 2H, the method for forming a three-dimensional memory according to the present embodiment includes the following steps:
step S11, providing a base, where the base includes a substrate 20, a stack structure 21 on the surface of the substrate 20, a channel hole 25 penetrating through the stack structure 21, an epitaxial layer 30 on the surface of the substrate 20 and exposed at the bottom of the channel hole 25, and a charge storage layer covering the inner wall of the channel hole 25 and the surface of the epitaxial layer 25, as shown in fig. 2A.
In particular, the material of the substrate 20 may be, but is not limited to, silicon. The stack structure 21 includes interlayer insulating layers 211 and sacrificial layers 212 alternately stacked on the surface of the substrate 20 in a direction perpendicular to the substrate 20. The material of the interlayer insulation 211 may be an oxide material (e.g., silicon dioxide), and the material of the sacrificial layer 212 may be a nitride material (e.g., silicon nitride). The number of stacked layers of the stacked structure 21 can be set by those skilled in the art according to actual needs, and can be, for example, 32 layers, 64 layers or 128 layers. In this embodiment, a buffer oxide layer 22 and a dielectric layer 23 may be further disposed between the substrate 20 and the stacked structure 21. After the stacked structure 21 is formed, a channel hole 25 penetrating through the stacked structure 21 is formed by an etching process, and the epitaxial layer 30 is grown at the bottom of the channel hole 25. One skilled in the art can also form the auxiliary layer 24 on the surface of the epitaxial layer 30 to avoid damage to the epitaxial layer 30 in the subsequent etching process. The material of the auxiliary layer 24 may be an oxide material. Then, the charge storage layer is deposited on the inner wall of the channel hole 25, and the charge storage layer covers the surface of the auxiliary layer 24.
Step S12 is to form a first processed layer 29 on the sidewall surface of the charge storage layer and a second processed layer 28 on the bottom wall surface of the charge storage layer, where the first processed layer 29 has an etching selectivity with respect to both the second processed layer 28 and the charge storage layer, as shown in fig. 2C.
Specifically, the first processed layer 29 and the second processed layer 28 are respectively formed on the sidewall and bottom wall surfaces of the charge storage layer, and the first processed layer 29 is controlled to have an etching selectivity with respect to the second processed layer 28, so that the second processed layer 28 can be selectively removed by a wet etching process without damaging the first processed layer 29, thereby protecting the charge storage layer on the sidewall of the channel hole 25. A specific method of forming the first processed layer 29 on the sidewall surface of the charge storage layer and forming the second processed layer 28 on the bottom wall surface of the charge storage layer may be selected by those skilled in the art according to actual needs, and the present embodiment does not limit this method as long as the first processed layer 29 and the second processed layer 28 having etching selectivity with respect to each other can be formed on the sidewall and the bottom wall of the charge storage layer.
Optionally, the specific steps of forming the first processing layer 29 on the sidewall surface of the charge storage layer and forming the second processing layer 28 on the bottom wall surface of the charge storage layer include:
forming a protective layer on the surfaces of the side wall and the bottom wall of the charge storage layer;
the protective layer on the side wall of the charge storage layer and/or the bottom wall of the charge storage layer is modified to form the first treated layer 29 and the second treated layer 28.
Specifically, in order to simplify the process steps, the protective layer may be formed prior to the entire surface of the charge storage layer, and then the first processed layer 29 and the second processed layer 28 may be formed by performing modification treatment on the protective layer on the side wall of the charge storage layer, performing modification treatment on the protective layer on the bottom wall of the charge storage layer, or performing modification treatment on the charge storage layers on the side wall and the bottom wall of the charge storage layer, respectively. The specific manner of the modification treatment can be selected by those skilled in the art according to actual needs, such as oxidation, ion implantation, etc.
Optionally, the protective layer is a single-layer structure; or,
the protective layer is of a multilayer structure which is sequentially overlapped along the radial direction of the channel hole.
Optionally, the specific steps of forming the protection layer on the surface of the sidewall and the bottom wall of the charge storage layer include:
forming a first sub-layer 271 on the sidewall and bottom wall surfaces of the charge storage layer;
forming a second sub-layer 272 covering the surface of the first sub-layer 271, wherein the second sub-layer 272 has etching selectivity relative to the first sub-layer 271;
forming a third sub-layer 273 covering the surface of the second sub-layer 272, wherein the third sub-layer 273 has etching selectivity with respect to the second sub-layer 272, and forming the protection layer including the first sub-layer 271, the second sub-layer 272, and the third sub-layer 273, as shown in fig. 2A.
Optionally, the specific step of modifying the protective layer on the sidewall of the charge storage layer and/or the bottom wall of the charge storage layer includes:
the third sub-layer 273, which is located on the sidewalls of the second sub-layer 272 and/or the bottom wall of the second sub-layer 272, is modified to form the first processed layer 29 located on the sidewalls of the second sub-layer 272 and the second processed layer 28 located on the bottom wall of the second sub-layer 272.
Optionally, the specific steps of forming the first processed layer 29 on the sidewall of the second sub-layer 272 and the second processed layer 28 on the bottom wall of the second sub-layer 272 include:
implanting a doping element into the third sub-layer 273 on the bottom wall of the second sub-layer 272 to form the second handle layer 28, as shown in fig. 2B;
the third sub-layer 273 on the sidewalls of the second sub-layer 272 is oxidized to form the first handle layer 29, as shown in FIG. 2C.
Optionally, the material of the third sub-layer 273 is polysilicon;
the doping element is nitrogen.
The following description will be given taking the example where the material of the first sublayer 271 is a polysilicon material, the material of the second sublayer 272 is a nitride material, and the material of the third sublayer 273 is a polysilicon material. After the charge storage layer is formed, the first sub-layer 271 is deposited on the entire surface of the charge storage layer, the second sub-layer 272 is deposited on the entire surface of the first sub-layer 271, and the third sub-layer 273 is deposited on the entire surface of the second sub-layer 272, that is, the first sub-layer 271, the second sub-layer 272, and the third sub-layer 273 are sequentially stacked along the radial direction of the channel hole 25, as shown in fig. 2A. Then, nitrogen is implanted into the third sub-layer 273 on the bottom wall of the channel hole 25 in a direction perpendicular to the substrate 20, so as to modify the material at the bottom of the third sub-layer 273 into a polysilicon material doped with nitrogen, thereby forming the second handle layer 28, as shown in fig. 2B. Then, an oxidizing gas such as oxygen is supplied into the channel hole 25, and the third sub-layer 273 on the sidewall of the channel hole 25 is oxidized to form the first processed layer 29 made of silicon oxide, as shown in fig. 2C. In the oxidation process, on the one hand, the second process layer 28 is not easily oxidized because it is doped with nitrogen; on the other hand, due to the blocking effect of the second sub-layer 272, the first sub-layer 271, which is made of polysilicon, is not oxidized. An etch selectivity is provided between the first processed layer 29, which is made of silicon oxide, and the second processed layer 28, which is made of polysilicon doped with nitrogen.
Step S13, the second handle layer 28 is removed, exposing the charge storage layer, as shown in fig. 2D.
In order to avoid damage to the first handle layer 29 caused by plasma bombardment during dry etching, thereby ensuring that the charge storage layer on the sidewall of the channel hole 25 is protected by the first handle layer 29 during the removal of the second handle layer 28, optionally, the second handle layer 28 is selectively removed by a wet etching process.
Optionally, the specific step of exposing the charge storage layer includes:
and selectively removing the second processing layer 28, the second sublayer 272 on the bottom wall of the charge storage layer and the first sublayer 273 on the bottom wall of the charge storage layer by using a wet etching process to expose the charge storage layer.
For example, due to the etch selectivity between the first handle layer 29 and the second handle layer 28, the second handle layer 28 can be removed by a wet etching process by selecting an appropriate etching reagent, exposing the second sub-layer 272 and leaving the first handle layer 29. Then, since the material of the first processing layer 29 is silicon oxide and the material of the second sub-layer 272 is silicon nitride, the second sub-layer 272 on the bottom wall of the channel hole 25 can also be selectively removed by a wet etching process, and the first processing layer 29 remains. The first sub-layer 271 is made of polysilicon, so that the first sub-layer 271 on the bottom wall of the channel hole 25 can be selectively removed by a wet etching process, and the first processing layer 29 is still remained, thereby obtaining the structure shown in fig. 2D. In the process of exposing the charge storage layer, a wet etching process is adopted, so that bombardment of plasma on the film layer on the side wall of the channel hole 25 in the dry etching process is avoided, and the completeness of the morphology of the side wall of the charge storage layer is ensured.
Step S14, removing the charge storage layer at the bottom of the channel hole 25, and exposing the epitaxial layer 30, as shown in fig. 2G.
In order to avoid damage to the film layer on the sidewall of the channel hole 25 due to plasma bombardment in the dry etching process, optionally, the charge storage layer at the bottom of the channel hole 25 is removed by using a wet etching process, and the epitaxial layer 30 is exposed.
Optionally, the charge storage layer includes a blocking layer 261 covering the sidewall of the channel hole 25 and the surface of the epitaxial layer 30, a charge trapping layer 262 covering the surface of the blocking layer 261, and a tunneling layer 263 covering the surface of the charge trapping layer 262; the first handle layer 29 is the same material as the tunneling layer 263; the specific steps of removing the charge storage layer at the bottom of the channel hole 25 further include:
a wet etching process is used to simultaneously remove the first handle layer 29 and the tunneling layer 263 on the bottom wall of the channel hole 25, exposing the charge trapping layer 262 and the second sublayer 272 on the sidewall of the charge storage layer, as shown in fig. 2E.
For example, the materials of the first handle layer 29 and the tunneling layer 263 are silicon oxide, the first handle layer 29 has an etching selectivity with respect to the second sub-layer 272 made of silicon nitride, the tunneling layer 263 also has an etching selectivity with respect to the charge trapping layer 262 made of nitride, and by selecting an appropriate etching reagent, the first handle layer 29 and the tunneling layer 263 can be removed simultaneously by a one-step wet etching process with the second sub-layer 272 and the charge trapping layer 262 as an etching stop layer, so as to form the structure shown in fig. 2E.
Optionally, the second sublayer 272 is the same material as the charge trapping layer 262; the specific steps of removing the charge storage layer at the bottom of the channel hole 25 further include:
the second sub-layer 272 and the charge trapping layer 262 on the bottom wall of the channel hole 25 are simultaneously removed by a wet etching process, exposing the blocking layer 261 and the first sub-layer 271 on the sidewall of the charge storage layer, as shown in fig. 2F.
For example, the second sub-layer 272 and the charge trapping layer 262 are made of silicon nitride, the second sub-layer 272 has an etching selectivity with respect to the first sub-layer 271 made of polysilicon, the charge trapping layer 262 also has an etching selectivity with respect to the blocking layer 261 made of oxide, by selecting a suitable etching reagent, the first sub-layer 271 and the blocking layer 261 can be used as an etching stop layer, and the second sub-layer 272 and the charge trapping layer 262 can be removed simultaneously by a one-step etching process, so as to form the structure shown in fig. 2F.
Optionally, the barrier layer 261 has an etching selectivity with respect to the first sublayer 271; the specific steps of removing the charge storage layer at the bottom of the channel hole 25 further include:
removing the blocking layer 261 on the bottom wall of the channel hole 25 by using a wet etching process to expose the epitaxial layer 30, as shown in fig. 2G;
the first sub-layer 271 is removed by a wet etching process, as shown in fig. 2H.
For example, the barrier layer 261 made of silicon oxide has an etching selectivity with respect to the first sub-layer 271 made of polysilicon, and when the auxiliary layer 24 is also made of silicon oxide, the barrier layer 261 and the auxiliary layer 24 above the bottom of the channel hole 25 can be removed by a wet etching process by selecting an appropriate etching reagent to form an opening 31 exposing the epitaxial layer 30, as shown in fig. 2G. In the etching process of this step, due to the protection effect of the first sub-layer 271, the charge storage layer on the sidewall of the channel hole 25 is not etched, and is not damaged by the bombardment of plasma. Finally, a suitable etching reagent is selected, and the first sub-layer 271 is removed by a wet etching process, so as to obtain the structure shown in fig. 2H. And then, depositing a polysilicon material on the surface of the charge storage layer and the surface of the epitaxial layer 30 to form a channel layer.
Moreover, the present embodiment further provides a three-dimensional memory. The three-dimensional memory provided in this embodiment mode can be formed by any one of the above-described methods for forming a three-dimensional memory. The specific structure of the three-dimensional memory can be seen in fig. 2A-2H. As shown in fig. 2A to fig. 2H, the three-dimensional memory provided in this embodiment includes:
a base including a substrate 20, a stack structure 21 on the surface of the substrate, a channel hole 25 penetrating the stack structure 21, and an epitaxial layer 30 on the surface of the substrate 20 and exposed to the bottom of the channel hole 25;
the charge storage layer covers the inner wall of the channel hole 25, an opening 31 exposing the epitaxial layer 30 is formed in the bottom of the charge storage layer, the opening 31 is formed in the position, where the side wall of the charge storage layer covers the first processing layer 29 and the bottom wall of the charge storage layer covers the second processing layer 28, after the second processing layer 28 is removed, of the bottom wall of the charge storage layer, the second processing layer 28 and the charge storage layer are formed, and the first processing layer 29 has etching selectivity relative to the second processing layer 28 and the charge storage layer.
In particular, the material of the substrate 20 may be, but is not limited to, silicon. The stack structure 21 includes interlayer insulating layers 211 and sacrificial layers 212 alternately stacked on the surface of the substrate 20 in a direction perpendicular to the substrate 20. The material of the interlayer insulation 211 may be an oxide material (e.g., silicon dioxide), and the material of the sacrificial layer 212 may be a nitride material (e.g., silicon nitride). By controlling the etching selectivity of the first processing layer 29 relative to the second processing layer 28, the second processing layer 28 can be selectively removed by a wet etching process without damaging the first processing layer 29, so that the charge storage layer on the sidewall of the channel hole 25 is protected, and the charge storage layer after the opening 31 is formed has a flat surface. Optionally, an etching selection ratio between the first handle layer 29 and the second handle layer 28 is greater than 3, and an etching selection ratio between the first handle layer 29 and the charge storage layer is also greater than 3. The first handle layer 29 and the second handle layer 28 may be formed using a deposition process in combination with an ion implantation and/or oxidation process.
Optionally, the three-dimensional memory further includes an auxiliary layer 24, and the opening 31 penetrates the auxiliary layer 24 in a direction perpendicular to the substrate 20. The auxiliary layer 24 is used to prevent damage to the epitaxial layer 30 during the subsequent etching process to form the opening 31. The material of the auxiliary layer 24 may be, but is not limited to, an oxide material.
Optionally, the material of the second processed layer 28 is a polysilicon material doped with nitrogen element, and the material of the first processed layer 29 is an oxide material.
Optionally, the first processed layer 29 is a single-layer structure or a multi-layer structure sequentially stacked in a radial direction of the channel hole 25;
the second processed layer 28 has a single-layer structure or a multi-layer structure sequentially stacked in a radial direction of the channel hole 25.
Optionally, a first sublayer 271 and a second sublayer 272 are respectively disposed between the charge storage layer and the first handle layer 29 and between the charge storage layer and the second handle layer 28, the second sublayer 272 is located on a side of the first sublayer 271 facing away from the charge storage layer, and the second sublayer 272 has an etching selectivity with respect to the first sublayer 271.
Specifically, the first sub-layer 271 continuously covers the entire surface of the charge storage layer, the second sub-layer 272 continuously covers the entire surface of the first sub-layer 271 facing away from the charge storage layer, that is, the first sub-layer 271 and the second sub-layer 272 are sequentially stacked in the radial direction of the channel hole 25, the first processing layer 29 covers the sidewall surface of the second sub-layer 272, and the second processing layer 28 covers the sidewall surface of the first sub-layer 271.
Optionally, the charge storage layer includes a blocking layer 261, a charge trapping layer 262 and a tunneling layer 263 sequentially stacked in a radial direction of the channel hole 25;
the first handle layer 29 is made of the same material as the tunneling layer 263 so that the tunneling layer 263 and the first handle layer 29 can be removed simultaneously during the formation of the opening 31.
For example, the materials of the first handle layer 29 and the tunneling layer 263 are silicon oxide, the first handle layer 29 has an etching selectivity with respect to the second sub-layer 272, which is silicon nitride, and the tunneling layer 263 also has an etching selectivity with respect to the charge trapping layer 262, which is nitride, and by selecting an appropriate etching reagent, the first handle layer 29 and the tunneling layer 263 can be removed simultaneously by a one-step wet etching process with the second sub-layer 272 and the charge trapping layer 262 as an etching stop layer.
Optionally, the second sub-layer 272 is made of the same material as the charge trapping layer, so that the charge trapping layer 262 and the second sub-layer 272 can be removed simultaneously during the process of forming the opening 31.
For example, the second sub-layer 272 and the charge trapping layer 262 are made of silicon nitride, the second sub-layer 272 has an etching selectivity with respect to the first sub-layer 271 made of polysilicon, the charge trapping layer 262 also has an etching selectivity with respect to the blocking layer 261 made of oxide, and by selecting an appropriate etching reagent, the first sub-layer 271 and the blocking layer 261 can be used as an etching stop layer, and the second sub-layer 272 and the charge trapping layer 262 can be removed simultaneously by a one-step etching process.
Optionally, the blocking layer 261 has an etch selectivity with respect to the first sub-layer 271.
Optionally, the material of the first sub-layer 271 is a polysilicon material.
Specifically, the blocking layer 261 is made of an oxide material, and the oxide material has a higher etching selectivity relative to a polysilicon material, so that the first sub-layer 271 can protect the charge storage layer on the sidewall of the channel hole 25. Thereafter, a suitable etching reagent is selected, and the first sub-layer 271 is removed by a wet etching process.
The three-dimensional memory further comprises a channel layer, and the channel layer covers the surface of the charge storage layer and the surface of the epitaxial layer 30.
In the three-dimensional memory and the forming method thereof provided by the present embodiment, the first processing layer and the second processing layer are respectively formed on the surface and the side wall of the charge storage layer inside the trench hole, and the first processing layer and the second processing layer are controlled to have etching selectivity with respect to each other, and the first processing layer also has etching selectivity with respect to the charge storage layer, so that the second processing layer and the charge storage layer at the bottom of the trench hole can be selectively removed by an etching process in a subsequent process, thereby avoiding damage to the charge storage layer on the side wall of the trench hole, ensuring the integrity of the morphology of the side wall of the charge storage layer, improving the electrical performance of the core region of the three-dimensional memory, and improving the yield of the three-dimensional memory.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (19)

1. A method for forming a three-dimensional memory is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a substrate, a stacking structure positioned on the surface of the substrate, a channel hole penetrating through the stacking structure, an epitaxial layer positioned on the surface of the substrate and exposed at the bottom of the channel hole, and a charge storage layer covering the inner wall of the channel hole and the surface of the epitaxial layer;
forming a first processing layer on the surface of the side wall of the charge storage layer and forming a second processing layer on the surface of the bottom wall of the charge storage layer, wherein the first processing layer has etching selectivity relative to the second processing layer and the charge storage layer;
removing the second processing layer to expose the charge storage layer;
and removing the charge storage layer at the bottom of the channel hole to expose the epitaxial layer.
2. The method of claim 1, wherein the steps of forming a first process layer on a sidewall surface of the charge storage layer and forming a second process layer on a bottom wall surface of the charge storage layer comprise:
forming a protective layer on the surfaces of the side wall and the bottom wall of the charge storage layer;
modifying the protective layer on the side wall of the charge storage layer and/or the bottom wall of the charge storage layer to form the first processed layer and the second processed layer.
3. The method of claim 1, wherein the protective layer has a single-layer structure; or,
the protective layer is of a multilayer structure which is sequentially overlapped along the radial direction of the channel hole.
4. The method as claimed in claim 2, wherein the step of forming the protection layer on the surface of the sidewall and the bottom wall of the charge storage layer comprises:
forming a first sublayer on the surfaces of the side wall and the bottom wall of the charge storage layer;
forming a second sublayer covering the surface of the first sublayer, wherein the second sublayer has etching selectivity relative to the first sublayer;
and forming a third sublayer covering the surface of the second sublayer, wherein the third sublayer has etching selectivity relative to the second sublayer, and the protective layer comprising the first sublayer, the second sublayer and the third sublayer is formed.
5. The method according to claim 4, wherein the step of modifying the protective layer on the sidewall of the charge storage layer and/or the bottom wall of the charge storage layer comprises:
modifying the third sub-layer on the sidewalls of the second sub-layer and/or the bottom wall of the second sub-layer to form the first treated layer on the sidewalls of the second sub-layer and the second treated layer on the bottom wall of the second sub-layer.
6. The method of claim 5, wherein the step of forming the first processing layer on the sidewall of the second sub-layer and the second processing layer on the bottom wall of the second sub-layer comprises:
implanting doping elements into the third sub-layer on the bottom wall of the second sub-layer to form the second processing layer;
and oxidizing the third sub-layer on the side wall of the second sub-layer to form the first processing layer.
7. The method of claim 6, wherein the material of the third sub-layer is polysilicon;
the doping element is nitrogen.
8. The method of claim 5, wherein exposing the charge storage layer comprises:
and selectively removing the second processing layer, the second sublayer positioned on the bottom wall of the charge storage layer and the first sublayer positioned on the bottom wall of the charge storage layer by adopting a wet etching process, and exposing the charge storage layer.
9. The method as claimed in claim 8, wherein the charge storage layer comprises a blocking layer covering the sidewall of the channel hole and the surface of the epitaxial layer, a charge trapping layer covering the surface of the blocking layer, and a tunneling layer covering the surface of the charge trapping layer; the first processing layer is made of the same material as the tunneling layer; the specific step of removing the charge storage layer at the bottom of the channel hole further includes:
and simultaneously removing the first processing layer and the tunneling layer on the bottom wall of the channel hole by adopting a wet etching process, and exposing the charge trapping layer and the second sublayer on the side wall of the charge storage layer.
10. The method of claim 9, wherein the second sub-layer is the same material as the charge trapping layer; the specific step of removing the charge storage layer at the bottom of the channel hole further includes:
and simultaneously removing the second sublayer and the charge trapping layer on the bottom wall of the channel hole by adopting a wet etching process, and exposing the blocking layer and the first sublayer on the side wall of the charge storage layer.
11. The method of claim 10, wherein the barrier layer has an etch selectivity with respect to the first sub-layer; the specific step of removing the charge storage layer at the bottom of the channel hole further includes:
removing the barrier layer on the bottom wall of the channel hole by adopting a wet etching process to expose the epitaxial layer;
and removing the first sub-layer by adopting a wet etching process.
12. A three-dimensional memory, comprising:
the substrate comprises a substrate, a stacked structure positioned on the surface of the substrate, a channel hole penetrating through the stacked structure, and an epitaxial layer positioned on the surface of the substrate and exposed to the bottom of the channel hole;
the charge storage layer covers in the inner wall in channel hole, just the bottom of charge storage layer has one and exposes the opening of epitaxial layer, the opening is in the lateral wall of charge storage layer covers first processing layer, after charge storage layer diapire covers the second processing layer, get rid of the second processing layer with channel hole bottom the charge storage layer is formed, first processing layer for the second processing layer with the charge storage layer all has the sculpture selectivity.
13. The three-dimensional memory according to claim 12, wherein the material of the second processing layer is a polysilicon material doped with nitrogen element, and the material of the first processing layer is an oxide material.
14. The three-dimensional memory according to claim 12, wherein the first processed layer is a single-layer structure or a multi-layer structure sequentially stacked in a radial direction of the channel hole;
the second processing layer is of a single-layer structure or a multi-layer structure which is sequentially overlapped along the radial direction of the channel hole.
15. The three-dimensional memory according to claim 12, wherein a first sublayer and a second sublayer are provided between the charge storage layer and the first handle layer and between the charge storage layer and the second handle layer, the second sublayer being provided on a side of the first sublayer facing away from the charge storage layer, the second sublayer having an etch selectivity with respect to the first sublayer.
16. The three-dimensional memory according to claim 15, wherein the charge storage layer comprises a blocking layer, a charge trapping layer, and a tunneling layer sequentially stacked in a radial direction of the channel hole;
the first handle layer is of the same material as the tunneling layer such that the tunneling layer and the first handle layer can be removed simultaneously during formation of the opening.
17. The three-dimensional memory according to claim 16, wherein the second sublayer is the same material as the charge trapping layer, such that the charge trapping layer and the second sublayer can be removed simultaneously during the formation of the opening.
18. The three-dimensional memory according to claim 16, wherein the barrier layer has an etch selectivity with respect to the first sublayer.
19. The three-dimensional memory according to claim 18, wherein the material of the first sublayer is a polysilicon material.
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