CN111399588A - Clock signal generation circuit, driving method and electronic device - Google Patents
Clock signal generation circuit, driving method and electronic device Download PDFInfo
- Publication number
- CN111399588A CN111399588A CN202010190170.6A CN202010190170A CN111399588A CN 111399588 A CN111399588 A CN 111399588A CN 202010190170 A CN202010190170 A CN 202010190170A CN 111399588 A CN111399588 A CN 111399588A
- Authority
- CN
- China
- Prior art keywords
- clock
- phase
- signal
- output
- enable control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention provides a clock signal generating circuit, a driving method and electronic equipment, and relates to the technical field of digital circuits. The clock signal generation circuit includes: a counter for generating a phase setting value by counting according to a clock phase adjustment requirement; the decoding and synchronizing module is used for loading a phase initial value, receiving the phase setting value from the counter in the phase adjusting process, decoding the phase initial value or the phase setting value into an enabling control signal, and outputting the enabling control signal after synchronizing; and the clock selector is used for receiving the synchronizing processed enable control signal and selecting the input clock signals with the phases corresponding to the initial phase values or the phase setting values from the multipath input clock signals according to the enable control signal to be synthesized and output.
Description
Technical Field
The present invention relates to the field of digital circuit technologies, and in particular, to a clock signal generating circuit, a driving method, and an electronic device.
Background
The clock signal of the synchronous circuit system is more and more complex with the continuous improvement of the Integration and complexity of the digital circuit, the generation of the clock signal of the synchronous circuit system is more and more complex, a plurality of clock signals with different phases are often needed for a V L SI (Very L area Scale Integration, Very large Scale Integration) system such as FPGA (Field Programmable Gate Array), and a certain phase relation is required for some system applications, so that the phase of the clock signal is generally required to be dynamically adjusted to ensure the correctness of the circuit timing sequence and the function.
A commonly used clock signal phase selection scheme is shown in FIG. 1, wherein input clocks C L KIN < n:0> have a specific phase relationship, i.e. the phases between the clocks are continuous and can cover one clock cycle, and the method adopts MUX (multiplexer) to select the target phase clock as output, in the scheme, because the selection signal SE L x < m:0> is asynchronous signal, when the different phase clocks are switched by changing the selection signal, the output clock may generate glitch, which causes the function of the following logic circuit to be abnormal.
Disclosure of Invention
According to the clock signal generating circuit, the driving method and the electronic equipment provided by the embodiment of the invention, the phase of the clock signal generated by the scheme can be dynamically adjusted and switched, and no burr phenomenon exists during phase dynamic adjustment and switching.
In a first aspect, an embodiment of the present invention provides a clock signal generation circuit, including:
a counter for generating a phase setting value by counting according to a clock phase adjustment requirement;
a decoding and synchronizing module, configured to load a phase initial value in an initial phase implementation process and receive the phase setting value from the counter in a phase adjustment process, decode the phase initial value or the phase setting value into an enable control signal, and output the enable control signal after performing synchronization processing on the enable control signal, where the synchronization processing is to synchronize the enable control signal to a clock domain that needs to be adjusted;
and the clock selector is used for receiving the synchronizing processed enable control signal and selecting an input clock signal with a phase corresponding to the initial phase value or the phase setting value from a plurality of paths of input clock signals as an output according to the enable control signal, and the phases of the plurality of paths of input clock signals are continuous and can cover one clock cycle.
Optionally, the clock selector includes one or more clock selector units, the decoding and synchronizing module outputs one or more enable control signals, the enable control signals correspond to the clock selector units one to one, and the clock selector unit is configured to receive a corresponding synchronization-processed enable control signal from the decoding and synchronizing module, and select, as an output, an input clock signal having a phase corresponding to the initial phase value or the set phase value from the multiple input clock signals according to the corresponding synchronization-processed enable control signal.
Optionally, the decoding and synchronizing module includes: a decoder for decoding the initial phase setting value or the phase setting value into a plurality of enable control signals, wherein only one path of the enable control signals is a high level, and the rest are low levels; and the synchronization circuit is used for carrying out synchronization processing on the enable control signal and outputting the enable control signal, and the enable control signal after the synchronization processing is triggered by the falling edge of the input clock.
Optionally, the decoder is a 3-8 decoding circuit, and the synchronous circuit includes a first flip-flop, a second flip-flop, and eight output flip-flops;
a trigger end of the first flip-flop inputs a first input clock signal in the input clock signals, an input end of the first flip-flop is connected with an output end of the 3-8 decoding circuit, first to fourth bits from low to high in an output signal of the first flip-flop are output to input ends of first to fourth output flip-flops in the eight output flip-flops, and the first flip-flop is used for triggering sampling of an output signal of the 3-8 decoding circuit by a rising edge of the first input clock signal;
the trigger end of the second flip-flop inputs the first input clock signal, the input end of the first flip-flop receives the fourth to eighth bits from low bit to high bit in the output signal of the first flip-flop, the output end of the second flip-flop is connected with the input ends of the fifth to eighth output flip-flops in the eight output flip-flops, and the second flip-flop is used for sampling the fourth to eighth bits from low bit to high bit in the output signal of the first flip-flop and outputting the fourth to eighth bits after sampling the falling edge of the first input clock signal;
and the triggering ends of the eight output triggers are respectively input into one of the input clock signals, and the eight output triggers are respectively output after being sampled by the clock falling edge of the corresponding input clock signal.
Optionally, an input end of the first and gate receives the switched clock signal and the enable control signal corresponding thereto; the input end of the second AND gate receives a target switching clock signal and an enabling control signal corresponding to the target switching clock signal; and the output end of the OR gate is connected with the two input ends of the OR gate, and the output end of the OR gate is the output end of the clock selector.
In a second aspect, an embodiment of the present invention provides a driving method of the clock signal generating circuit, wherein the counter receives a dynamic phase adjustment trigger signal STEP _ N, a dynamic phase adjustment DIRECTION direct, a dynamic phase adjustment channel selection signal SE L < m:0>, a loading signal L OAD of the dynamic phase adjustment selected channel phase selection signal, and a current phase selection signal PHASENOW < m:0> of the dynamic phase adjustment selected channel, the decoding and synchronizing module receives a new phase selection signal PHASENEW < m:0> at the time of dynamic phase adjustment from an output terminal of the counter, the decoding and synchronizing module further receives an input clock signal C L KIN < N:0>, a dynamic phase adjustment trigger signal STEP _ N, a dynamic phase adjustment channel selection signal SE L < m:0> and each channel clock phase initial setting value PHASEINIT0/1/…/x < m:0>, the clock selector receives an enable control signal kec 7/35n/…/355631/35n < m:0> of each channel clock selector from an output terminal of the decoding and synchronizing module;
the driving method comprises the steps that the decoding and synchronizing module loads and stores phase initial values through initial setting values PHASEINIT0/1/…/x < m:0> of the phases of the clocks of all channels, decodes the phase initial values into corresponding enable control signals, then carries out synchronizing processing on the enable control signals, transmits the enable control signals after the synchronizing processing to corresponding clock selector units, and the clock selector units select input clock signals of corresponding phases from the input clock signals C L KIN < n:0> according to the phase initial values to serve as outputs.
The driving method further comprises a dynamic phase adjustment step, wherein the dynamic phase adjustment step comprises the steps of receiving a new phase selection signal PHASENEW < m:0> output by the counter during dynamic phase adjustment and decoding the new phase selection signal PHASENEW < m:0> into a selected channel enable signal (EN0/1/2 …/x < n:0>), wherein only 1 path of an enable signal n +1 path is high level, and the rest n paths are low level, then carrying out synchronization processing on the enable signal (EN0/1/2 …/x < n:0>), outputting an enable control signal C L KEN0/1.. x < n:0> after the synchronization processing, triggering the synchronization processing by the falling edge of the input clock C L KIN < n:0>, and respectively sending the enable control signal C L KEN0/1.. x < n:0> to a corresponding clock selection unit to serve as synchronous input control.
If the output channel is not changed during phase adjustment, the STEP of dynamic phase adjustment further comprises the STEPs that a counter acquires the DIRECTION of dynamic phase adjustment through a dynamic phase adjustment DIRECTION DIRECTION, at the moment, a dynamic phase adjustment channel selection signal SE L < m:0> is kept unchanged, then a loading signal L OAD of the dynamic phase adjustment selected channel phase selection signal is triggered to keep low level, then a current channel phase selection value PHASENOW < m:0> is loaded to the counter, then a STEP _ N signal is triggered, the counter achieves 1 adding or 1 subtracting when the STEP _ N rises according to the dynamic phase adjustment DIRECTION, the counter outputs a new phase selection value PHASENENM < m:0> and sends the new phase selection value PHASENOW to the decoding and synchronizing module, decoding is completed in the decoding and synchronizing module and synchronizes to a clock domain of an input clock, a new enabling control signal is output, the enabling control signal is transmitted to a corresponding clock selector unit, and the clock selector unit is switched to a new phase clock EW according to the enabling control signal.
If the output channel is not changed during the phase adjustment, the phase adjustment STEP further comprises that when the counter selects the dynamic phase adjustment DIRECTION according to the dynamic phase adjustment DIRECTION directive, the channel of the phase adjustment is selected according to a dynamic phase adjustment channel selection signal SE L < m:0>, the current phase selection signal PHASENOW < m:0> of the channel selected by the counter dynamic phase adjustment is transmitted to the counter, then the OAD signal is triggered L, the high level is kept for a period of time, the current channel phase selection value PHASENOW < m:0> is loaded to the counter, then the STEP _ N signal is triggered, the counter realizes 1 adding or 1 subtracting when the STEP _ N rises, the counter outputs a new phase selection value PHASENEW < m:0> and is transmitted to a decoding and synchronizing module, the decoding and synchronizing are finished in the module, the clock domain of the input clock C L KIN are synchronized, a new enable control signal is output, the enable control signal is transmitted to the corresponding clock selector unit, and the clock selector unit is switched to a new clock.
In a third aspect, an embodiment of the present invention further provides an electronic device, which includes any one of the clock signal generation circuits described above.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium stores computer instructions, and the computer instructions, when executed by a processor, implement the driving method of any one of the above.
According to the clock signal generating circuit, the driving method and the electronic device, in the scheme, a counter generates a phase setting value according to a clock phase adjusting requirement, and then the phase setting value is transmitted to a clock selector through a decoding and synchronizing module, the clock selector selects an input clock signal with a phase corresponding to the phase setting value from a plurality of paths of input clock signals as output according to the phase setting value, wherein the phases of the plurality of paths of input clock signals are continuous and can cover one clock period. Because the control signal input to the clock selector is controlled by the signal output by the decoding and synchronizing module, no glitch exists during the switching of the phase dynamic adjustment.
Drawings
FIG. 1 is a schematic diagram of a common clock signal phase selection scheme;
FIG. 2 is a schematic diagram of a clock signal generating circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a 3-8 decoding circuit constituting an exemplary decoding and synchronization module according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a synchronization circuit forming an exemplary decode and synchronization module according to an embodiment of the present invention;
FIG. 5 is a simplified logic diagram of an exemplary clock selector suitable for use in the clock signal generation circuit of FIG. 2 according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a clock initial phase timing diagram of a clock signal generating circuit suitable for the present embodiment;
FIG. 7 is a timing diagram illustrating clock phase adjustment of the clock signal generating circuit according to the present embodiment;
fig. 8 is a timing diagram of clock phase adjustment internal signals of the clock signal generating circuit according to the present embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, because the selection signal SE L x < m:0> in the clock signal phase selection scheme shown in FIG. 1 is an asynchronous signal, when the selection signal is changed to realize the switching of clocks with different phases, the output clock may generate glitches, which causes the function abnormality of the following logic circuit, so the scheme shown in FIG. 1 usually realizes the static selection clock;
in order to solve the above two main problems, the inventor proposes a new design idea of a clock phase dynamic adjustment circuit, in which a clock signal generation circuit only needs one counter and a clock selector circuit, and is matched with other logic circuits to implement the phase adjustability of a clock signal, and can implement dynamic forward or reverse cycle adjustment (which can continuously accumulate more than one clock cycle delay or advance), and an output clock has no glitch. The following describes aspects of the present application with reference to the drawings.
As shown in fig. 2, an embodiment of the present invention provides a clock signal generating circuit, which includes a Counter (COUNT)11, a DECODE and synchronization module (DECODE & SYNC)12, and a clock selector (phaese L0/1./x) 13.
The counter 11 is used to generate a phase setting value by counting according to the clock phase adjustment requirement.
The decoding and synchronizing module 12 is configured to load a phase initial value in an initial phase implementation process, receive the phase setting value from the counter 11 in a phase adjustment process, decode the phase initial value or the phase setting value into an enable control signal, perform synchronization processing on the enable control signal, and output the enable control signal, where the synchronization processing is to synchronize the enable control signal to a clock domain that needs to be adjusted.
The clock selector 13 is configured to receive the synchronization-processed enable control signal, and select, as an output, an input clock signal having a phase corresponding to the initial phase value or the set phase value from among multiple input clock signals according to the enable control signal, where the multiple input clock signals have consecutive phases and may cover one clock cycle.
The present embodiment can realize the count of 1 plus or 1 minus cycle through the counter 11, or other step size. The counter can be controlled to count according to a certain time sequence by adjusting the interface signal according to the clock phase adjustment requirement, so that the phase adjustment information is converted into a digital phase setting value. For example, the larger the adjusted phase, the longer the count time, and the larger the number representing the phase setting value to be output.
In some embodiments, as shown in fig. 2 and 6, the counter 11 may be, for example, a counter 11 receiving a dynamic phase adjustment trigger signal STEP _ N, a dynamic phase adjustment DIRECTION direct, a dynamic phase adjustment channel selection signal SE L < m:0>, a loading signal L OAD of the dynamic phase adjustment selected channel phase selection signal, and a current phase selection signal PHASENOW < m:0> of the dynamic phase adjustment selected channel, outputting a new phase selection signal PHASENEW < m:0> when dynamic phase adjustment is performed to the decode and synchronization module, the counter 11 controlling the counter to add 1 or subtract 1 through direct (including dynamic phase adjustment DIRECTION information), then triggering L OAD signal (keeping high level for a period of time) to load the selected channel phase selection PHASENOW < m:0> to the counter, and outputting the new phase selection signal PHASENOW < m:0> when the clock signal STEP _ N rises.
The decoding and synchronizing module 12 of this embodiment stores an initial phase setting value, receives an output of the counter 11, determines which output clock needs phase adjustment, updates the phase setting value, and generates an enable control signal according to the phase initial value or the phase setting value.
As shown in fig. 2 and fig. 6, in an alternative embodiment, the decoding and synchronizing module 12 loads an initial phase setting value PHASEINIT0/1.. x < m:0> during an initial phase process, decodes the initial phase setting value into a control signal EN0/1.. x < n:0> corresponding to each channel, synchronizes the control signals EN0/1.. x < n:0> to a clock domain to be adjusted, and outputs a synchronized enable control signal C L KEN0/1.. x < n:0>, so as to achieve synchronization of the input control signal of the initial phase process clock selector module (subsequent module), and receives a signal PHASENEW < m:0> output by the counter 11 during a phase dynamic adjustment process, decodes the synchronized enable control signal into an EN0/1.. x < n:0> output by the selected channel 0/1.. x < n:0> and synchronizes the input control signal n0/1.. x < n:0> to a clock domain to be adjusted, so as to achieve synchronization of the input control signal C860/n synchronization process in the phase dynamic adjustment process.
In an alternative embodiment, the clock selector 13 includes one or more clock selector units (phasse L0/1./x), the decode and synchronization module 12 outputs one or more enable control signals, the enable control signals correspond to the clock selector units one to one, and the clock selector unit is configured to receive corresponding synchronization processed enable control signals from the decode and synchronization module 12 and select an input clock signal with a phase corresponding to the initial phase value or the phase setting value among the multiple input clock signals C L KIN < n:0> according to the corresponding synchronization processed enable control signals as an output.
In an optional embodiment, the decoding and synchronizing module 12 includes a decoder configured to decode the initial phase setting value or the phase setting value into a plurality of enable control signals, where only one of the enable control signals is at a high level and the others are at a low level, and a synchronizing circuit configured to synchronize and output the enable control signals, where the synchronized enable control signals are triggered by a falling edge of an input clock C L KIN < n:0 >.
As shown in fig. 3, the decoder may be a 3-8 decoding circuit.
As shown in FIG. 4, the synchronous circuit may include a first flip-flop, a second flip-flop, and eight output flip-flops, wherein a trigger terminal of the first flip-flop inputs a first input clock signal C L CK <0> of the input clock signals C L KIN < n:0>, an input terminal of the first flip-flop is connected to an output terminal of the 3-8 decoding circuit, first to fourth bits <3:0> of the output signal of the first flip-flop from low to high are output to input terminals of first to fourth output flip-flops of the eight output flip-flops, the first flip-flop is configured to sample an output signal of the 3-8 decoding circuit triggered by a rising edge of the first input clock signal C L CK <0>, an output signal of the eight output flip-flop is input with the first input clock signal C L CK <0>, an input terminal of the first flip-flop receives a fourth to eighth bits <7:4> of the output signal from low to high of the output signal of the first flip-flop, and an input terminal of the second flip-flop receives a falling signal C590 of the output signal of the eight output flip-flops from the eight output signal C590, and output flip-flops are respectively connected to a falling edge of the eight input flip-flop, the eight output flip-flop, the output flip-flop, and output signal C590 from an output terminal of the eight output flip-flop is output from an output signal C590, a falling edge of the eight output flip-flop is output signal output from an output terminal of the eight output flip-flop, and output flip-flop is output signal C590, a falling edge of the eight output flip-flop is output flip-flop, and output from an output terminal of the.
The clock selector of the embodiment receives the enable control signal C L KEN0/1.. x < n:0> output by the decoding and synchronizing module, and switches to a new phase clock to output according to a proper logic design in the clock selector module according to the change of the input enable control signal C L KEN0/1.. x < n:0> (after clock synchronization).
The clock selector may include one or more clock selection units, which correspond one-to-one to the output channels (or output clocks). The clock selection unit acquires a phase setting value of a corresponding output channel from the decoding and synchronizing module, and then selects an input clock signal with a phase corresponding to the phase setting value from the multi-path input clock signals as output.
In an alternative embodiment, as shown in fig. 5, the clock selector unit comprises: the input end of the first AND gate receives the switched clock signal and the corresponding enable control signal; the input end of the second AND gate receives a target switching clock signal and an enabling control signal corresponding to the target switching clock signal; and the output end of the OR gate is connected with the two input ends of the OR gate, and the output end of the OR gate is the output end of the clock selector. The switched clock signal herein refers to an input clock having the same phase as the output clock of the channel before the phase adjustment, and the target switched clock signal refers to an input clock having the same phase as the output clock of the channel after the phase adjustment.
The embodiment of the present invention further provides a driving method of the above clock signal generation circuit, in the initial phase adjustment implementation process, the driving method includes that the decoding and synchronization module 12 loads and stores the initial phase value through the initial setting value PHASEINIT0/1/…/x < m:0> of each channel clock phase, decodes the initial phase value into the corresponding enable control signal, then synchronizes each enable control signal, and transmits each enable control signal C L KEN0/1/…/x < n:0> after the synchronization processing to the corresponding clock selector unit, and the clock selector unit selects the input clock signal of the corresponding phase as output in the input clock signal C L KIN < n:0> according to the initial phase value.
The driving method further comprises a dynamic phase adjustment step, wherein the dynamic phase adjustment step comprises the steps of receiving a new phase selection signal PHASENEW < m:0> output by the counter 11 during dynamic phase adjustment and decoding the new phase selection signal PHASENEW < m:0> into a selected channel enable signal (EN0/1/2 …/x < n:0>), wherein only 1 path of an enable signal n +1 path is high level, and the rest n paths are low level, then carrying out synchronization processing on the enable signal (EN0/1/2 …/x < n:0>), outputting an enable control signal C L KEN0/1.. x < n:0> after the synchronization processing, triggering the synchronization processing is carried out by the falling edge of the input clock C L KIN < n:0>, and respectively sending the enable control signal C L KEN0/1.. x < n:0> to a corresponding clock selection unit to serve as a synchronization input control clock.
The clock signal generating circuit and the driving method thereof according to the present invention will be further described with reference to the accompanying drawings.
As shown in FIG. 2, in some embodiments, the counter 11 receives a dynamic phase adjustment trigger signal STEP _ N, a dynamic phase adjustment DIRECTION DIRECTION, a dynamic phase adjustment channel selection signal SE L < m:0>, a loading signal L OAD of the dynamic phase adjustment selected channel phase selection signal, and a current phase selection signal PHASENOW < m:0> of the dynamic phase adjustment selected channel, and outputs a new phase selection signal PHASENEW < m:0> at the time of dynamic phase adjustment to the decoding and synchronizing module 12.
The decoding and synchronizing module 12 receives a new phase selection signal PHASENEW < m:0> from the output end of the counter 11, and also receives an input clock signal C L KIN < N:0>, a dynamic phase adjustment trigger signal STEP _ N, a dynamic phase adjustment channel selection signal SE L < m:0>, and initial setting values of each channel clock phase PHASEINIT0/1/…/x < m:0>, and outputs enable control signals C L KEN0/1/…/x < m:0> of each channel clock selector to the clock selector 13.
The clock selector 13 includes a plurality of clock selector units (PHASESE L0/1./x), each of the clock selector units (PHASESE L0/1./x) receives the enable control signal C L KEN0/1/…/x < m:0> of the corresponding channel from the output terminal of the decode and synchronization module 12, and the clock selector also receives the input clock signal C L KIN < n:0>, and the output clock is C L KOUT0/1/…/x.
The counter is realized by controlling the counter to add 1 or subtract 1 through the dynamic phase adjustment DIRECTION DIRECTION, then triggering L OAD signal (keeping high level for a period of time) to load the selected channel phase selection value PHASENOW < m:0> into the counter, adding 1 or subtracting 1 on the basis of PHASENOW < m:0> at the rising edge of clock signal STEP _ N, and outputting a new phase selection signal PHASENEW < m:0 >.
The decoding and synchronization module implementation process comprises the steps that in the initial phase implementation process, firstly, phase initial values (PHASEINIT0/1/2 …/x < m:0>) are loaded and decoded into respective enable signals (EN0/1/2 …/x < n:0>), wherein only 1 path of n +1 paths of enable signals is high level, the rest n paths of enable signals are low level, then the enable signals (EN0/1/2 …/x < n:0>) are synchronized, and synchronized enable control signals C L KEN0/1.. x < n:0> are output, the output signals are triggered by falling edges of an input clock C L KIN < n:0>, and finally the enable signals C L KEN0/1.. x < n:0> are respectively sent to respective clock selection units to be used as synchronous input control.
As shown in fig. 3, taking m 2 as an example, decoding can be realized by a 3-8 decoding circuit, PHASE <2:0> setting value is determined, only 1 way of the output enable signal EN <7:0> is high level, and the other 7 ways are low level, then the enable signal (EN0/1/2 …/x < n:0>) is synchronized, and a synchronized enable control signal C L KEN0/1.. x < n:0> is output, as shown in fig. 4, taking n 7 as an example, the decoding circuit outputs EN <7:0> first triggers DFF0 sampling output by a rising edge of C L KIN <0>, according to the PHASE relationship of the input clock C L KIN <7:0> and the control relationship between the clock and the enable signal, the sampled enable signal <7:0> is divided into two groups, wherein the low bit <3:0> is directly sent to the corresponding falling edge, the sampled enable signal is sent to the corresponding falling edge of the clock C367: 0>, and then the sampled enable signal is sent to a falling edge of C367: 3:0, and finally sent to a falling edge of the corresponding sampling clock 3: 4930, and then the synchronous output is sent to a falling edge of the corresponding clock C367: 3:0, and finally sent to the corresponding sampling edge of the sampling clock 3: 3, and then is sent to the corresponding sampling edge of the corresponding sampling clock n < 7.
Secondly, in the dynamic phase adjustment realization process, PHASENEW < m:0> output by the counter 11 is received and decoded into a selected channel enable signal (EN0/1/2 …/x < n:0>), wherein only 1 path of the n +1 paths of enable signals is high level, and the other n paths of enable signals are low level, then the enable signal (EN0/1/2 …/x < n:0>) is synchronized, and an enable control signal C L KEN0/1.. x < n:0> is output after synchronization, the output signal is triggered by the falling edge of an input clock C L KIN < n:0>, and finally the enable control signal C L KEN0/1.. x < n:0> is respectively sent to respective clock selectors to be used as synchronous input control.
As shown in FIG. 6, taking the initial phase implementation process of the output clock C L KOUT0/1/2 as an example, the initial phase values PHASEINIT0/1/2< m:0> are (m +1) ' b0 … 000/0 … 001/0 … 010 respectively, the initial value difference between two adjacent clocks is (m +1) ' b0 … 001, that is, the phase difference between two adjacent clocks of the output clock C L KOUT0/1/2 is T/(n +1), the enable control signals C L KEN0/1/2< n:0> generated after the decoding and synchronization processes are respectively performed are (n +1) ' b0 … 000/0 … 010/0 … 100 respectively, wherein only 1 path of each enable signal is 1, and the rest n paths are 0, the enable control signals are respectively sent to the respective clock selectors to select the corresponding phase clocks as outputs.
The clock selector realizes the process that: the switched clock signal and its corresponding enable control signal are anded (and logically processed) to obtain a signal a, the target switching clock signal and its corresponding enable control signal are anded (and logically processed) to obtain a signal B, and then the signals a + B are anded (or logically processed), so that a glitch-free clock switching process is realized, and the simple logic is as shown in fig. 5.
The dynamic adjustment process of the clock phase is implemented according to a certain timing sequence through a digital interface, and as shown in fig. 7, a schematic diagram of the timing sequence of the clock phase adjustment is shown.
The dynamic adjustment does not change the channel process, firstly selects the dynamic phase adjustment DIRECTION through DIRECTION, at this time SE L < m:0> is kept unchanged, then triggers L OAD signal and keeps high level for a period of time, the current channel phase selection value PHASENOW < m:0> is loaded to the counter, then triggers STEP _ N signal, according to the adjustment DIRECTION counter, when STEP _ N rises, the counter realizes adding 1 or subtracting 1, the counter outputs the new phase selection value PHASENEW < m:0> to the decoding and synchronization module, completes decoding in the module and synchronizes to C L KIN clock domain, outputs the new enable control signal, and finally the enable control signal is sent to the corresponding clock selector module to switch to the new phase clock.
As shown in fig. 8, taking the output clock C L KOUT0/1 as an example, the initial phase values PHASEINIT0/1< m:0> are (m +1) ' b0 … 000/0 …, respectively, the two clock initial values differ by (m +1) ' b0 …, i.e. the initial phase difference of the output clock C L KOUT0/1 is T/(N +1), C L KOUT0 is selected for dynamic backward adjustment, when PHASENOW is equal to PHASEINIT0< m:0>, i.e. (m +1) ' b0 … 000, the STEP _ N signal is triggered to generate a new phase selection value, the counter is added with 1 on the basis of asenow and updated to PHASENEW, when PHASENEW is changed from (m +1) ' b0 … 000 to (m +1) ' b0 …, the new phase selection value is switched to the input clock C L N <7:0> clock domain after the decoding and synchronization module is completed, when the phase selection value is changed from (m +1) ' b0 … 000 to (m +1) ' b0 …), the new phase selection value is switched to the high clock selection level as the output clock level of the dynamic phase difference of the clock C L/460, which is switched to the low clock level/(N465) which is switched to the output clock level which is switched to the low clock level of the dynamic level < e < C L < k 460/(N465 < N466 level after the output clock 466 level is switched to the output.
The dynamic adjustment channel changing process is that when the DIRECTION selects the dynamic phase adjustment DIRECTION, the SE L < m:0> is changed simultaneously, the current phase selection value of the target channel is sent to PHASENOW < m:0>, then L OAD signals are triggered and kept at a high level for a period of time, the current channel phase selection value PHASENOW < m:0> is loaded to a counter, then STEP _ N signals are triggered, 1 is added or subtracted according to the rising edge of the STEP _ N of the adjustment DIRECTION counter, the counter outputs a new phase selection value PHASENEW < m:0> and then is sent to a decoding and synchronizing module, decoding is completed in the module and synchronized to a C L KIN clock domain, a new enabling control signal is output, and finally the enabling control signal is sent to a corresponding clock selector module and is switched to a new phase clock.
As shown in fig. 7, the respective timing relationships between the signals need to be satisfied to ensure that the current dynamic adjustment is valid.
The clock signal generating circuit and the driving method thereof provided by the embodiment of the invention adopt the design idea of the timer, so that the clock phase can be adjusted in a forward or reverse cycle manner, the output clock has no burrs, and the clock can be dynamically switched among multiple paths of clocks and the phase adjustment can be carried out.
The clock signal generating circuit provided by the embodiment of the invention is particularly suitable for the field of multiple clocks of which the phase of a certain output clock signal needs to be continuously adjusted.
An embodiment of the present invention also provides an electronic device including the clock signal generation circuit described in any one of the above.
Embodiments of the present invention also provide a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions, when executed by a processor, implement any of the above-mentioned driving methods.
The invention relates to a clock phase dynamic adjusting Circuit of a Digital Circuit System (Digital Circuit System), in particular to a clock phase continuous adjusting Circuit which continuously adjusts the clock phase according to a certain time sequence through a specific Digital interface according to the application requirement in the field of multiple clocks of which a certain path of clock phase needs to be continuously adjusted. By adopting the proposed design sequence and thought, firstly, the forward or reverse cycle adjustment of the clock phase can be realized, and the output clock has no burr, and secondly, the switching between the multi-path clocks can be carried out and the phase adjustment can be carried out.
It will be understood by those skilled in the art that all or part of the processes of the embodiments of the methods described above may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (11)
1. A clock signal generation circuit, comprising:
a counter for generating a phase setting value by counting according to a clock phase adjustment requirement;
a decoding and synchronizing module, configured to load a phase initial value in an initial phase implementation process and receive the phase setting value from a counter in a phase adjustment process, decode the phase initial value or the phase setting value into an enable control signal, and output the enable control signal after performing synchronization processing on the enable control signal, where the synchronization processing is to synchronize the enable control signal to a clock domain that needs to be adjusted;
and the clock selector is used for receiving the synchronizing processed enable control signal and selecting an input clock signal with a phase corresponding to the initial phase value or the phase setting value from a plurality of paths of input clock signals as an output according to the enable control signal, and the phases of the plurality of paths of input clock signals are continuous and can cover one clock cycle.
2. The clock signal generation circuit of claim 1,
the clock selector comprises one or more clock selector units, the decoding and synchronizing module outputs one or more enable control signals, the enable control signals correspond to the clock selector units one to one, and the clock selector units are used for receiving corresponding enable control signals after synchronous processing from the decoding and synchronizing module and selecting input clock signals with phases corresponding to the initial phase values or the phase setting values from the multipath input clock signals according to the corresponding enable control signals after synchronous processing to serve as output.
3. The clock signal generation circuit of claim 2, wherein the decode and synchronization module comprises:
a decoder for decoding the initial phase setting value or the phase setting value into a plurality of enable control signals, wherein only one path of the enable control signals is a high level, and the rest are low levels;
and the synchronization circuit is used for carrying out synchronization processing on the enable control signal and outputting the enable control signal, and the enable control signal after the synchronization processing is triggered by the falling edge of the input clock.
4. The clock signal generation circuit of claim 3,
the decoder is a 3-8 decoding circuit, and the synchronous circuit comprises a first trigger, a second trigger and eight output triggers;
a trigger end of the first flip-flop inputs a first input clock signal in the input clock signals, an input end of the first flip-flop is connected with an output end of the 3-8 decoding circuit, first to fourth bits from low to high in an output signal of the first flip-flop are output to input ends of first to fourth output flip-flops in the eight output flip-flops, and the first flip-flop is used for triggering sampling of an output signal of the 3-8 decoding circuit by a rising edge of the first input clock signal;
the trigger end of the second flip-flop inputs the first input clock signal, the input end of the first flip-flop receives the fourth to eighth bits from low bit to high bit in the output signal of the first flip-flop, the output end of the second flip-flop is connected with the input ends of the fifth to eighth output flip-flops in the eight output flip-flops, and the second flip-flop is used for sampling the fourth to eighth bits from low bit to high bit in the output signal of the first flip-flop and outputting the fourth to eighth bits after sampling the falling edge of the first input clock signal;
and the triggering ends of the eight output triggers are respectively input into one of the input clock signals, and the eight output triggers are respectively output after being sampled by the clock falling edge of the corresponding input clock signal.
5. The clock signal generation circuit of claim 1, wherein the clock selector unit comprises:
the input end of the first AND gate receives the switched clock signal and the corresponding enable control signal;
the input end of the second AND gate receives a target switching clock signal and an enabling control signal corresponding to the target switching clock signal;
and the output end of the OR gate is connected with the two input ends of the OR gate, and the output end of the OR gate is the output end of the clock selector.
6. A driving method of the clock signal generation circuit according to any one of claims 1 to 5,
the counter receives a dynamic phase adjustment trigger signal STEP _ N, a dynamic phase adjustment DIRECTION DIRECTION, a dynamic phase adjustment channel selection signal SE L < m:0>, a loading signal L OAD of the dynamic phase adjustment selected channel phase selection signal and a current phase selection signal PHASENOW < m:0> of the dynamic phase adjustment selected channel, the decoding and synchronizing module receives a new phase selection signal PHASENEW < m:0> when the dynamic phase adjustment is carried out from the output end of the counter, the decoding and synchronizing module also receives an input clock signal C L KIN < N:0>, a dynamic phase adjustment trigger signal STEP _ N, a dynamic phase adjustment channel selection signal SE L < m:0> and each channel clock phase initial setting value PHASEINIT0/1/…/x < m:0>, the clock selector receives an enable control signal C5631 KEN0/1/…/x < N:0> of each channel clock selector from the output end of the decoding and synchronizing module, and the clock selector also receives a clock signal C5630K < N > 360;
the driving method comprises the steps that the decoding and synchronizing module loads and stores phase initial values through initial setting values PHASEINIT0/1/…/x < m:0> of clock phases of all channels, decodes the phase initial values into corresponding enable control signals, then carries out synchronizing processing on the enable control signals, and transmits the enable control signals C L KEN0/1/…/x < n:0> after the synchronizing processing to corresponding clock selector units, and the clock selector units select input clock signals of corresponding phases from the input clock signals C L KIN < n:0> according to the phase initial values to serve as outputs.
7. The driving method according to claim 6, further comprising a dynamic phase adjustment step, the dynamic phase adjustment step including:
receiving a new phase selection signal PHASENEW < m:0> output by the counter during dynamic phase adjustment and decoding the new phase selection signal PHASENEW < m:0> into a selected channel enable signal (EN0/1/2 …/x < n:0>), wherein only 1 path of the n +1 paths of enable signals is high level, and the rest n paths of enable signals are low level, then carrying out synchronization processing on the enable signal (EN0/1/2 …/x < n:0>), outputting an enable control signal C L KEN0/1.. x < n:0>, wherein the synchronization processing is triggered by the falling edge of the input clock C L KIN < n:0>, and the enable control signal C L KEN0/1.. x < n:0> is respectively sent to a corresponding clock selection unit to be used as synchronous input control.
8. The driving method according to claim 6, wherein if the phase adjustment does not change the output channel, the dynamic phase adjustment step further comprises:
the counter obtains the DIRECTION of dynamic phase adjustment through a dynamic phase adjustment DIRECTION DIRECTION, wherein a dynamic phase adjustment channel selection signal SE L < m:0> is kept unchanged, then a loading signal L OAD of the dynamic phase adjustment selected channel phase selection signal is triggered to keep low level, then a current channel phase selection value PHASENOW < m:0> is loaded to the counter, then a STEP _ N signal is triggered, the counter realizes 1 addition or 1 subtraction at the rising edge of STEP _ N according to the dynamic phase adjustment DIRECTION, the counter outputs a new phase selection value PHASENEW < m:0> and sends the new phase selection value PHASENEW < m:0> to the decoding and synchronizing module, decoding is completed in the decoding and synchronizing module and is synchronized to a clock domain of an input clock, a new enabling control signal is output, the enabling control signal is transmitted to a corresponding clock selector unit, and the clock selector unit is switched to a new phase clock according to the enabling control signal.
9. The driving method according to claim 6, wherein if the phase adjustment does not change the output channel, the phase adjustment step further comprises:
when the counter selects a dynamic phase adjustment DIRECTION according to a dynamic phase adjustment DIRECTION directive, a channel with adjusted phase is selected according to a dynamic phase adjustment channel selection signal SE L < m:0>, the current phase selection signal PHASENOW < m:0> of the channel selected by the counter through dynamic phase adjustment is transmitted to the counter, then L OAD signals are triggered and kept at a high level for a period of time, the current channel phase selection value PHASENOW < m:0> is loaded to the counter, then STEP _ N signals are triggered, the counter is added with 1 or subtracted with 1 when STEP _ N rises according to the adjustment DIRECTION, the counter outputs a new phase selection value PHASENEW < m:0> and transmits the new phase selection value PHASENEW < m:0> to a decoding and synchronization module, decoding is completed in the module and the new phase selection value is synchronized to a clock domain of an input clock C L KIN, a new enabling control signal is output, the enabling control signal is transmitted to the corresponding clock selector unit, and the clock selector unit is switched to a new phase clock.
10. An electronic device characterized in that it comprises a clock signal generation circuit according to any one of claims 1 to 5.
11. A computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions which, when executed by a processor, implement the driving method according to any one of claims 6 to 9.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010190170.6A CN111399588B (en) | 2020-03-18 | 2020-03-18 | Clock signal generation circuit, driving method and electronic device |
| JP2022549567A JP2023515026A (en) | 2020-03-18 | 2020-07-21 | CLOCK SIGNAL GENERATING CIRCUIT, DRIVING METHOD AND ELECTRONIC DEVICE |
| PCT/CN2020/103276 WO2021184623A1 (en) | 2020-03-18 | 2020-07-21 | Clock signal generation circuit, driving method, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010190170.6A CN111399588B (en) | 2020-03-18 | 2020-03-18 | Clock signal generation circuit, driving method and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111399588A true CN111399588A (en) | 2020-07-10 |
| CN111399588B CN111399588B (en) | 2021-09-21 |
Family
ID=71434348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010190170.6A Active CN111399588B (en) | 2020-03-18 | 2020-03-18 | Clock signal generation circuit, driving method and electronic device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2023515026A (en) |
| CN (1) | CN111399588B (en) |
| WO (1) | WO2021184623A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112580278A (en) * | 2020-12-07 | 2021-03-30 | 海光信息技术股份有限公司 | Optimization method and optimization device for logic circuit and storage medium |
| CN112671379A (en) * | 2021-03-17 | 2021-04-16 | 北京紫光青藤微系统有限公司 | Clock phase selection circuit |
| WO2021184623A1 (en) * | 2020-03-18 | 2021-09-23 | 深圳市紫光同创电子有限公司 | Clock signal generation circuit, driving method, and electronic device |
| CN114578895A (en) * | 2020-12-02 | 2022-06-03 | 京东方科技集团股份有限公司 | Integrated circuit and clock signal distribution method thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI823224B (en) * | 2021-12-30 | 2023-11-21 | 新唐科技股份有限公司 | Control circuit and control method |
| CN115441860B (en) * | 2022-11-07 | 2023-02-17 | 西安水木芯邦半导体设计有限公司 | Multichannel output controller and PCB defect detection system |
| CN117519425B (en) * | 2024-01-03 | 2024-05-10 | 芯耀辉科技有限公司 | Clock signal generation method, computer equipment and medium |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5498990A (en) * | 1991-11-05 | 1996-03-12 | Monolithic System Technology, Inc. | Reduced CMOS-swing clamping circuit for bus lines |
| CN101021739A (en) * | 2007-03-28 | 2007-08-22 | 威盛电子股份有限公司 | Resetting system and resetting method |
| CN101299159A (en) * | 2008-07-01 | 2008-11-05 | 深圳市远望谷信息技术股份有限公司 | Clock switch circuit |
| CN101373629A (en) * | 2007-08-14 | 2009-02-25 | 三星电子株式会社 | Clock signal generator, semiconductor memory device including the same, and methods of operating the same |
| CN101419483A (en) * | 2008-11-27 | 2009-04-29 | 华亚微电子有限公司 | Clock generator based on phase-locked loop and clock generating method |
| CN101689062A (en) * | 2007-05-11 | 2010-03-31 | 莱斯特大学 | Tick source |
| CN101938348A (en) * | 2010-07-30 | 2011-01-05 | 重庆金美通信有限责任公司 | Clock regeneration method taking standard clock/data as reference |
| US20150070054A1 (en) * | 2013-09-09 | 2015-03-12 | Megachips Corporation | Synchronization system and frequency divider circuit |
| CN108241405A (en) * | 2016-12-26 | 2018-07-03 | 比亚迪股份有限公司 | The generation method of on piece clock circuit and on piece clock signal |
| CN109672444A (en) * | 2018-12-19 | 2019-04-23 | 南京国博电子有限公司 | A kind of ultrahigh speed digital analog converter that multichannel clock interweaves |
| CN110376872A (en) * | 2019-05-29 | 2019-10-25 | 西安电子科技大学 | A kind of time-to-digit converter applied to TADC based on asynchronous reset |
| CN110502066A (en) * | 2019-08-15 | 2019-11-26 | Oppo广东移动通信有限公司 | Clock switching device, method and electronic equipment |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3636657B2 (en) * | 2000-12-21 | 2005-04-06 | Ｎｅｃエレクトロニクス株式会社 | Clock and data recovery circuit and clock control method thereof |
| JP5359521B2 (en) * | 2009-04-24 | 2013-12-04 | ソニー株式会社 | Binary value conversion circuit and method, AD conversion apparatus, solid-state imaging device, and camera system |
| CN109753481B (en) * | 2019-01-15 | 2020-11-24 | 上海安路信息科技有限公司 | Dynamic phase switching system and dynamic phase switching method |
| CN110011659B (en) * | 2019-04-15 | 2021-01-15 | 上海安路信息科技有限公司 | Frequency divider and chip thereof |
| CN111399588B (en) * | 2020-03-18 | 2021-09-21 | 深圳市紫光同创电子有限公司 | Clock signal generation circuit, driving method and electronic device |
-
2020
- 2020-03-18 CN CN202010190170.6A patent/CN111399588B/en active Active
- 2020-07-21 WO PCT/CN2020/103276 patent/WO2021184623A1/en active Application Filing
- 2020-07-21 JP JP2022549567A patent/JP2023515026A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5498990A (en) * | 1991-11-05 | 1996-03-12 | Monolithic System Technology, Inc. | Reduced CMOS-swing clamping circuit for bus lines |
| CN101021739A (en) * | 2007-03-28 | 2007-08-22 | 威盛电子股份有限公司 | Resetting system and resetting method |
| CN101689062A (en) * | 2007-05-11 | 2010-03-31 | 莱斯特大学 | Tick source |
| CN101373629A (en) * | 2007-08-14 | 2009-02-25 | 三星电子株式会社 | Clock signal generator, semiconductor memory device including the same, and methods of operating the same |
| CN101299159A (en) * | 2008-07-01 | 2008-11-05 | 深圳市远望谷信息技术股份有限公司 | Clock switch circuit |
| CN101419483A (en) * | 2008-11-27 | 2009-04-29 | 华亚微电子有限公司 | Clock generator based on phase-locked loop and clock generating method |
| CN101938348A (en) * | 2010-07-30 | 2011-01-05 | 重庆金美通信有限责任公司 | Clock regeneration method taking standard clock/data as reference |
| US20150070054A1 (en) * | 2013-09-09 | 2015-03-12 | Megachips Corporation | Synchronization system and frequency divider circuit |
| CN108241405A (en) * | 2016-12-26 | 2018-07-03 | 比亚迪股份有限公司 | The generation method of on piece clock circuit and on piece clock signal |
| CN109672444A (en) * | 2018-12-19 | 2019-04-23 | 南京国博电子有限公司 | A kind of ultrahigh speed digital analog converter that multichannel clock interweaves |
| CN110376872A (en) * | 2019-05-29 | 2019-10-25 | 西安电子科技大学 | A kind of time-to-digit converter applied to TADC based on asynchronous reset |
| CN110502066A (en) * | 2019-08-15 | 2019-11-26 | Oppo广东移动通信有限公司 | Clock switching device, method and electronic equipment |
Non-Patent Citations (3)
| Title |
|---|
| JUN-CHEOL JEON: "Five-Input Majority Gate Based QCA Decoder", 《ADVANCED SCIENCE AND TECHNOLOGY LETTERS》 * |
| 张振: "FPGA内数字时钟管理模块的研究与设计", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
| 王鲁豫: "FPGA中数字时钟管理模块的设计", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021184623A1 (en) * | 2020-03-18 | 2021-09-23 | 深圳市紫光同创电子有限公司 | Clock signal generation circuit, driving method, and electronic device |
| CN114578895A (en) * | 2020-12-02 | 2022-06-03 | 京东方科技集团股份有限公司 | Integrated circuit and clock signal distribution method thereof |
| CN112580278A (en) * | 2020-12-07 | 2021-03-30 | 海光信息技术股份有限公司 | Optimization method and optimization device for logic circuit and storage medium |
| CN112671379A (en) * | 2021-03-17 | 2021-04-16 | 北京紫光青藤微系统有限公司 | Clock phase selection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2023515026A (en) | 2023-04-12 |
| CN111399588B (en) | 2021-09-21 |
| WO2021184623A1 (en) | 2021-09-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111399588B (en) | Clock signal generation circuit, driving method and electronic device | |
| US7777534B2 (en) | Fraction-N frequency divider and method thereof | |
| US8248138B2 (en) | Method and apparatus for preventing phase interpolation circuit from glitch during clock switching | |
| KR100533915B1 (en) | Clock signal selecting device and method for guaranting its clock continuity | |
| KR102654395B1 (en) | Glitch-free clock switching circuit | |
| JP2010158004A (en) | Delay circuit, and variable delay circuit | |
| US6646480B2 (en) | Glitchless clock output circuit and the method for the same | |
| CN111224649A (en) | Fixed time delay circuit of high-speed interface | |
| US6653867B1 (en) | Apparatus and method for providing a smooth transition between two clock signals | |
| US8339175B2 (en) | Phase generating apparatus and method thereof | |
| US7183831B2 (en) | Clock switching circuit | |
| US11616502B2 (en) | Phase interpolator and clock signal selector thereof | |
| CN110867199A (en) | Synchronous mirror delay circuit and synchronous mirror delay operation method | |
| CN114337661B (en) | Decimal frequency dividing and dynamic phase shifting system based on PLL circuit | |
| US8841939B2 (en) | Switching control circuit and switching device | |
| CN113504809B (en) | Dynamic switching method, device and system for multipath clocks | |
| JP3101315B2 (en) | Automatic time adjustment circuit | |
| KR20100082834A (en) | Clock circuit with clock transfer capability and method | |
| CN106982058B (en) | Frequency eliminator and control method thereof | |
| CN118041345A (en) | Arbitrary integer frequency divider with dynamically configurable frequency dividing coefficient | |
| JP3930641B2 (en) | Switching method and switching system for active and standby systems | |
| CN117411465A (en) | Clock switching circuit, chip and electronic equipment | |
| KR20000042405A (en) | Circuit for changing main system clock in synchronous system | |
| JPH0738398A (en) | Clock switching circuit | |
| JP2734401B2 (en) | Data multiplexing circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |