CN118041345A - Arbitrary integer frequency divider with dynamically configurable frequency dividing coefficient - Google Patents

Abstract

The application relates to a frequency divider with dynamically configurable frequency dividing coefficient, which controls a counter to count the pulses of an input clock signal by taking the value of the target frequency dividing coefficient as a counting period when the target frequency dividing coefficient is not 1, and further generates a first frequency dividing clock signal according to the counting quantity.

Description

Arbitrary integer frequency divider with dynamically configurable frequency dividing coefficient

Technical Field

The application relates to the technical field of frequency dividers, in particular to an arbitrary integer frequency divider with dynamically-configurable frequency dividing coefficient.

Background

The frequency divider of any integer is commonly used for frequency division of clock signals in the field of digital circuits, the ratio of the clock frequency of an input clock to the clock frequency domain of an output clock is called a frequency division coefficient, and the frequency divider can be applied to scenes with different frequency requirements according to the characteristic that the frequency divider of any integer is supported.

The conventional integer frequency divider is configured by performing frequency division coefficient before the system starts to work, when the frequency divider is in the working process, dynamic adjustment of the frequency division coefficient is not supported, if the frequency division coefficient is forcefully changed in the working process of the frequency divider, burrs are generated in the clock switching process of the output clock, and the stability of a circuit system driven by the output clock is greatly affected.

Disclosure of Invention

The application provides an arbitrary integer frequency divider with dynamically configurable frequency division coefficients, wherein the change of the frequency division coefficients does not cause the output clock to generate burrs.

An arbitrary integer divider with dynamically configurable division coefficients, comprising:

A counter;

The frequency division coefficient control circuit is connected with the counter and used for receiving the frequency division coefficient signal and obtaining the frequency division coefficient represented by the frequency division coefficient signal to obtain a target frequency division coefficient; if the target frequency division coefficient is not 1, controlling the counter to count the pulses of the input clock signal by taking the value of the target frequency division coefficient as a counting period to obtain the counting number;

The frequency division clock generation circuit is connected with the counter and is used for generating a first frequency division clock signal with uniform pulse distribution in each counting period according to the counting quantity;

The output selection circuit is respectively connected with the frequency division coefficient control circuit and the frequency division clock generation circuit and is used for receiving the input clock signal and selecting at most one of the input clock signal and the first frequency division clock signal to output according to the target frequency division coefficient;

The frequency division coefficient control circuit is further configured to obtain the count number if the frequency division coefficient changes, and update the target frequency division coefficient when the count number reaches the count period, so that the output selection circuit outputs the input clock signal or the first frequency division clock signal with a complete period in the count period where the change time of the frequency division coefficient is located.

In one embodiment, the frequency division coefficient control circuit is further configured to count a first transition edge of the input clock signal to obtain the count number;

The frequency division clock generation circuit is also used for generating an initial signal, and turning over the level of the initial signal at the current moment when the count number reaches 1 and the count number exceeds a count threshold value to obtain the first frequency division clock signal; wherein the count threshold is equal to one-half of the value of the target division factor.

In one embodiment, the frequency divider further comprises:

The duty ratio trimming circuit is respectively connected with the frequency division coefficient control circuit, the frequency division clock generation circuit and the output selection circuit and is used for acquiring the first frequency division clock signal, and if the target frequency division coefficient is an odd number which is not 1, the duty ratio trimming circuit is used for performing duty ratio trimming on the acquired first frequency division clock signal to acquire a second frequency division clock signal; wherein the duty cycle of the second divided clock signal is 50%;

the output selection circuit is also connected with the duty cycle trimming circuit and is used for outputting the input clock signal if the target frequency division coefficient is 1; outputting the second frequency division clock signal if the target frequency division coefficient is an odd number of non-1; and outputting the first frequency division clock signal if the target frequency division coefficient is even.

In one embodiment, the duty cycle trimming circuit comprises:

The clock sampling circuit is respectively connected with the frequency division coefficient control circuit and the frequency division clock generation circuit and is used for acquiring the first frequency division clock signal, and if the target frequency division coefficient is an odd number which is not 1, the clock sampling circuit takes the time corresponding to the second jump edge of the input clock signal as the sampling time to sample the first frequency division clock signal to obtain a trimming signal;

And the logic operation circuit is respectively connected with the clock sampling circuit, the frequency division clock generation circuit and the output selection circuit and is used for performing OR operation on the trimming signal and the first frequency division clock signal to obtain the second frequency division clock signal.

In one embodiment, the output selection circuit includes:

the selection control circuit is connected with the frequency division coefficient control circuit and is used for outputting a first gating signal and a second gating signal according to the target frequency division coefficient;

The control end of the first selector is connected with the selection control circuit and is used for receiving the first gating signal;

The control end of the second selector is connected with the selection control circuit, the control end of the second selector is used for receiving the second gating signal, and the output end of the second selector is connected with the first input end of the first selector;

the first input end of the second selector is used for receiving a first target signal, the second input end of the second selector is used for receiving a second target signal, and the second input end of the first selector is used for receiving a third target signal; the first, second and third target signals are any one of the first, second and input clock signals, respectively, and the first, second and third target signals are different from each other.

In one embodiment, the selection control circuit takes the time at which the second transition edge of the input clock signal is located as the time at which the first strobe signal and the second strobe signal are output.

In one embodiment, a first input of the second selector is configured to receive the first divided clock signal, and a second input of the second selector is configured to receive the second divided clock signal; the second input terminal of the first selector is used for receiving the input clock signal.

In one embodiment, the selection control circuit includes:

The comparison module is used for comparing the target frequency division coefficient with 1;

The control end of the third selector is connected with the comparison module, the first input end of the third selector is used for receiving a first level signal, the second input end of the third selector is used for receiving a second level signal, and the third selector is used for outputting a target level signal according to the comparison result of the comparison module; the target level signal is the first level signal or the second level signal;

the data input end of the first D trigger is connected with the output end of the third selector, the output end of the first D trigger is connected with the control end of the second selector, the clock end of the first D trigger is used for receiving the input clock signal, and the first D trigger is used for outputting the target level signal at the moment of the second jump edge of the input clock signal to serve as the first gating signal.

In one embodiment, the selection control circuit further comprises:

The data input end of the second D trigger is used for receiving a coefficient last bit signal, the output end of the second D trigger is connected with the control end of the first selector, the clock end of the second D trigger is used for receiving the input clock signal, and the second D trigger is used for outputting the coefficient last bit signal at the moment of a second jump edge of the input clock signal to be used as the second gating signal; wherein the coefficient last bit signal is used to characterize the value of the zeroth bit number when the target division coefficient is represented as a binary number.

In one embodiment, the clock sampling circuit includes:

the sampling module is connected with the frequency division clock generation circuit;

The turnover module is connected with the sampling module and is used for turnover the level of the input clock signal to obtain a turnover clock signal;

And the judging and processing module is respectively connected with the frequency division coefficient control circuit and the sampling module and is used for controlling the sampling module to sample the first frequency division clock signal by taking the moment corresponding to the first jump edge of the turnover clock signal as the sampling moment if the target frequency division coefficient is an odd number of non-1 so as to obtain the trimming signal.

In one embodiment, the frequency divider further comprises:

and the cross-clock domain processing circuit is connected with the frequency division coefficient control circuit and is used for synchronizing the frequency division coefficient signal to the clock domain where the input clock signal is.

The frequency divider acquires the frequency division coefficient as a target frequency division coefficient through the frequency division coefficient control circuit, then controls the counter to count the pulses of the input clock signal by taking the value of the target frequency division coefficient as a counting period when the target frequency division coefficient is not 1, and further the frequency division clock generation circuit generates a first frequency division clock signal according to the counting quantity.

Drawings

FIG. 1 is a block diagram of an arbitrary integer divider with dynamically configurable division coefficients according to an embodiment of the present application;

FIG. 2 is a timing diagram of an output clock signal during dynamic switching of coefficients of a conventional frequency divider;

FIG. 3 is a timing diagram of the output clock signal during dynamic switching of the divider coefficients according to an embodiment of the present application;

FIG. 4 is a timing diagram of the output clock signal during dynamic switching of divider coefficients according to another embodiment of the present application;

FIG. 5 is a block diagram of an arbitrary integer divider with dynamically configurable division coefficients according to another embodiment of the present application;

FIG. 6 is a block diagram of a frequency divider with dynamically configurable division coefficients according to another embodiment of the present application;

FIG. 7 is a block diagram of an output selection circuit according to an embodiment of the present application;

FIG. 8 is a waveform diagram of the output signal when the first strobe signal and the second strobe signal arrive at the same time;

FIG. 9 is a waveform diagram of the output signal when the first strobe signal and the second strobe signal do not arrive at the same time;

FIG. 10 is a graph showing output waveforms of the divided clock signals when the first strobe signal and the second strobe signal arrive at the low level time of the input clock signal;

FIG. 11 is a timing diagram of the output clock signal during dynamic switching of the divider coefficients according to the present application;

FIG. 12 is a circuit diagram of an output select circuit according to another embodiment of the present application;

FIG. 13 is a block diagram of a clock sampling circuit according to an embodiment of the present application;

Fig. 14 is a block diagram of an arbitrary integer divider with dynamically configurable division coefficients according to another embodiment of the present application.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without any inventive effort, are intended to be within the scope of the application.

It should be noted that, in the embodiments of the present application, all directional indicators (such as up, down, left, right, front, and rear … …) are merely used to explain the relative positional relationship, movement conditions, and the like between the components in a specific posture (as shown in the drawings), if the specific posture is changed, the directional indicators correspondingly change, and the connection may be a direct connection or an indirect connection.

Furthermore, descriptions such as those referred to as "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the indicated technical features in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present application.

The application provides an arbitrary integer frequency divider with dynamically configurable frequency division coefficient, as shown in fig. 1, the frequency divider comprises a counter 120, a frequency division coefficient control circuit 110, a frequency division clock generation circuit 130 and an output selection circuit 140; the frequency division coefficient control circuit 110 is connected with the counter 120 and is used for receiving the frequency division coefficient signal, obtaining the frequency division coefficient represented by the frequency division coefficient signal and obtaining a target frequency division coefficient; if the target frequency division coefficient is not 1, the counter 120 is controlled to count the pulses of the input clock signal with the value of the target frequency division coefficient as a counting period to obtain a counting number; the frequency-dividing clock generating circuit 130 is connected to the counter 120, and is configured to generate a first frequency-dividing clock signal with uniform pulse distribution in each counting period according to the count number; the output selection circuit 140 is connected to the frequency division coefficient control circuit 110 and the frequency division clock generation circuit 130, and is configured to receive the input clock signal, and select at most one of the input clock signal and the first frequency division clock signal according to the target frequency division coefficient for outputting; the frequency division coefficient control circuit 110 is further configured to obtain the count number if the frequency division coefficient changes, and update the target frequency division coefficient when the count number reaches the count period, so that the output selection circuit 140 has a complete period in the count period where the frequency division coefficient change time is located.

It can be understood that the waveform of the input clock signal is a continuous pulse, and the division factor is input to the division factor control circuit 110 in the form of a division factor signal for indicating division of the input clock signal by a specific multiple; when the frequency divider starts to operate, after receiving the frequency division coefficient signal, the frequency division coefficient control circuit 110 obtains the frequency division coefficient represented by the frequency division coefficient signal, and then, transmits the obtained frequency division coefficient as a target frequency division coefficient to the output selection circuit 140 for output selection on one hand, and determines to generate the first frequency division clock signal on the other hand.

Specifically, the frequency division coefficient control circuit 110 determines whether the target frequency division coefficient is 1, and when it is determined that the target frequency division coefficient is not 1, that is, when the input clock signal is instructed to perform frequency division other than one frequency division, in order to obtain the first frequency division signal with the frequency division coefficient being the target frequency division coefficient, the frequency division coefficient control circuit 110 may use the value of the target frequency division coefficient as a counting period, control the counter 120 to count the pulses of the input clock signal to obtain the count number, and then generate the first frequency division clock signal according to the count number. It will be appreciated that, for the n-divided clock signal of the input clock signal, the n pulses of the input clock signal correspond to 1 pulse of the n-divided clock signal, so that to obtain the first divided clock signal of the input clock signal, the pulses of the input clock signal may be counted with the target division coefficient as a count period, so as to generate one pulse in each count period, and the specific divided clock generation circuit 130 may generate the pulses when the count number is a specific value, so that the first divided clock signal has only one pulse distributed in each count period, and the pulses are uniformly distributed in each count period.

Further, the output selection circuit 140 may receive the input clock signal and the first divided clock signal, respectively, and after receiving the target division factor, output at most one of the input clock signal and the first divided clock signal according to the target division factor. Specifically, the output selection circuit 140 may not output the input clock signal and the first divided clock signal; or the output selection circuit 140 may output only the input clock signal, for example, when the target division coefficient is 1; or the output selection circuit 140 may output only the first divided clock signal, for example, when the target division coefficient is not 1.

The frequency division coefficient represented by the frequency division coefficient signal may be dynamically changed, and when the frequency division coefficient is changed, the frequency division coefficient control circuit 110 may first obtain the count number of the counter 120, and update the target frequency division coefficient when the count number reaches the count period.

Specifically, if the target frequency division coefficient is changed from 1 to a value greater than 1, the output selection circuit 140 directly outputs the input clock signal before the change, so that the count number and the count period of the counter 120 are both default to 0, at this time, it can be considered that the frequency division coefficient control circuit 110 can directly update the target frequency division coefficient, after the frequency division coefficient is changed, the counter 120 counts according to the new target frequency division coefficient, and since 1 is the minimum frequency division coefficient, and generates the first frequency division clock signal according to the count number of the pulses, the first pulse of the first frequency division clock signal must not be generated in the current count period, so that two pulses in the current count period do not occur, that is, the integrity of the input clock signal period output by the output selection circuit 140 before the frequency division coefficient is changed is not affected.

If the target division coefficient is reduced from a value greater than 1 to 1, if the output selection circuit 140 immediately switches to directly output the input clock signal, the clock of the first division clock signal may be incomplete in the counting period in which the change time is located. For example, as shown in fig. 2, when the division coefficient changes from 4 to 1 at the change time T0, if the output clock signal is immediately switched to the direct output input clock signal, a new pulse appears in the output clock signal of the output selection circuit 140 in the counting period T0, resulting in incomplete four-divided clock period in the counting period T0, and finally, an ideal four-divided clock signal cannot be obtained; if the target division coefficient is updated when the count number reaches the count period, referring to time T1 in fig. 3, no clock loss occurs in the count period T1. Therefore, by updating the target frequency division coefficient when the count number reaches the count period, the output selection circuit 140 can output the input clock signal after the output of the first frequency division clock signal is completed in the current count period, so as to realize the complete period of the first frequency division clock signal.

If the target division coefficient is reduced from a value greater than 1 to a value other than 1, the divided clock generation circuit 130 generates a first divided clock signal according to the new count period, and then outputs the first divided clock signal by the output selection circuit 140. If the target frequency division coefficient is directly used as the counting period when the target frequency division coefficient is reduced, the counter 120 may start counting the new period when the complete counting of the previous period is not completed, and finally the period of the first frequency division clock signal in the counting period where the change moment is located is incomplete; for example, as shown in fig. 4, when the frequency division coefficient is changed from 4 to 7, if the target frequency division coefficient is updated when the count number reaches the count period, that is, when the time T4 in the figure is updated, no clock loss occurs in the count period T2.

Therefore, by updating the target division coefficient when the count number reaches the count period, the counter 120 can start counting the new period after completing the complete count of the previous period, and finally, the period complete of the first division clock signal is realized.

In summary, by acquiring the count number when the frequency division coefficient changes, and updating the target frequency division coefficient when the count number reaches the count period, it is possible to achieve that the periods of the input clock signal and the first frequency division clock signal output by the output selection circuit 140 are complete in the count period where the change time of the frequency division coefficient is located.

The frequency divider acquires the frequency division coefficient as the target frequency division coefficient through the frequency division coefficient control circuit 110, then controls the counter 120 to count the pulses of the input clock signal by taking the value of the target frequency division coefficient as the counting period when the target frequency division coefficient is not 1, and further the frequency division clock generation circuit 130 generates the first frequency division clock signal according to the counting number, because the input clock signal and the first frequency division clock signal are selectively output by the output selection circuit 140 according to the target frequency division coefficient, and the period of the first frequency division clock signal is also determined by the target frequency division coefficient, when the frequency division coefficient changes, the time when the output selection circuit 140 outputs the input clock signal and the starting time of the period of the first frequency division clock signal can be changed when the counting number reaches the counting period, and finally the output clock signal or the first frequency division clock signal has a complete period within the counting period when the change time of the frequency division coefficient is changed, thereby avoiding the output clock signal from generating burrs in the clock switching process and ensuring the stability of a circuit system driven by the output clock signal.

In one embodiment, the frequency division coefficient control circuit 110 is further configured to count the first transition edges of the input clock signal to obtain a count number; the frequency-dividing clock generating circuit 130 is further configured to generate an initial signal, and when the count number reaches 1 and the count number exceeds the count threshold, flip the level of the initial signal at the current time to obtain a first frequency-dividing clock signal; wherein the count threshold is equal to one-half of the value of the target division factor.

It will be appreciated that counting pulses of the input clock signal may be accomplished by counting transitions of the input clock signal. At the time of starting, the initial signal generated by the divided clock generating circuit 130 may be constant at a low level, and then the divided clock generating circuit 130 inverts the level of the initial signal according to the count number such that the count number of the first transition edges is 1 and the level during exceeding the count threshold is a high level.

For example, taking the first jump edge as the rising edge, if the initial count value of the counter 120 is 0 and the count is up, the maximum count value of the counter 120 in one counting period is the frequency division coefficient minus 1. Referring to fig. 3, the initial signal may be a low level signal, the first frequency division coefficient is 4, the counting period of the counter 120 is also 4, the counting threshold is equal to 2, the counter 120 starts to count up from 0, the maximum count value is 3, and when the number of counts is 1, i.e. the count value is 0 (for example, at time t 2), the initial signal is turned from low level to high level; when the count number exceeds the count threshold 2, namely the count number is 3, and the count value is 2 (for example, at the time t 3), the initial signal is turned from the high level to the low level again; when the counter 120 counts to 3, it again starts counting from 0, and the divided clock generating circuit 130 continues to flip the count value, so as to finally obtain the first divided clock signal. In one embodiment, the divided clock generation circuit 130 may be further configured to receive an input clock signal, and start up and output an initial signal under the driving of the input clock signal.

The control process is simple by generating the initial signal and then performing level inversion according to the count number to obtain the frequency division signal, and the obtained frequency division signal is stable.

In one embodiment, referring to fig. 5, the frequency divider further includes a duty cycle trimming circuit 150, which is respectively connected to the frequency division coefficient control circuit 110, the frequency division clock generating circuit 130, and the output selecting circuit 140, and is configured to obtain a first frequency division clock signal, and if the target frequency division coefficient is an odd number other than 1, perform duty cycle trimming on the obtained first frequency division clock signal to obtain a second frequency division clock signal; wherein the duty cycle of the second divided clock signal is 50%; the output selection circuit 140 is further connected to the duty cycle trimming circuit 150, and is configured to output the input clock signal if the target frequency division coefficient is 1; outputting a second frequency division clock signal if the target frequency division coefficient is an odd number of non-1; if the target frequency division coefficient is even, the first frequency division clock signal is output.

It can be understood that when the target division coefficient is even, the duty ratio of the first divided clock signal obtained by the level inversion method is 50%, for example, the divided clock signal when the target division coefficient is 4 in fig. 3 and 4; when the target division coefficient is odd, the duty ratio of the first division clock signal obtained according to the level inversion manner is not 50%, for example, the division clock signal when the target division coefficient is 7 in fig. 4, so in order to expand the application scenario, the divider can be applied to a digital circuit having strict requirements on the duty ratio, and the duty ratio trimming circuit 150 needs to perform duty ratio trimming on the first division clock signal obtained when the target division coefficient is odd than 1, so as to obtain the second division clock signal, so that the duty ratio of the second division clock signal becomes 50%, for example, the five division clock signal obtained when the target division coefficient is 5 in fig. 3.

Further, when the output selection circuit 140 performs signal selection output according to the target frequency division coefficient, if the target frequency division coefficient is 1, the input clock signal is directly output; if the number is even, the first divided clock signal is output, and if the number is odd, the second divided clock signal is output, so that the duty ratio of the signals output by the output selection circuit 140 is ensured to be 50%.

In one embodiment, referring to fig. 6, the duty cycle trimming circuit 150 includes a clock sampling circuit 151 and a logic operation circuit 152, where the clock sampling circuit 151 is connected to the frequency division coefficient control circuit 110 and the frequency division clock generating circuit 130, respectively, and is configured to obtain a first frequency division clock signal, and if the target frequency division coefficient is an odd number other than 1, sample the first frequency division clock signal with a time corresponding to a second transition edge of the input clock signal as a sampling time, so as to obtain a trimming signal; the logic operation circuit 152 is connected to the clock sampling circuit 151, the divided clock generating circuit 130, and the output selecting circuit 140, and is configured to perform an or operation on the trimming signal and the first divided clock signal, to obtain a second divided clock signal.

Where s1 represents the first divided clock signal and s2 represents the second divided clock signal. After obtaining the target frequency division coefficient, the frequency division coefficient control circuit 110 sends the target frequency division coefficient to the clock sampling circuit 151 to perform parity determination; the second transition edge of the input clock signal may be a falling edge, and if it is determined that the second transition edge is an odd number other than 1, the first divided clock signal is sampled at a time corresponding to the falling edge of the input clock signal, for example, when the target frequency division coefficient is 7, the sampled trimming signal may be as shown in fig. 4.

Further, with continued reference to fig. 4, the logic operation circuit 152 performs an or operation on the trimming signal and the first divided clock signal, so that the duty ratio of the second divided clock signal obtained after the operation reaches 50%, and the rising edge of the pulse of the second divided clock signal is the same as that of the first divided clock, so that the clock missing condition does not occur in the counting period where the variation moment of the division coefficient is located.

In one embodiment, the clock sampling circuit 151 may receive the input clock signal to sample the first divided clock signal according to a second transition edge of the input clock signal.

In one embodiment, referring to fig. 7, the output selection circuit 140 includes a selection control circuit 1400, a first selector MUX1, and a second selector MUX2; the selection control circuit 1400 is connected to the frequency division coefficient control circuit 110, and is configured to output a first strobe signal and a second strobe signal according to a target frequency division coefficient; the control end of the first selector MUX1 is connected with the selection control circuit 1400, and the control end of the first selector MUX1 is used for receiving the first strobe signal; a control end of the second selector MUX2 is connected with the selection control circuit 1400, the control end of the second selector MUX2 is used for receiving a second gating signal, and an output end of the second selector MUX2 is connected with a first input end of the first selector MUX 1; a first input terminal of the second selector MUX2 is used for receiving the first target signal, a second input terminal of the second selector MUX2 is used for receiving the second target signal, and a second input terminal of the first selector MUX1 is used for receiving the third target signal; the first target signal, the second target signal and the third target signal are any one of a first frequency division clock signal, a second frequency division clock signal and an input clock signal respectively, and the first target signal, the second target signal and the third target signal are different from each other.

It will be appreciated that the first selector MUX1 and the second selector MUX2 may be 2-to-1 data selectors, respectively, and that the first selector MUX1 and the second selector MUX2 may be cascaded to form a 3-to-1 data selector. The first input end and the second input end of the second selector MUX2, and the second input end of the first selector MUX1 are used as 3 input ends, and can respectively receive one of the first frequency division clock signal, the second frequency division clock signal and the input clock signal in a one-to-one correspondence manner, then respectively control the selection output of the first selector MUX1 and the second selector MUX2 through the first gating signal and the second gating signal, and finally output one of the first frequency division clock signal, the second frequency division clock signal and the input clock signal.

In one embodiment, the selection control circuit 1400 takes the time at which the second transition edge of the input clock signal is located as the time at which the first strobe signal and the second strobe signal are output.

It will be appreciated that, to ensure accurate output of signals in cooperation with the first selector MUX1 and the second selector MUX2, the first strobe signal and the second strobe signal should arrive at the corresponding selectors at the same time, respectively, however, due to the effects of device delay and routing delay, there may be a certain deviation in the actual arrival times of the two strobe signals output by the selection control circuit 1400, which may cause the output signals to have glitches. For example, referring to fig. 8, in theory, the transitions of the first strobe signal sel1 and the second strobe signal sel2 should be at the same time, so that accurate switching between signals can be ensured, and an accurate output signal is finally obtained; if there is a time difference between transitions of the first strobe signal sel1 and the second strobe signal sel2, as shown in fig. 9, the transition may not be switched to a theoretical low level signal during a time period Δt where the time difference exists, and a glitch phenomenon may occur.

In this regard, the timing at which the selection control circuit 1400 outputs the first strobe signal and the second strobe signal may be designed to take the timing at which the second transition edge of the input clock signal is located as the output timing. Wherein the second transition edge of the input clock signal may be a falling edge.

In actual circuit operation, the time difference between the first strobe signal sel1 and the second strobe signal sel2 will be smaller than half clock period of the input clock signal, and the rising edges of the first divided clock signal and the second divided clock signal are after the first clock period of the input clock signal after the target division coefficient is acquired, so that the first strobe signal and the second strobe signal (refer to the first strobe signal and the second strobe signal in fig. 3) are output on the falling edge of the first clock period, the switching time can be limited within the falling edge of the clock period and the rising edge of the next clock period, for example, within the period t in fig. 10, during which the first divided clock signal, the second divided clock signal and the input clock signal are in a low level state, and therefore the clock output will be a low level anyway, thereby avoiding the glitch phenomenon and ensuring the reliability of the output clock signal. For example, referring to fig. 11, the selection control circuit 1400 outputs the first strobe signal and the second strobe signal at the falling edge timings td1 and td2 of the input clock signal, and the timings at which the first strobe signal and the second strobe signal reach the selector still correspond to the falling edge timings of the input clock signal under the influence of the delay, so that no glitch is generated.

In one embodiment, a first input of the second selector MUX2 is configured to receive a first divided clock signal, and a second input of the second selector MUX2 is configured to receive a second divided clock signal; a second input of the first selector MUX1 is arranged to receive an input clock signal.

It will be appreciated that the second selector MUX2 selects one of the first divided clock signal and the second divided clock signal to be output under the driving of the second strobe signal sel2, and the first selector MUX1 selects one of the output and input clock signals of the second selector MUX2 under the driving of the first strobe signal sel 1.

In one embodiment, referring to fig. 12, the selection control circuit 1400 includes a comparison module, a third selector MUX3, and a first D flip-flop; the comparison module is used for comparing a target frequency division coefficient (shown as div_factor_syn in the figure) with 1; the control end of the third selector MUX3 is connected with the comparison module, the first input end of the third selector MUX3 is used for receiving the first level signal, the second input end of the third selector MUX3 is used for receiving the second level signal, and the third selector MUX3 is used for outputting the target level signal according to the comparison result of the comparison module; the target level signal sel1_r is the first level signal or the second level signal; the data input end of the first D trigger is connected with the output end of the third selector MUX3, the output end of the first D trigger is connected with the control end of the second selector MUX2, the clock end of the first D trigger is used for receiving an input clock signal, and the first D trigger is used for outputting a target level signal at the moment of a second jump edge of the input clock signal to serve as a first gating signal.

Wherein, the first level signal may be a low level (denoted by 0 in the figure), and the second level signal may be a high level (denoted by 1 in the figure); when the comparison result is that the target frequency division coefficient is equal to 1, outputting a second level signal, wherein the second level signal starts to be output at the falling edge moment of the input clock signal under the time sequence control of the first D trigger and finally is transmitted to the first selector MUX1, and the first selector MUX1 outputs the input clock signal according to the second level signal; on the contrary, when the comparison result is that the target frequency division coefficient is not equal to 1, a first level signal is output, and under the timing control of the first D flip-flop, the first level signal starts to be output at the time of the falling edge of the input clock signal (denoted by clk_rev in the figure) and finally is transmitted to the first selector MUX1, and the first selector MUX1 outputs the signal output by the second selector MUX2, namely the first frequency division clock signal or the second frequency division clock signal, according to the first level signal.

In one embodiment, the selection control circuit 1400 further includes a second D flip-flop, a data input terminal of the second D flip-flop is configured to receive a coefficient last bit signal (div_factor_syn [0] in the figure), an output terminal of the second D flip-flop is connected to the control terminal of the first selector MUX1, a clock terminal of the second D flip-flop is configured to receive the input clock signal, and the second D flip-flop is configured to output the coefficient last bit signal at a time when a second transition edge of the input clock signal is located, as a second strobe signal; wherein the coefficient last bit signal is used to characterize the value of the zeroth bit number when the target division coefficient is represented as a binary number.

It will be appreciated that to determine the parity of the target division coefficient, a coefficient last signal representing the value of the zeroth bit of the target division coefficient may be obtained, and if the value of the signal is high, it indicates that the target division coefficient is odd, and if the signal is low, it indicates that the signal is even, and under the timing control of the second D flip-flop, the coefficient last signal starts to be output at the time of the falling edge of the input clock signal (denoted as clk_rev in the figure), and finally is transmitted to the second selector MUX2, so that the second selector MUX2 outputs the first division clock signal clk_rise or the second division clock signal clk_dd according to the value of the coefficient last signal.

In one embodiment, referring to FIG. 13, the clock sampling circuit 151 includes a sampling module 1511, a flipping module 1512, and a decision processing module 1513; the sampling module 1511 is connected to the divided clock generation circuit 130; the turnover module 1512 is connected with the sampling module 1511, and is configured to turn a level of an input clock signal to obtain a turnover clock signal; the judging and processing module 1513 is respectively connected to the frequency division coefficient control circuit 110 and the sampling module 1511, and is configured to control the sampling module 1511 to sample the first frequency division clock signal with a time corresponding to the first transition edge of the flip clock signal as a sampling time if the target frequency division coefficient is an odd number of non-1, so as to obtain the trimming signal.

Wherein the first transition edge of the inverted clock signal may be a rising edge. It can be understood that the sampling time of the trimming signal is the time when the falling edge of the input clock signal is located, and the sampling module generally samples the rising edge, so that the input clock signal can be turned by adopting the turning module, so that the falling edge of the input clock signal corresponds to the rising edge of the turning clock signal, and further, the time corresponding to the rising edge of the turning clock signal is directly used as the sampling time to sample the first frequency division clock signal, so that the trimming signal can be obtained. The jump edge conversion is carried out through the turnover signal, so that the sampling driving is realized, and the method is simple and efficient.

In one embodiment, as shown in fig. 14, the frequency divider further includes a cross-clock domain processing circuit connected to the frequency division coefficient control circuit 110 for synchronizing the frequency division coefficient signal to a clock domain in which the input clock signal is located.

It can be appreciated that the cross-clock domain processing circuit is responsible for performing clock domain synchronization operation on the input asynchronous signal to synchronize it to the clock domain of the input clock, thereby preventing metastable states.

In addition, the frequency division coefficient control circuit can be enabled to control by an external enabling signal, and the frequency division coefficient control circuit is in a working state when the external enabling signal is in a high level; the external enabling signal is transmitted to the frequency division coefficient control circuit after clock domain synchronization through the clock domain crossing processing circuit.

In one embodiment, the frequency divider may receive an external reset signal to reset the states of the modules.

The application also provides an arbitrary integer frequency divider with dynamically configurable frequency division coefficient, which comprises a counter, a frequency division coefficient control circuit, a frequency division clock generation circuit, an output selection circuit, a duty cycle trimming circuit and a cross-clock domain processing circuit, wherein the duty cycle trimming circuit comprises a clock sampling circuit and a logic operation circuit, and the output selection circuit comprises a selection control circuit, a first selector and a second selector; the selection control circuit comprises a comparison module, a third selector, a first D trigger and a second D trigger; the clock sampling circuit comprises a sampling module, a turnover module and a judging and processing module, wherein the connection relation of the modules can be described by referring to the embodiment.

Specifically, the cross-clock domain processing circuit synchronizes the frequency division coefficient signal to a clock domain where the input clock signal is located, the frequency division coefficient control circuit receives the synchronized frequency division coefficient signal, obtains a frequency division coefficient represented by the frequency division coefficient signal, obtains a target frequency division coefficient, and if the target frequency division coefficient is not 1, controls the counter to count the first jump edge of the input clock signal by taking the value of the target frequency division coefficient as a counting period, so as to obtain the counting number.

The frequency division clock generation circuit is also used for generating an initial signal, and turning over the level of the initial signal at the current moment when the count number reaches 1 and the count number exceeds a count threshold value to obtain a first frequency division clock signal; wherein the count threshold is equal to one-half of the value of the target division factor.

The sampling module acquires a first frequency division clock signal; the turnover module turns the level of the input clock signal to obtain a turnover clock signal; the judging and processing module is used for controlling the sampling module to sample the first frequency division clock signal by taking the moment corresponding to the first jump edge of the turnover clock signal as the sampling moment if the target frequency division coefficient is an odd number of non-1, so as to obtain a trimming signal; the logic operation circuit also obtains a first frequency division clock signal, and then performs OR operation on the trimming signal and the first frequency division clock signal to obtain a second frequency division clock signal.

The output selection circuit is used for outputting an input clock signal if the target frequency division coefficient is 1; outputting a second frequency division clock signal if the target frequency division coefficient is an odd number of non-1; if the target frequency division coefficient is even, the first frequency division clock signal is output. The frequency division coefficient control circuit is further used for acquiring the counting number if the frequency division coefficient changes, and updating the target frequency division coefficient when the counting number reaches the counting period, so that the output selection circuit outputs the input clock signal or the first frequency division clock signal with a complete period in the counting period where the change moment of the frequency division coefficient is located.

The output selection circuit comprises a selection control circuit, a first selector and a second selector, wherein the selection control circuit comprises a comparison module, a third selector, a first D trigger and a second D trigger: the comparison module is used for comparing the target frequency division coefficient with 1; the first input end of the third selector is used for receiving the first level signal, the second input end of the third selector is used for receiving the second level signal, and the third selector is used for outputting a target level signal according to the comparison result of the comparison module; the target level signal is a first level signal or a second level signal; the clock end of the first D trigger is used for receiving an input clock signal and outputting a target level signal at the moment of a second jump edge of the input clock signal to serve as a first gating signal.

The data input end of the second D trigger is used for receiving the coefficient last bit signal, the clock end of the second D trigger is used for receiving the input clock signal, and the second D trigger is used for outputting the coefficient last bit signal at the moment of the second jump edge of the input clock signal to be used as a second gating signal; wherein the coefficient last bit signal is used to characterize the value of the zeroth bit number when the target division coefficient is represented as a binary number.

The control end of the first selector is used for receiving a first gating signal; the control end of the second selector is used for receiving a second gating signal, and the output end of the second selector is connected with the first input end of the first selector; the first input end of the second selector is used for receiving the first frequency division clock signal, and the second input end of the second selector is used for receiving the second frequency division clock signal; the second input of the first selector is for receiving an input clock signal.

The frequency divider with the structure can support asynchronous input of the frequency division coefficient and the clock signal, can output the frequency division clock with the duty ratio of 50% by adjusting the effective time of the frequency division coefficient, has no burr phenomenon caused by incomplete clock, and avoids the burr phenomenon caused by device delay and routing delay by selecting the switching time.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the application.

Claims (11)

1. An arbitrary integer divider with dynamically configurable division coefficients, comprising:

A counter;

The frequency division coefficient control circuit is connected with the counter and used for receiving the frequency division coefficient signal and obtaining the frequency division coefficient represented by the frequency division coefficient signal to obtain a target frequency division coefficient; if the target frequency division coefficient is not 1, controlling the counter to count the pulses of the input clock signal by taking the value of the target frequency division coefficient as a counting period to obtain the counting number;

The frequency division clock generation circuit is connected with the counter and is used for generating a first frequency division clock signal with uniform pulse distribution in each counting period according to the counting quantity;

The output selection circuit is respectively connected with the frequency division coefficient control circuit and the frequency division clock generation circuit and is used for receiving the input clock signal and selecting at most one of the input clock signal and the first frequency division clock signal to output according to the target frequency division coefficient;

The frequency division coefficient control circuit is further configured to obtain the count number if the frequency division coefficient changes, and update the target frequency division coefficient when the count number reaches the count period, so that the output selection circuit outputs the input clock signal or the first frequency division clock signal with a complete period in the count period where the change time of the frequency division coefficient is located.

2. The dynamically configurable divide-by-factor arbitrary integer divider of claim 1, wherein the divide-by-factor control circuit is further configured to count first transitions of the input clock signal to obtain the count number;

The frequency division clock generation circuit is also used for generating an initial signal, and turning over the level of the initial signal at the current moment when the count number reaches 1 and the count number exceeds a count threshold value to obtain the first frequency division clock signal; wherein the count threshold is equal to one-half of the value of the target division factor.

3. The frequency divider of claim 2, wherein the frequency divider further comprises:

The duty ratio trimming circuit is respectively connected with the frequency division coefficient control circuit, the frequency division clock generation circuit and the output selection circuit and is used for acquiring the first frequency division clock signal, and if the target frequency division coefficient is an odd number which is not 1, the duty ratio trimming circuit is used for performing duty ratio trimming on the acquired first frequency division clock signal to acquire a second frequency division clock signal; wherein the duty cycle of the second divided clock signal is 50%;

the output selection circuit is also connected with the duty cycle trimming circuit and is used for outputting the input clock signal if the target frequency division coefficient is 1; outputting the second frequency division clock signal if the target frequency division coefficient is an odd number of non-1; and outputting the first frequency division clock signal if the target frequency division coefficient is even.

4. The dynamically configurable divide-by-factor arbitrary integer divider of claim 3, wherein the duty cycle trimming circuit comprises:

The clock sampling circuit is respectively connected with the frequency division coefficient control circuit and the frequency division clock generation circuit and is used for acquiring the first frequency division clock signal, and if the target frequency division coefficient is an odd number which is not 1, the clock sampling circuit takes the time corresponding to the second jump edge of the input clock signal as the sampling time to sample the first frequency division clock signal to obtain a trimming signal;

And the logic operation circuit is respectively connected with the clock sampling circuit, the frequency division clock generation circuit and the output selection circuit and is used for performing OR operation on the trimming signal and the first frequency division clock signal to obtain the second frequency division clock signal.

5. The dynamically configurable divide-by-factor arbitrary integer divider of claim 3, wherein the output selection circuit comprises:

the selection control circuit is connected with the frequency division coefficient control circuit and is used for outputting a first gating signal and a second gating signal according to the target frequency division coefficient;

The control end of the first selector is connected with the selection control circuit and is used for receiving the first gating signal;

The control end of the second selector is connected with the selection control circuit, the control end of the second selector is used for receiving the second gating signal, and the output end of the second selector is connected with the first input end of the first selector;

the first input end of the second selector is used for receiving a first target signal, the second input end of the second selector is used for receiving a second target signal, and the second input end of the first selector is used for receiving a third target signal; the first, second and third target signals are any one of the first, second and input clock signals, respectively, and the first, second and third target signals are different from each other.

6. The dynamically configurable divide-by-factor arbitrary integer divider of claim 5, wherein the selection control circuit takes a time at which a second transition edge of the input clock signal is present as a time at which the first strobe signal and the second strobe signal are output.

7. The dynamically configurable divide-by-factor arbitrary integer divider of claim 6, wherein a first input of the second selector is configured to receive the first divided clock signal and a second input of the second selector is configured to receive the second divided clock signal; the second input terminal of the first selector is used for receiving the input clock signal.

8. The dynamically configurable divide-by-factor arbitrary integer divider of claim 7, wherein the selection control circuit comprises:

The comparison module is used for comparing the target frequency division coefficient with 1;

The control end of the third selector is connected with the comparison module, the first input end of the third selector is used for receiving a first level signal, the second input end of the third selector is used for receiving a second level signal, and the third selector is used for outputting a target level signal according to the comparison result of the comparison module; the target level signal is the first level signal or the second level signal;

the data input end of the first D trigger is connected with the output end of the third selector, the output end of the first D trigger is connected with the control end of the second selector, the clock end of the first D trigger is used for receiving the input clock signal, and the first D trigger is used for outputting the target level signal at the moment of the second jump edge of the input clock signal to serve as the first gating signal.

9. The dynamically configurable divide-by-factor arbitrary integer divider of claim 7, wherein the selection control circuit further comprises:

The data input end of the second D trigger is used for receiving a coefficient last bit signal, the output end of the second D trigger is connected with the control end of the first selector, the clock end of the second D trigger is used for receiving the input clock signal, and the second D trigger is used for outputting the coefficient last bit signal at the moment of a second jump edge of the input clock signal to be used as the second gating signal; wherein the coefficient last bit signal is used to characterize the value of the zeroth bit number when the target division coefficient is represented as a binary number.

10. The dynamically configurable divide-by-factor arbitrary integer divider of claim 4, wherein the clock sampling circuit comprises:

the sampling module is connected with the frequency division clock generation circuit;

The turnover module is connected with the sampling module and is used for turnover the level of the input clock signal to obtain a turnover clock signal;

And the judging and processing module is respectively connected with the frequency division coefficient control circuit and the sampling module and is used for controlling the sampling module to sample the first frequency division clock signal by taking the moment corresponding to the first jump edge of the turnover clock signal as the sampling moment if the target frequency division coefficient is an odd number of non-1 so as to obtain the trimming signal.

11. The dynamically configurable divide-by-factor arbitrary integer divider of claim 4, wherein the divider further comprises:

and the cross-clock domain processing circuit is connected with the frequency division coefficient control circuit and is used for synchronizing the frequency division coefficient signal to the clock domain where the input clock signal is.