CN101021739A - Resetting system and resetting method - Google Patents
Resetting system and resetting method Download PDFInfo
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- CN101021739A CN101021739A CN 200710079471 CN200710079471A CN101021739A CN 101021739 A CN101021739 A CN 101021739A CN 200710079471 CN200710079471 CN 200710079471 CN 200710079471 A CN200710079471 A CN 200710079471A CN 101021739 A CN101021739 A CN 101021739A
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Abstract
The invention provides a reset system and method, specially relating to a reset operation of integrated circuit chips, which includes: a delay module, receiving a reset source signal and a reference clock signal to generate a system reset signal and a synchronization signal, a clock control signal generation module, receiving the synchronization signal changing from effect state to fail and making the clock control signal effect, and a latch module, deciding whether to output system clock signal based on the received reference clock signal and clock control signal.
Description
Technical field
The present invention relates to a kind of method for designing of integrated circuit, particularly a kind of resetting system and repositioning method that is applied in the integrated circuit (IC) design.
Background technology
Along with the development of integrated circuit (IC) design technology, it is big that the design scale of single-chip circuit becomes, and design complexities also increases thereupon.In integrated circuit (IC) design, be in the large scale integrated circuit design of representative particularly at present, adopt the synchronous sequence method for designing to come the logic output of each module of control chip usually with SOC chip (system on chip, SOC (system on a chip)).Described synchronous sequence design is meant the chip internal at integrated circuit, and all triggers all work in identical clock signal, and the upset of all flip-flop states also all occurs in synchronization.
But, in real process, because clock signal arrives the difference in path that each trigger experiences, thereby make that the time-delay of clock signal is inequality on each trigger, thereby it is inequality to cause clock signal to arrive time of each trigger, and then the upset that can't guarantee all flip-flop states is all at synchronization.Therefore, cause the logic state confusion of system probably, cause this integrated circuit (IC) design can't reach the requirement of expection thus.As shown in Figure 1; identical for guaranteeing that clock signal arrives time of each trigger; prior art can compensate to the transmission path of each trigger FF1～FFn clock signal clock_in by the method for inserting clock trees usually, so that clock signal clock_in can reach all triggers at synchronization.
Similarly, as shown in Figure 1, adopt the method that is similar to the insertion clock trees to guarantee that reset source signal rst_in arrives each trigger in the design chips 1, i.e. trigger FF1～FFn synchronously in the prior art usually.Each trigger is provided with a reset terminal RST, in order to receive reset source signal rst_in, carries out reset operation to impel trigger FF1～FFn respectively according to reset source signal rst_in.In general, by the circuit access path of reset source signal rst_in to the reset terminal RST of trigger FF1～FFn, i.e. P1, P2...Pn is also inequality.For convenience of description, suppose that reset source signal rst_in is the shortest to the path P 1 of trigger FF1, reset source signal rst_in is the longest to the path P n of trigger FFn.For making trigger FF1～FFn can carry out reset operation synchronously, prior art is inserted two time-delay impact damper Buf in path P 1, in path P 2, insert a time-delay impact damper Buf simultaneously, so that arrive trigger FF1 and FF2 after the delay of the schedule time of reset source signal rst_in process, and impel trigger FF1～FFn to carry out reset operation synchronously.
Yet, owing to must insert the time-delay impact damper of some to the length of the circuit access path of trigger according to the reset source signal in the above-mentioned resetting system, thus the complexity and the area of chip of design of integrated circuit increased.Especially for the large scale integrated chip design, if, will increase the design difficulty and the cost of integrated circuit (IC) chip greatly still by increasing the reset source signal Synchronization that the time-delay impact damper makes reception.
Summary of the invention
The object of the present invention is to provide a kind of integrated circuit resetting system and integrated circuit repositioning method, it can be applied to large scale integrated circuit, and has lower cost.
The invention provides a kind of resetting system that is used to finish the reset operation of integrated circuit (IC) chip, it comprises: a Postponement module receives a reset source signal and a reference clock signal, to produce a systematic reset signal and a synchronous signal; Clock system signal generator module for the moment, receive described systematic reset signal and synchronizing signal and reference clock signal, to produce a clock control signal, described clock control signal generation module makes described clock control signal effective after the synchronizing signal that receives becomes failure state by effective status; And a latch units, whether determine the output system clock signal according to reference clock signal that receives and clock control signal.
The invention provides a kind of repositioning method that is used to finish the reset operation of integrated circuit (IC) chip, it comprises: according to the reset source signal produce one with the synchronous synchronizing signal of reference clock signal; Synchronizing signal is carried out delay operation, to obtain a systematic reset signal; Produce a clock control signal according to described synchronizing signal and systematic reset signal, whether export a clock signal of system with decision; And export this systematic reset signal, to carry out reset operation, wherein after described synchronizing signal becomes failure state by effective status, make described clock control signal effective, so that the clock signal of system of output is a disarmed state.
The output that the present invention sends to the clock signal of system of integrated circuit (IC) chip by control realizes the synchronization operation of asynchronous reset, thereby need in the circuit access path, not add delay buffer, and then can reduce the complexity of circuit design, reduce area of chip simultaneously.
Description of drawings
Fig. 1 is the structural representation of the resetting system of prior art.
Fig. 2 is the structural representation according to the resetting system of one embodiment of the invention.
Fig. 3 is the control signal sequential chart of resetting system shown in Figure 2.
Fig. 4 is the structural representation according to the resetting system of another embodiment of the present invention.
Embodiment
By the description of carrying out below in conjunction with the accompanying drawing that an example exemplarily is shown, above and other objects of the present invention and characteristics will become apparent.
The present invention finishes the synchronization operation of the asynchronous reset of integrated circuit by the output of control system clock signal.Specify resetting system of the present invention below with reference to accompanying drawing.
See also Fig. 2, produce a systematic reset signal 111 and a clock signal of system 311 to design chips 500, so that the trigger FF1～FFn in the design chips 500 carries out reset operation according to the resetting system 100 of one embodiment of the invention according to reset source signal rst_in that receives and reference clock signal clock_in.
The resetting system 100 of present embodiment comprises a Postponement module 1, clock system signal generator module 2, an and latch units 3 for the moment.Postponement module 1 reaches delay operation according to the reference clock signal clock_in that receives synchronously to reset source signal rst_in, and exports a synchronous signal 101 and a systematic reset signal 111.Trigger FF1～FFn in the design chips 500 carries out reset operation according to systematic reset signal 111.Clock control signal generation module 2 receives synchronizing signal 101 and systematic reset signal 111, to export a clock control signal 221.Latch units 3 receive clock control signals 221 and reference clock signal clock_in, and whether determine output system clock signal 311 according to clock control signal 221.
Clock control signal generation module 2 comprises an XOR gate 20, a phase inverter 21 and a trigger 22.The synchronizing signal 101 of 20 pairs of receptions of XOR gate and systematic reset signal 111 carry out xor operation, to export a signal 201.21 pairs of signals of phase inverter 201 carry out operated in anti-phase to produce a pre-latch signal 210.Trigger 22 receives pre-latch signal 210 and reference clock signal clock_in, to obtain the clock control signal 221 synchronous with reference clock signal clock_in.
To those skilled in the art, above embodiment only is a realization preferred embodiments of the present invention.Those skilled in the art can be by above explanation, and disclosing scope based on the present invention can have different embodiments.For example, clock control signal generation module 2 also can utilize with door or other logic module to be formed, and reach clock control signal generation module 2 after the synchronizing signal 101 that receives becomes failure state by effective status, make described clock control signal 221 effective results.Similarly, whether latch units 3 determines output system clock signal 311 according to reference clock signal clock_in that receives and clock control signal 221, also can be formed and is produced identical effect by the Different Logic assembly.
For clearly disclosing the present invention, describing resetting system of the present invention below with reference to the oscillogram of above-mentioned each control signal is the how output by the control system clock signal synchronous reset operation that realizes design chips.
See also Fig. 3, suppose that reset source signal rst_in low level is effective, and reset source signal rst_in becomes effective status in the T3 cycle of reference clock signal clock_in by disarmed state, promptly need design chips 500 is carried out reset operation.Synchronization module 10 carries out synchronous operation according to reference clock signal clock_in to reset source signal rst_in immediately, and to produce the synchronizing signal 101 that differs a clock period with reset source signal rst_in, promptly synchronizing signal 101 is effective at clock period T3～T5.Subsequently, trigger D3, the D4 of delay unit 11, D5 carry out delay operation to synchronizing signal 101 successively, thereby the systematic reset signal 111 that makes delay unit 11 outputs postpones 3 clock period end with respect to synchronizing signal 101, and promptly systematic reset signal 111 is effective at clock period T3～T8.At this moment, the trigger FF1～FFn in the design chips 500 can carry out reset operation according to the systematic reset signal 111 that receives.20 pairs of synchronizing signals 101 of XOR gate and systematic reset signal 111 carry out xor operation, and phase inverter 21 obtains pre-latch signal 210 with the signal 201 of XOR gate 20 output after anti-phase.Obviously, when synchronizing signal 101 and systematic reset signal 111 were effective status, pre-latch signal 210 was a high level; When synchronizing signal 101 becomes disarmed state by effective status, and systematic reset signal 111 is when still being in effective status, and pre-latch signal 210 becomes effective status; When synchronizing signal 101 and systematic reset signal 111 were disarmed state, pre-latch signal 210 became disarmed state by effective status, that is to say that pre-latch signal is an effective status at clock period T6～T8.Because clock control signal 221 is done to obtain after the synchronous processing through 22 pairs of pre-latch signals 210 of trigger, so clock control signal 221 becomes effective status/disarmed state with respect to pre-210 clock period of delay of latch signal, promptly clock control signal 221 is effective at clock period T7～T9.Because latch 30 is according to reference clock signal clock_in clock control signal 221 to be carried out negative edge effectively to latch, and clock door 31 is the output that comes control system clock signal 311 according to the signal 301 of latch 30 outputs, thereby clock signal of system 311 is disarmed state between the negative edge of the negative edge of clock period T7 and clock period T10, promptly remains low level state.
As seen from the above description, after the systematic reset signal that receives is effective, trigger FF1～FFn in the design chips 500 begins to carry out reset operation, and the state that trigger FF1～FFn carries out behind the reset operation will remain unchanged, up to receiving efficient system clock signal 311.In general, clock signal of system 311 had some delays before the trigger FF1～FFn that arrives design chips 500, and same systematic reset signal 111 also has some delays.Before systematic reset signal 111 becomes disarmed state and afterwards all clock signal of system 311 being controlled to be disarmed state in the native system is in order to guarantee that each the trigger FF1～FFn in the design chips 500 does not have clock along occurring at this moment, to guarantee foundation and the retention time between them when systematic reset signal 111 is invalid from effectively becoming.Like this, before synchronous clock signal of system 311 sends to design chips 500, trigger FF1～FFn has just passed through and has resetted, so the trigger of design chips 500 can carry out normal logical operation behind the clock signal of system 311 of receiving normal output respectively.On the other hand, as shown in Figure 3, in a period of time after reset source signal rst_in becomes effective status, clock signal of system 311 still can normally be exported, thereby resetting system of the present invention can be realized the reset operation of design chips 500 by some specific software.For example, can come the initialization system reset signal to remain valid time of state by software.
Figure 4 shows that structural representation according to the resetting system of another embodiment of the present invention.Need to prove that components identical all indicates with identical label among Fig. 4 and Fig. 2.
As is known to the person skilled in the art, the resetting system of one embodiment of the invention shown in Figure 2 can come the time of Adjustment System reset signal continuous and effective by the quantity that changes delay unit 11 internal triggers.Resetting system shown in Figure 4 then is the effective time that changes clock signal of system by the frequency of adjusting reference clock signal.As shown in Figure 4, reference clock signal clock_in exports Postponement module 1 and clock control signal generation module 2 to after handling by the frequency division of clock division unit 6, thereby reaches the effect that increases the clock period.For instance, the reference clock signal clock_in of the 6 pairs of receptions in clock division unit carries out obtaining a clock signal 60 after the processing of 1/2 frequency division, and promptly two reference clock signal clock_in cycles equal the cycle of a clock signal 60.Like this, lock unit 10 carries out exporting synchronizing signal 101 after the synchronous operation according to 60 pairs of reset source signals of clock signal rst_in, and the synchronizing signal 101 of this moment has postponed two reference clock signal clock_in cycles with respect to reset source signal rst_in.Obviously, systematic reset signal 111 by delay unit 11 outputs has postponed six reference clock signal clock_in cycles with respect to synchronizing signal 101, thereby the resetting system shown in Figure 2 with respect to the present invention, the 111 effective times of systematic reset signal in the present embodiment have increased by one times, and plenty of time carries out reset operation thereby make trigger FF1～FFn in the design chips 500 have more.
The disclosed resetting system of the present invention has following advantage:
1. avoid systematic reset signal to be delivered to the time delay of each trigger, after each trigger being finished reset, receive clock signal of system again, enter normal manipulation mode.This effect can effectively improve the fiduciary level of system.
2. can not need during system design the taking into account system reset signal to be delivered to the time delay of each trigger, simplify the restriction of wiring design.
3. but the reset request that support software produced.The reset request that software takes place must still be in just can finish under the normal running and reset at hardware.Resetting system of the present invention still continues the output system clock signal by Postponement module when receiving the reset source signal, subordinate's hardware still can be under the normal running, makes system's continuous firing and finish to reset.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Claims (14)
1. resetting system is used to finish the reset operation of integrated circuit (IC) chip, it is characterized in that, comprising:
One Postponement module receives a reset source signal and a reference clock signal, to produce a systematic reset signal and a synchronous signal;
Clock system signal generator module for the moment, receive described systematic reset signal, synchronizing signal and reference clock signal, to produce a clock control signal, described clock control signal generation module makes described clock control signal effective after the synchronizing signal that receives becomes failure state by effective status; And
Whether one latch units determines the output system clock signal according to reference clock signal that receives and clock control signal.
2. resetting system according to claim 1, it is characterized in that, when synchronizing signal that receives when described clock control signal generation module and systematic reset signal were effective status, the clock control signal of described clock control signal generation module output was a disarmed state.
3. resetting system according to claim 1, it is characterized in that, the synchronizing signal that receives when described clock control signal generation module is a disarmed state, and systematic reset signal is when being effective status, and the clock control signal of described clock control signal generation module output is an effective status.
4. resetting system according to claim 1, it is characterized in that, when synchronizing signal that receives when described clock control signal generation module and systematic reset signal were disarmed state, the clock control signal of described clock control signal generation module output was a disarmed state.
5. according to any described resetting system in the claim 1 to 4, it is characterized in that described clock control signal generation module comprises:
One XOR gate receives described synchronizing signal and systematic reset signal; And
One phase inverter, the signal that described XOR gate is exported carries out anti-phase processing back output one pre-latch signal.
6. resetting system according to claim 5 is characterized in that, described clock control signal generation module also comprises a trigger, receives described pre-latch signal and reference clock signal, to export described clock control signal.
7. resetting system according to claim 1 is characterized in that, described Postponement module comprises:
One synchronous unit carries out synchronous operation to described reset source signal and reference clock signal, and exports described synchronizing signal; And
One delay unit receives the synchronizing signal of described lock unit output, and exports described systematic reset signal after synchronizing signal is carried out delay operation.
8. resetting system according to claim 1 is characterized in that, described latch units comprises:
One latch, its control end receives described reference clock signal, and its input end receives described clock control signal; And
One clock door receives signal and reference clock signal that described latch is exported.
9. resetting system according to claim 8 is characterized in that, and is wherein described, and when the clock control signal of latch reception was effective status, the clock signal of system of described clock door output was a disarmed state.
10. resetting system according to claim 1 is characterized in that, also comprises a clock frequency unit, and the reference clock signal that receives is carried out exporting described Postponement module to after frequency division is handled.
11. a repositioning method is used to finish the reset operation of integrated circuit (IC) chip, it is characterized in that, comprising:
According to generation one of reset source signal and the synchronous synchronizing signal of reference clock signal;
Synchronizing signal is carried out delay operation, to obtain a systematic reset signal;
Produce a clock control signal according to described synchronizing signal and systematic reset signal, whether export a clock signal of system with decision; And
Export this systematic reset signal, to carry out reset operation, wherein:
After described synchronizing signal becomes failure state by effective status, make described clock control signal effective, so that the clock signal of system of output is a disarmed state.
12. repositioning method according to claim 11 is characterized in that, when described synchronizing signal and systematic reset signal are effective status, makes described clock control signal invalid, with the output system clock signal.
13. repositioning method according to claim 11 is characterized in that, when described synchronizing signal is a disarmed state, and systematic reset signal makes described clock control signal effective when being effective status.
14. repositioning method according to claim 11 is characterized in that, when described synchronizing signal and systematic reset signal are disarmed state, makes described clock control signal invalid, with the output system clock signal.
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| CNB2007100794716A CN100498649C (en) | 2007-03-28 | 2007-03-28 | Resetting system and resetting method |
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