CN115441860B - Multichannel output controller and PCB defect detection system - Google Patents

Multichannel output controller and PCB defect detection system Download PDF

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Publication number
CN115441860B
CN115441860B CN202211385022.5A CN202211385022A CN115441860B CN 115441860 B CN115441860 B CN 115441860B CN 202211385022 A CN202211385022 A CN 202211385022A CN 115441860 B CN115441860 B CN 115441860B
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output
channel
input
signal
gate
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CN115441860A (en
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来新泉
刘明明
周宏哲
李继生
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Xi'an Shuimuxinbang Semiconductor Design Co ltd
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Xi'an Shuimuxinbang Semiconductor Design Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention provides a multichannel output controller and a PCB defect detection system, which comprises a line decoder, a channel module and a control module, wherein the line decoder is used for decoding a signal from a signal processing module; the line decoder comprises N inputs for receiving the external channel acknowledge signal and M outputs, wherein M =2 N (ii) a The channel module comprises M output channels, the input end of each output channel is correspondingly connected with one output end of the line decoder, and the input ends of all the output channels are also used for receiving external data signals; the input end of the control module is used for receiving an external channel confirmation signal, and the output end of the control module is connected with the input end of the output channel; the control module and the line decoder confirm a target channel in the channel module according to an external channel confirmation signal and send a control signal to the target channel so that the target channel collects an external data signal and outputs the signal to an external detection circuit. The invention not only improves the expansibility but also improves the controllability of the multi-channel output controller.

Description

Multichannel output controller and PCB defect detection system
Technical Field
The invention relates to the technical field of PCB (printed circuit board), in particular to a multi-channel output controller and a PCB defect detection system.
Background
The PCB defect detection system is mainly used for detecting the defects of short/open circuit, protrusion/depression, scratch, pin holes, residual copper, line width/line distance violation and the like in the PCB. At present, the PCB is mainly scanned through scanning technologies such as linear scanning or 3D scanning, and the like, so that whether the PCB has the defects or not is detected. When defect detection is carried out through a scanning technology, a multi-channel output controller is generally required to assist, an existing multi-channel output controller cannot control a specific channel, controllability is poor, accuracy in detection is reduced, and meanwhile, the number of channels of the existing multi-channel output controller cannot be expanded, expansibility is poor, and detection requirements of different PCB boards cannot be met.
Disclosure of Invention
The invention provides a multi-channel output controller and a PCB defect detection system, and aims to solve the problems of poor controllability and poor expansibility of a multi-channel controller in the conventional PCB defect detection system.
In a first aspect, the present invention provides a multi-channel output controller, including a line decoder, a channel module, and a control module; the line decoder comprises N inputs for receiving the external channel acknowledge signal and M outputs, wherein M =2 N (ii) a The channel module comprises M output channels, the input end of each output channel is correspondingly connected with one output end of the line decoder, and the input ends of all the output channels are also used for receiving external data signals; the input end of the control module is used for receiving the external channel confirmation signal, and the output end of the control module is connected with the input end of the output channel; the control module and the line decoder confirm a target channel in the channel module according to the external channel confirmation signal and send a control signal to the target channel so that the target channel collects the external data signal and outputs the signal to an external detection circuit.
Further, the output channel comprises a first two-input and gate, a second two-input and gate and a trigger; the first input end of the first two-input AND gate is connected with one output end of the line decoder, the second input end of the first two-input AND gate is connected with the output end of the control module, the output end of the first two-input AND gate is connected with the first input end of the second two-input AND gate, the second input end of the second two-input AND gate is used for receiving an external sampling signal, the output end of the second two-input AND gate is connected with the second input end of the trigger, and the first input end of the trigger is used for receiving the external data signal.
Furthermore, the output channel further comprises a selector, a first input end of the selector is connected with a first output end of the trigger, a second input end of the selector is connected with a second output end of the trigger, and a third input end of the selector is further used for receiving an external output selection control signal.
Further, the output channel further comprises an output drive, and the output drive is connected with the selector.
Further, the trigger circuit further comprises a reset module, and the reset module is connected with all the triggers.
Furthermore, the channel module further comprises a two-input not and gate, a first input end of the two-input not and gate is used for receiving an external reset signal, a second input end of the two-input not and gate is connected with an output end of the reset module and is used for receiving an internal reset signal output by the reset module, and output ends of the two-input not and gate are connected with reset ends of all the triggers.
The system further comprises a Schmitt trigger module, wherein the input end of the Schmitt trigger module is used for receiving the external channel confirmation signal and the external data signal, and the output end of the Schmitt trigger module is respectively connected with the line decoder, the control module and the input ends of all the output channels.
The testing module comprises a multi-input NAND gate, M two-input NAND gates and a switch tube;
the first input ends of the two input NAND gates are connected with one output end of the line decoder, the second input ends of the two input NAND gates are connected with the output end of the output channel, the output ends of the two input NAND gates are connected with one input end of the multiple input NAND gate, the output end of the multiple input NAND gate is connected with the grid electrode of the switch tube, the source electrode of the switch tube is grounded, and the drain electrode of the switch tube is connected with the external detection circuit.
Further, the line decoder includes 6 input terminals and 64 output terminals, and the channel module includes 64 output channels, and each output channel is correspondingly connected to an output terminal of one of the line decoders.
In a second aspect, the present invention further provides a PCB defect detecting system, which includes any one of the above multi-channel output controllers.
The multi-channel output controller and the PCB defect detection system disclosed by the invention can confirm the output channel needing to be gated through the line decoder and the control module, set the output channel as the target channel, acquire and store the external data signal after the target channel is gated, and output the signal to the detection circuit, so that the number of the output channels can be increased according to the actual situation, whether a certain output channel is gated or not can be accurately controlled, and the expansibility and the controllability are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a block diagram of a multi-channel output controller according to an embodiment of the present invention;
FIG. 2 is a block schematic diagram of a multi-channel output controller provided in accordance with yet another embodiment of the present invention;
FIG. 3 is a circuit diagram of an output channel of a multi-channel output controller according to an embodiment of the invention;
FIG. 4 is a circuit diagram of a multi-channel output controller according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a test module of the multi-channel output controller according to an embodiment of the invention;
FIG. 6 is a timing diagram of the main signals in the circuit diagram of the multi-channel output controller shown in FIG. 4.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
In addition, directional terms used in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", and the like, refer to the attached drawings and the directions of usage of the product. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. Further, in the drawings, structures that are similar or identical are denoted by the same reference numerals.
Referring to fig. 1 to 6, fig. 1 is a block diagram of a multi-channel output controller 100 according to an embodiment of the present invention; FIG. 2 is a block diagram of a multi-channel output controller 100 according to another embodiment of the present invention; FIG. 3 is a circuit diagram of the output channel 31 of the multi-channel output controller 100 according to one embodiment of the present invention; FIG. 4 is a circuit diagram of the multi-channel output controller 100 according to an embodiment of the present invention; FIG. 5 is a circuit diagram of the test module 40 of the multi-channel output controller 100 according to one embodiment of the present invention; fig. 6 is a timing diagram of main signals in the circuit diagram of the multi-channel output controller 100 shown in fig. 4.
As shown in fig. 1, the multi-channel output controller 100 includes a line decoder 10, a channel module 30, and a control module 20; the line decoder 10 comprises N inputs for receiving the external channel acknowledge signal and M outputs, where M =2 N (ii) a The channel module 30 includes M output channels 31, an input end of each output channel 31 is correspondingly connected to one output end of the line decoder 10, and input ends of all the output channels 31 are further used for receiving an external Data signal Data; the input end of the control module 20 is configured to receive the external channel confirmation signal, and the output end of the control module 20 is connected to the input end of the output channel 31; the control module 20 and the line decoder 10 determine a target channel in the channel module 30 according to the external channel determination signal, and send a control signal to the target channel so that the target channel collects the external Data signal Data and outputs the signal to an external detection circuit.
Wherein the line decoder 10 is used for decoding an input binary code and determining an output channel 31 to be gated, the line decoder 10 may include N input terminals and M output terminals, where M =2 N . For example, the line decoder 10 may include 4 inputs and 16 outputs. The channel module 30 may include M output channels 31, for example, 16 output channels 31, and each output channel 31 is connected to an output terminal of one line decoder 10 for receiving the control signal sent by the line decoder 10. The control module 20 may be stagedWhen a plurality of control chips are connected, each control chip can be connected with the same number of output channels 31 and is used for controlling the corresponding output channels 31, and after the number of the output channels 31 is increased, the number of the control chips can be synchronously increased, so that the output channels 31 can be conveniently expanded. After receiving the external channel confirmation signal, the control module 20 enables the corresponding control chip, and then sends a control signal to the corresponding output channel 31 according to the external channel confirmation signal, where the external channel confirmation signal may include an external channel address signal and a chip select signal, the line decoder and the control module confirm the target channel according to the external channel address signal, and the control module also enables the corresponding control chip according to the chip select signal, thereby controlling gating of the corresponding output channel 31. For example, if the output channel 31 connected to the second output terminal of the line decoder 10 needs to be gated, the channel is taken as a target channel, the line decoder 10 outputs a control signal to the target channel through the second output terminal, meanwhile, the control module 20 synchronously sends the control signal to the target channel, and the target channel is turned on after receiving the control signal sent by the line decoder 10 and the control signal sent by the control module 20 at the same time, where the control signal may be a level signal, and the output channel 31 may be set to be turned on when receiving a high level signal at the same time. After the target channel is conducted, the external Data signal Data is output to the rear-stage circuit through the target channel, and the rear-stage circuit can be a detection circuit and is used for detecting whether the PCB has defects or not. It should be noted that there may be a plurality of output channels 31 that are simultaneously gated at the same time, and the present invention is not limited thereto.
As a further embodiment, the output channel 31 includes a first two-input and gate 311, a second two-input and gate 312, and a flip-flop 313; the first input end of the first two-input and gate 311 is connected to one output end of the line decoder 10, the second input end of the first two-input and gate 311 is connected to the output end of the control module 20, the output end of the first two-input and gate 311 is connected to the first input end of the second two-input and gate 312, the second input end of the second two-input and gate 312 is configured to receive an external sampling signal Clk, the output end of the second two-input and gate 312 is connected to the second input end of the flip-flop 313, and the first input end of the flip-flop 313 is configured to receive the external Data signal Data.
As shown in fig. 3, a first input terminal of the first two-input and gate 311 is connected to one output terminal of the line decoder 10 for receiving a corresponding control signal, and a second input terminal thereof is connected to the control module 20 for receiving a control signal, for example, the first two-input and gate may be connected to an enable pin of a control chip in the control module 20. A first input of the second two-input and gate 312 is connected to the output of the first two-input and gate 311, a second input thereof is used for receiving the Clk signal, i.e. the timing signal, and an output thereof is connected to the flip-flop 313. The flip-flop 313 may be a D flip-flop for sampling and storing the external Data signal Data, and has a first input terminal D for receiving the external Data signal Data, a second input terminal Clk connected to an output terminal of the second two-input and gate 312, and an output terminal for outputting the external Data signal Data. When the first input terminal of the first two-input and gate 311 receives the control signal output by the line decoder 10 and the second input terminal receives the control signal output by the control module 20, the first two-input and gate 311 is turned on and outputs a signal to the first input terminal of the second two-input and gate 312, and if the second input terminal of the second two-input and gate 312 receives the external sampling signal Clk, the second two-input and gate 312 is turned on and outputs a signal to the flip-flop 313. The external Data signal Data may be transmitted all the time, but the acquisition of the external Data signal Data is started when the flip-flop 313 receives the signal output by the second two-input and gate 312 and the acquired external Data signal Data is output as an output signal.
As a further embodiment, the output channel 31 further includes a selector 314, a first input terminal of the selector 314 is connected to a first output terminal of the flip-flop 313, a second input terminal of the selector 314 is connected to a second output terminal of the flip-flop 313, and a third input terminal of the selector 314 is further configured to receive an external output selection control signal Pol.
As shown in fig. 3, the selector 314 may be an alternative multiplexer for selecting whether the output signal is a positive logic level output or a negative logic level output according to the output selection control signal Pol, so as to facilitate defect detection meeting different requirements.
As a further embodiment, the output channel 31 further comprises an output driver 315, and the output driver 315 is connected to the selector 314.
As shown in fig. 3, the output driver 315 is mainly used to improve the driving capability of the output signal.
As a further embodiment, a reset module 50 is further included, and the reset module 50 is connected to all the flip-flops 313.
As shown in fig. 3, the flip-flop 313 may further include a third input terminal nrst. The third input terminal nrst of the flip-flop 313 is connected to the reset module 50, and the flip-flop 313 can be reset by the reset module 50, so that the next defect detection is facilitated.
As a further embodiment, the channel module 30 further includes a two-input not and gate 32, a first input end of the two-input not and gate 32 is configured to receive an external reset signal Rst0, a second input end of the two-input not and gate 32 is connected to the output end of the reset module 50 and is configured to receive an internal reset signal Rst1 output by the reset module 50, and output ends of the two-input not and gate 32 are connected to all the flip-flops 313.
The reset module 50 may be connected to the third input end of the flip-flop 313 through a two-input not and gate 32, a first input end of the two-input not and gate 32 is configured to receive an external reset signal Rst0, a second input end of the two-input not and gate is connected to the reset module 50 and configured to receive an internal reset signal Rst1, when any reset signal is received, a signal is output to the flip-flop 313, the flip-flop 313 resets, the acquisition of the external Data signal Data is stopped, and the stored external Data is cleared. In addition, the reset module 50 may also be connected to the third input terminal of the flip-flop 313 through a nor gate.
As a further embodiment, a schmitt trigger module 60 is further included, an input end of the schmitt trigger module 60 is configured to receive the external channel confirmation signal and the external Data signal Data, and an output end of the schmitt trigger module 60 is connected to the input ends of the line decoder 10, the control module 20, and all the output channels 31, respectively.
The schmitt trigger module 60 may include a plurality of schmitt triggers 61 for suppressing noise in the input signal and preventing false triggering. The input signals include, but are not limited to, external Data signal Data, external reset signal Rst0, external channel confirmation signal, and external sampling signal Clk.
As a further embodiment, the testing device further includes a testing module 40, where the testing module 40 includes a multi-input nand gate 42, M two-input nand gates 41, and a switch tube TS; a first input end of the two-input nand gate 41 is connected to an output end of the line decoder 10, a second input end of the two-input nand gate 41 is connected to an output end of the output channel 31, an output end of the two-input nand gate 41 is connected to an input end of the multiple-input nand gate 42, an output end of the multiple-input nand gate 42 is connected to a gate of the switch tube TS, a source of the switch tube TS is grounded, and a drain of the switch tube TS is connected to the external detection circuit.
As shown in fig. 2 and fig. 5, the test module 40 is used to determine whether the logic of the output signal output by the channel module 30 is correct. The testing module 40 includes M two-input nand gates 41, that is, the number of the two-input nand gates 41 is the same as the number of the output channels 31, a first input of each two-input nand gate 41 is connected to one of the output channels 31 for receiving the output signal output by the output channel 31, a second input of each two-input nand gate 41 is further connected to the line decoder 10 for receiving the signal output by the line decoder 10, and when the two-input nand gates 41 receive the output signals of the line decoder 10 and the output channels 31 at the same time, the output signal is output to the multiple-input nand gates 42. The multi-input nand gate 42 is used for implementing nand relationship between a plurality of input signals, and the output signal is output to the switch tube TS through the multi-input nand gate 42, the switch tube may be an NMOS tube, and the drain of the NMOS tube outputs the output signal.
As a further embodiment, the line decoder 10 includes 6 input terminals and 64 output terminals, and the channel module 30 includes 64 output channels 31, and each of the output channels 31 is connected to an output terminal of one of the line decoders 10.
As shown in fig. 4, the line decoder 10 may be a 6-64 line decoder 10, which includes 6 input terminals and 64 output terminals, and correspondingly, the channel module 30 may include 64 output channels 31, and the schmitt trigger module 60 may include 11 schmitt triggers 61, where three schmitt triggers 61 are respectively used for receiving the external input signal DIN, the external sampling signal Clk and the external reset signal Rst0, and the remaining nine schmitt triggers 61 are used for receiving the external channel confirmation signal, and among the nine schmitt triggers 61, six are used for being connected to the line decoder 10, and two are used for being connected to the control module 20. An output end of the line decoder 10 is correspondingly connected with an output channel 31, so as to output corresponding signals to the output channel 31, as shown in fig. 4, the A1-A6 signals are external channel address signals, the A7-A8 signals are external channel address signals and chip select signals, the B1-B6 signals represent signals output after the A1-A6 signals are processed by the schmitt trigger 61, and the S1-S64 signals represent signals output by the line decoder 10 and correspond to different output channels 31. A second input terminal of the first two-input and gate 311 of the output channel 31 is connected to the control module 20. When the line decoder 10 outputs the S2 signal and the control module 20 simultaneously outputs the control signal, the second output channel 31 shown in fig. 4 is turned on, and when the flip-flop 313 receives the signal sent by the second two-input and gate 312, the flip-flop starts to collect and store the external Data signal Data, and finally outputs the output signal Dout 2.
As shown in fig. 6, fig. 6 is a timing diagram of the operation of the main signals in the circuit shown in fig. 4, hi is high, lo is low, the curves are connected to represent the associated signals, and a <6:1> is the input address of the decoder for determining the gated channel. As can be seen from fig. 6, when the DIN signal level rises, the Dout [ N ] signal is at a low level, and no signal is output, when the external sampling signal CLK is at a high level, which indicates that the flip-flop 313 of the nth output channel 31 starts to collect external data and output a signal, the Dout [ N ] signal level is high, that is, the nth output channel 31 changes with the change of the input signal when the rising edge of the external sampling signal CLK comes, and it should be noted that the output signals of the other un-gated output channels 31 maintain the waveform at the previous time, as shown by the Dout [ N +1] signal in fig. 6. When the Nth output channel 31 receives the external sampling signal Clk again, the flip-flop 313 stops sampling the external Data signal Data, and the level of Dout [ N ] is low. Meanwhile, after the nth output channel 31 starts sampling the external Data for a period of time, if the (N + 1) th output channel 31 also receives the external sampling signal Clk, the level of Dout [ N +1] is high, and the (N + 1) th output channel 31 starts collecting the external Data signal Data and starts outputting. As can be seen from FIG. 6, when the level of Dout [ N +1] is high, the level of Dout [ N ] signal remains unchanged and does not affect the output of the Nth output channel 31. When the level of the Rst signal is high, indicating that all flip-flops 313 are reset, stopping the data collection and clearing the stored data, as shown in fig. 6, the levels of the DIN signal and the Dout [ N +1] signal are both low. In addition, the TSn signal is output by the test module 40 to assist in determining the correctness of the output signal of the gated output channel 31.
The invention also discloses a PCB defect detection system which comprises the multichannel output controller 100.
The multi-channel output controller and the PCB defect detection system disclosed by the invention can confirm the output channel needing to be gated through the line decoder and the control module, set the output channel as the target channel, collect the external data signal and output the signal to the detection circuit after the target channel is gated, and meanwhile, the number of the output channels can be increased according to the actual situation, thereby improving the expansibility and the controllability.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (9)

1. A multi-channel output controller is applied to a PCB defect detection system and is characterized by comprising a line decoder, a channel module and a control module;
the line decoder comprises N inputs for receiving the outer channel acknowledge signal and M outputs, where M =2N;
the channel module comprises M output channels, the input end of each output channel is correspondingly connected with one output end of the line decoder, and the input ends of all the output channels are also used for receiving external data signals;
the input end of the control module is used for receiving the external channel confirmation signal, and the output end of the control module is connected with the input end of the output channel;
the control module and the line decoder confirm a target channel in the channel module according to the external channel confirmation signal and send a control signal to the target channel so that the target channel collects the external data signal and outputs the signal to an external detection circuit;
the output channel comprises a first two-input AND gate, a second two-input AND gate and a trigger;
the first input end of the first two-input AND gate is connected with one output end of the line decoder, the second input end of the first two-input AND gate is connected with the output end of the control module, the output end of the first two-input AND gate is connected with the first input end of the second two-input AND gate, the second input end of the second two-input AND gate is used for receiving an external sampling signal, the output end of the second two-input AND gate is connected with the second input end of the trigger, and the first input end of the trigger is used for receiving the external data signal.
2. The multi-channel output controller of claim 1, wherein the output channel further comprises a selector, a first input of the selector being connected to a first output of the flip-flop, a second input of the selector being connected to a second output of the flip-flop, a third input of the selector further being configured to receive an external output selection control signal.
3. The multi-channel output controller of claim 2, wherein the output channel further comprises an output driver, the output driver being coupled to the selector.
4. The multi-channel output controller of claim 1, further comprising a reset module, said reset module being connected to all of said flip-flops.
5. The multi-channel output controller of claim 4, wherein the channel module further comprises a two-input not AND gate, a first input terminal of the two-input not AND gate is configured to receive an external reset signal, a second input terminal of the two-input not AND gate is connected to the output terminal of the reset module and configured to receive an internal reset signal output by the reset module, and an output terminal of the two-input not AND gate is connected to the reset terminals of all the flip-flops.
6. The multi-channel output controller of claim 1, further comprising a schmitt trigger module having inputs for receiving the external channel acknowledge signal and the external data signal, and outputs coupled to the line decoder, the control module, and inputs of all of the output channels, respectively.
7. The multi-channel output controller of claim 1, further comprising a test module, said test module comprising a multi-input nand gate, M two-input nand gates, and a switch tube;
the first input ends of the two input NAND gates are connected with one output end of the line decoder, the second input ends of the two input NAND gates are connected with the output end of the output channel, the output ends of the two input NAND gates are connected with one input end of the multiple input NAND gate, the output end of the multiple input NAND gate is connected with the grid electrode of the switch tube, the source electrode of the switch tube is grounded, and the drain electrode of the switch tube is connected with the external detection circuit.
8. The multi-channel output controller of claim 1, wherein said line decoder includes 6 inputs and 64 outputs, and said channel block includes 64 output channels, each of said output channels being connected to a corresponding one of said line decoder outputs.
9. A PCB board defect detection system comprising a multi-channel output controller as claimed in any one of claims 1 to 8.
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