CN111384165B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN111384165B CN111384165B CN201811647738.1A CN201811647738A CN111384165B CN 111384165 B CN111384165 B CN 111384165B CN 201811647738 A CN201811647738 A CN 201811647738A CN 111384165 B CN111384165 B CN 111384165B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, relating to the technical field of microelectronics. The semiconductor device comprises a substrate, a semiconductor layer, a source electrode, a drain electrode and a grid electrode structure, wherein the semiconductor layer is manufactured on the substrate, the source electrode, the drain electrode and the grid electrode structure are manufactured on one side, far away from the substrate, of the semiconductor layer, the semiconductor layer comprises a barrier layer, the barrier layer is provided with a groove, a grid electrode dielectric layer in the grid electrode structure is manufactured on the basis of the groove, and the thickness of the grid electrode dielectric layer is designed to be larger than a preset value obtained through calculation according to the dielectric constant of the grid electrode dielectric layer, the dielectric constant of the barrier layer and the depth of the groove. Therefore, the capacitance between the grid metal layer of the grid dielectric layer and the channel layer is reduced, so that the threshold voltage is not changed, the transfer transconductance curve is flattened, and the linearity of the high-electron-mobility transistor device is improved.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a semiconductor device and a manufacturing method thereof.
Background
Nitride semiconductor materials, including GaN, have a High saturation Electron Mobility rate, a High breakdown voltage, and a wide bandgap, and because of these characteristics, High Electron Mobility Transistor (HEMT) devices based on GaN attract the attention of researchers and semiconductor manufacturers. The GaN HEMT device has extremely wide application prospect in the fields of high-speed, high-efficiency and high-frequency communication and power electronics in the next 20 years.
The inventors have studied and found that at high output power, the transfer function of the high electron mobility transistor becomes nonlinear, and the output power no longer increases with increasing input power, so that intermodulation distortion occurs in the communication system. This is mainly caused by the threshold voltage of the hemt, the transconductance of the hemt and the junction capacitance varying with the input power, and thus the signal distortion problem is caused because the linearity of the power amplifier device is poor and the gain is more easily compressed when the power amplifier device outputs high power. Therefore, how to achieve the purpose of keeping the threshold voltage constant and further flattening the transconductance curve of the transition so as to improve the linearity of the hemt device is an urgent technical problem to be solved.
Disclosure of Invention
The present invention provides a semiconductor device and a method for manufacturing the same.
The technical scheme provided by the invention is as follows:
a substrate;
the semiconductor layer is manufactured on one side of the substrate and comprises a barrier layer, and a groove is formed on one side, far away from the substrate, of the barrier layer; and
the grid structure comprises a grid dielectric layer and a grid metal layer, the grid dielectric layer is formed based on the groove, the grid metal layer is formed on one side, away from the substrate, of the grid dielectric layer, the thickness of the grid dielectric layer is larger than a preset value, and the preset value is obtained through calculation according to the dielectric constant of the grid dielectric layer, the dielectric constant of the barrier layer and the depth of the groove.
Further, the preset value is
ε ins Is the dielectric constant, epsilon, of the gate dielectric layer b Is the dielectric constant, t, of the barrier layer recess Is the depth of the groove.
Furthermore, the semiconductor device further comprises an insulating medium layer which is manufactured on one side of the barrier layer, which is far away from the substrate, an opening is formed at the position, corresponding to the groove, of the insulating medium layer, a gate groove is formed by communicating the insulating medium layer with the groove, the gate medium layer is deposited in the groove and extends into the opening, and the gate metal layer is arranged on one side, which is far away from the substrate, of the gate medium layer and extends out of the gate groove.
Further, the depth of the groove is smaller than the thickness of the gate dielectric layer.
Furthermore, the semiconductor layer further comprises a channel layer and a buffer layer, the buffer layer is manufactured on one side of the substrate, the channel layer is manufactured on one side of the buffer layer far away from the substrate, and the barrier layer is manufactured on one side of the channel layer far away from the buffer layer.
Further, the dielectric constant of the barrier layer is between 7 and 15, and the dielectric constant of the gate dielectric layer is between 2 and 15.
The present invention also provides a method for manufacturing a semiconductor device, comprising:
providing a substrate;
forming a semiconductor layer including a barrier layer on one side of the substrate;
manufacturing a source electrode and a drain electrode on the basis of the barrier layer, etching the barrier layer between the source electrode and the drain electrode to form a groove, and forming a grid dielectric layer on the basis of the groove, so that the thickness of the grid dielectric layer is larger than a preset value, wherein the preset value is obtained by calculation according to the dielectric constant of the grid dielectric layer, the dielectric constant of the barrier layer and the depth of the groove;
and manufacturing a grid metal layer based on the grid dielectric layer.
Further, the preset value is
ε ins Is the dielectric constant, epsilon, of the gate dielectric layer b Is the dielectric constant, t, of the barrier layer recess Is the depth of the groove.
Further, the step of etching the barrier layer between the source and drain electrodes to form a recess includes:
manufacturing an insulating medium layer positioned between the source electrode and the drain electrode based on the barrier layer;
and etching the insulating medium layer between the source electrode and the drain electrode to form an opening which penetrates through the insulating medium layer and is communicated with the groove, wherein the groove and the opening form a gate groove together.
Further, the step of manufacturing a gate metal layer based on the gate dielectric layer includes:
and depositing a metal material from one surface of the gate dielectric layer far away from the barrier layer, so that the metal material extends to the upper part of the insulating dielectric layer and partially covers the insulating dielectric layer to form a gate metal layer.
Further, the step of forming a gate dielectric layer based on the recess includes:
and depositing a dielectric material based on the groove, extending the dielectric material into the opening of the insulating dielectric layer, and enabling the thickness of the gate dielectric layer to be larger than the depth of the groove.
In the semiconductor device and the manufacturing method thereof provided by the embodiment of the application, the barrier layer is arranged through the groove, the gate dielectric layer in the gate structure is manufactured based on the groove, the thickness of the gate dielectric layer is made to be larger than a preset value, and the preset value is obtained through calculation according to the dielectric constant of the gate dielectric layer, the dielectric constant of the barrier layer and the depth of the groove, so that the capacitance between the gate metal layer arranged on the gate dielectric layer and the channel layer is reduced, the threshold voltage is not changed, the transfer transconductance curve is flattened, and the linearity of the high-electron-mobility transistor device is improved.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is another schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 3 is another schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Fig. 4 is a schematic view of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a semiconductor device manufactured based on steps S110-S130 in fig. 4 according to an embodiment of the present invention.
Fig. 6 is a schematic flow chart of step S130 in fig. 4.
Fig. 7 is a schematic structural diagram of a semiconductor device manufactured based on steps S110 to S120 in fig. 4 and step S132 in fig. 6.
Fig. 8 is a schematic structural diagram of a semiconductor device manufactured based on steps S110 to S120 in fig. 4 and step S134 in fig. 6.
Fig. 9 is a schematic structural diagram of a semiconductor device manufactured based on steps S110 to S130 in fig. 4 and steps S132 to S134 in fig. 6.
Icon: 100-a semiconductor device; 110-a substrate; 120-a semiconductor layer; 122-barrier layer; 122 a-grooves; 124-a channel layer; 126-a buffer layer; 130-source electrode; 140-a drain electrode; 150-a gate structure; 152-a gate dielectric layer; 154-gate metal layer; 160-insulating dielectric layer; 162-opening.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Referring to fig. 1, fig. 2 and fig. 3, an embodiment of the present invention provides a semiconductor device 100 including a substrate 110, a semiconductor layer 120, a source 130, a drain 140 and a gate structure 150.
The material of the substrate 110 may be determined according to actual needs. For example, the material of the substrate 110 may be sapphire, silicon nitride, gallium nitride, silicon or other material suitable for growing gallium nitride, and in the embodiment of the present application, without particular limitation, the deposition method of the substrate 110 may include CVD, VPE, MOCVD, LPCVD, PECVD, Pulsed Laser Deposition (PLD), atomic layer epitaxy, MBE, sputtering, evaporation, and the like. The present invention does not have any limitation on the material of the substrate 110 and the growth method thereof.
The semiconductor layer 120 is formed on one side of the substrate 110, the semiconductor layer 120 includes a barrier layer 122, and a groove 122a is formed on one side of the barrier layer 122 away from the substrate 110. The barrier layer 122 may be one or a combination of AlxGa1-xN, InxAl1-xN, AlN, and the like, and the side of the barrier layer 122 away from the substrate 110 may be formed with the recess 122a by masking, etching, and the like. Wherein, the cross section of the groove 122a may be rectangular, U-shaped, V-shaped or trapezoidal, and the depth d2 of the groove 122a may be set based on the thickness of the barrier layer 122 and the actual requirement.
The source 130, the drain 140 and the gate structure 150 are fabricated on a side of the barrier layer 122 away from the substrate 110, the gate structure 150 is located between the source 130 and the drain 140, the gate structure 150 includes a gate dielectric layer 152 and a gate metal layer 154, the gate dielectric layer 152 is fabricated on the basis of the groove 122a, the gate metal layer 154 is fabricated on a side of the gate dielectric layer 152 away from the substrate 110, and the thickness of the gate dielectric layer 152 is greater than a preset value, wherein the preset value is calculated according to the dielectric constant of the gate dielectric layer 152, the dielectric constant of the barrier layer 122 and the depth of the groove 122 a.
The source electrode 130 and the drain electrode 140 may be a single layer metal or a stack of multiple layers of metals, and may be made of one or more of nickel (Ni), aluminum (Al), titanium (Ti), gold (Au), or other metal materials. The gate dielectric layer 152 may be made of SiO2, AlN or alumina (Al2O3), etc. The gate metal layer 154 may be made of one or more of gold (Au), rhodium (Rh), indium (In), aluminum (Al), and titanium (Ti).
The shape of the gate structure 150 formed by the gate dielectric layer 152 and the gate metal layer 154 may be a T-shaped gate structure, a rectangular gate structure, or a trapezoidal field plate structure, and the like, which is not specifically limited herein, and may be set according to actual requirements.
It should be noted that the semiconductor layer 120 further includes a channel layer 124 disposed between the substrate 110 and the barrier layer 122, a semiconductor heterojunction is formed between the channel layer 124 and the barrier layer 122, a high concentration of two-dimensional electron gas is introduced into polarized charges at the interface of the heterojunction, so that the two-dimensional electron gas is formed at the interface between the channel layer 124 and the barrier layer 122, and the source electrode 130 and the drain electrode 140 are electrically connected to the two-dimensional electron gas in the semiconductor layer 120, and the electrical connection may be, but is not limited to, high temperature annealing, ion implantation, heavy doping, and the like. In the case of performing the high temperature annealing, the electrode metals of the source and drain electrodes 130 and 140 are electrically connected with the two-dimensional electron gas formed in the semiconductor layer 120. In the case of performing ion implantation and heavy doping, the source and drain electrodes 130 and 140 are composed of an ion-implanted portion or a heavily doped portion electrically connected with two-dimensional electron gas formed in the semiconductor layer 120 and an electrode thereon. The barrier layer 122 acts as a barrier to block the flow of carriers in the channel layer 124 toward the barrier layer 122.
The inventor has found that, in the prior art, when the gate structure 150 is fabricated, the barrier layer 122 under the gate structure 150 is etched and thinned to form the recess 122a, so as to reduce the two-dimensional electron gas concentration at the gate structure 150 and increase the ratio of the resistance (Rg) of the gate structure 150 to the total resistance, where Rtotal is Rs + Rd + Rg, Rs is the resistance of the source 130 and Rd is the resistance of the drain 140, so that the resistance of the gate structure 150 is dominant in the whole gate voltage range, thereby improving the flatness of transconductance. However, after etching, since the two-dimensional electron gas concentration at the corresponding position of the gate metal layer 154 is reduced and the barrier layer 122 becomes thinner, the threshold voltage of the semiconductor device 100 may move in the forward direction, and the schottky leakage may increase to reduce the two-dimensional electron gas concentration at the groove 122a, that is, the charge amount is reduced, and when the charge amount is reduced, the threshold voltage of the semiconductor device 100 may move in the forward direction, and the schottky leakage may increase.
According to the present application, the gate dielectric layer 152 is fabricated on the side of the gate dielectric layer 152 away from the substrate 110, and the appropriate thickness of the gate dielectric layer 152 is calculated according to the dielectric constant of the gate dielectric layer 152, the dielectric constant of the barrier layer 122 and the depth of the groove 122a, such that the capacitance (gate capacitance) between the gate metal layer 154 of the gate dielectric layer 152 and the channel layer 124 can be reduced, and according to the formula Q ═ C × V, when the charge amount Q is reduced, the gate capacitance C is reduced to ensure that the threshold voltage V tends to be unchanged and the leakage current can be effectively reduced, such that the transfer transconductance curve is flattened, thereby improving the linearity of the high-electron mobility transistor device.
Specifically, the preset value may be a ratio of the dielectric constant of the gate dielectric layer 152 to a product of the dielectric constant of the barrier layer 122 and the depth of the groove 122a, or may be a sum of the ratio and a constant, which is not specifically limited herein and may be set according to actual requirements.
Optionally, in this embodiment, the preset value is
ε ins Is the dielectric constant, ε, of the gate dielectric layer 152 b Is the dielectric constant, t, of the barrier layer 122 recess Is the depth of the groove 122 a.
The thickness of the barrier layer 122, the dielectric constant of the gate dielectric layer 152, the dielectric constant of the barrier layer 122, the thickness of the gate dielectric layer 152 and the depth of the groove 122a can be set according to practical application requirements, as long as the thickness of the barrier layer 122 is greater than the depth of the groove 122a, and the ratio of the dielectric constant of the gate dielectric layer 152 to the product of the dielectric constant of the barrier layer 122 and the depth of the groove 122a is smaller than the thickness of the gate dielectric layer 152, so that when the semiconductor device 100 is manufactured, when the materials and components of the barrier layer 122 and the gate dielectric layer 152 are changed, the gate capacitance of the semiconductor device 100 can be reduced to ensure that the threshold voltage tends to be unchanged, and the transfer transconductance curve is flattened, so that the linearity of the high-electron-mobility transistor device is improved.
In one embodiment, the cross-section of the recess 122a may be rectangular, the thickness of the barrier layer 122 may be in a range of 20nm to 40nm, the depth of the recess 122a may be in a range of 10nm to 30nm, and the thickness of the gate dielectric layer 152 may be in a range of 15nm to 35 nm.
In one embodiment, the dielectric constant of barrier layer 122 is between 7 and 15 and the dielectric constant of gate dielectric layer 152 is between 2 and 15. It should be understood that the dielectric constants of barrier layer 122 and gate dielectric layer 152 may vary depending on the device structure, and the illustration of the present embodiment is not intended to be limiting.
Based on the dielectric constant of the barrier layer 122 and the dielectric constant of the gate dielectric layer 152, the dielectric constant of the barrier layer 122 is generally larger than the dielectric constant of the gate dielectric layer 152, and therefore, in order to make the thickness of the gate dielectric layer 152 larger than the predetermined value, it is preferable that the depth of the groove 122a is smaller than the thickness of the gate dielectric layer 152 in this embodiment.
By setting the depth of the groove 122a to be smaller than the thickness of the gate dielectric layer 152, when the gate metal layer 154 is formed on the gate dielectric layer 152, the gate metal layer 154 can be prevented from contacting the semiconductor layer 120, and the semiconductor layer 120 is prevented from being broken down to generate a leakage current.
In this embodiment, the semiconductor device 100 further includes an insulating dielectric layer 160 formed on a side of the barrier layer 122 away from the substrate 110, an opening 162 is formed at a position corresponding to the groove 122a of the insulating dielectric layer 160, the opening is communicated with the groove 122a to form a gate trench, the gate dielectric layer 152 is deposited in the groove 122a and extends into the opening 162, and the gate metal layer 154 is disposed on a side of the gate dielectric layer 152 away from the substrate 110 and extends out of the gate trench.
The insulating dielectric layer 160 may further cover the source 130 and the drain 140, the insulating dielectric layer 160 may be made of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and when the insulating dielectric layer 160 is made of gallium nitride (GaN), the insulating dielectric layer may be formed by methods such as mocvb, PECVD, ALD, MBE, and the like.
By depositing the gate dielectric layer 152 in the groove 122a and extending into the opening 162, the gate metal layer 154 can be positioned in the insulating dielectric layer 160 under the condition that the gate capacitance is reduced to ensure that the threshold voltage tends to be unchanged, and the maximum electric field of the gate metal layer 154 can be kept in the insulating dielectric layer 160, so that the semiconductor layer 120 is prevented from being broken down, and the effect of reducing the electric leakage is achieved. In addition, the insulating dielectric layer 160 can also reduce ohmic contact resistance of the source electrode 130 and the drain electrode 140, improve electron mobility of the 2DEG in the channel, and increase a contact barrier of the gate metal layer 154 to perform insulating and passivation functions.
The semiconductor layer 120 further includes a channel layer 124, the buffer layer 126 is formed on a side of the substrate 110, the channel layer 124 is formed on a side of the buffer layer 126 away from the substrate 110, and the barrier layer 122 is formed on a side of the channel layer 124 away from the buffer layer 126.
Wherein the buffer layer 126 is located at one side of the substrate 110. The buffer layer 126 functions to adhere the channel layer 124 and protect the substrate 110 from some metal ions. The buffer layer 126 may be made of at least one material of indium aluminum gallium nitride (InAlGaN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), aluminum nitride (AlN), gallium nitride (GaN), and other semiconductor materials. For example, in the present embodiment, the buffer layer 126 is a gallium nitride (GaN) layer or an aluminum gallium nitride (AlGaN) layer with controllable aluminum content.
The channel layer 124 is located on a side of the buffer layer 126 away from the substrate 110 to provide a channel for movement of Two-Dimensional Electron Gas (2 DEG). The channel layer 124 may be one or more of undoped, n-doped or n-type partially doped GaN, AlxGa1-xN, InxAl1-xN, or AlN, with 0 < x < 1. For example, the channel layer 124 may be an unintentionally doped GaN layer.
In summary, in the semiconductor device 100 provided in the embodiment of the present application, by forming the groove 122a on the side of the barrier layer 122 away from the substrate 110, forming a gate dielectric layer 152 on the basis of the groove 122a, forming a gate metal layer 154 on the side of the gate dielectric layer 152 away from the substrate 110, wherein the thickness of the gate dielectric layer 152 is greater than a preset value, the preset value is calculated according to the dielectric constant of the gate dielectric layer 152, the dielectric constant of the barrier layer 122 and the depth of the groove 122a, the capacitance between the gate metal layer 154 of the gate dielectric layer 152 and the channel layer 124 can be reduced, as can be seen from the formula Q ═ C × V, when the charge quantity Q is reduced, the gate capacitance C is reduced to ensure that the threshold voltage V tends to be constant, so that the transfer transconductance curve is flattened, and the linearity of the high-electron-mobility transistor device is improved. Meanwhile, the thickness of the gate dielectric layer 152 is set to be greater than the depth of the groove 122a, and the insulating dielectric layer 160 is set to enable the maximum electric field of the gate metal layer 154 to be in the insulating dielectric layer 160, so that the semiconductor layer 120 is prevented from being broken down, and the effect of reducing electric leakage is achieved.
The embodiment of the present application further provides a method for manufacturing the semiconductor device 100, as shown in fig. 5, including the following steps S110 to S140.
In step S110, a substrate 110 is provided.
In step S120, a semiconductor layer 120 including a barrier layer 122 is formed on one side of the substrate 110.
After the preparation of the substrate 110 is completed, the substrate 110 may be placed in a growth chamber, and the semiconductor layer 120 may be formed on one side of the substrate 110 by using a metal organic chemical vapor deposition method. It is understood that the semiconductor layer 120 may be fabricated to include a channel layer 124 and a barrier layer 122, and further, a buffer layer 126 may be fabricated between the substrate 110 and the channel layer 124.
Specifically, in this embodiment, the step S120 includes: a buffer layer 126 is formed on a side of the substrate 110, a channel layer 124 is formed on a side of the buffer layer 126 remote from the substrate 110, and a barrier layer 122 is formed on a side of the channel layer 124 remote from the buffer layer 126.
Wherein the material of the semiconductor layer 120 may be a III-V compound, the channel layer 124 and the barrier layer 122 may form a heterojunction structure, and a two-dimensional electron gas layer is formed at an interface of the channel layer 124 and the barrier layer 122. The material of the barrier layer 122 may be any semiconductor material capable of forming a heterojunction structure with the channel layer 124, including gallium-based compound semiconductor materials or group III nitride semiconductor materials, such as InxAlyGazN1-x-y-z, where x is 0. ltoreq. 1, y is 0. ltoreq. 1, and z is 0. ltoreq. 1.
Step S130: manufacturing a source 130 and a drain 140 on the basis of the barrier layer 122, etching the barrier layer 122 between the source 130 and the drain 140 to form a groove 122a, and forming a gate dielectric layer 152 on the basis of the groove 122a, so that the thickness of the gate dielectric layer 152 is larger than a preset value. Referring to fig. 5, fig. 5 shows a semiconductor device 100 formed based on the above steps S110 to S130.
The preset value is calculated according to the dielectric constant of the gate dielectric layer 152, the dielectric constant of the barrier layer 122, and the depth of the groove 122 a.
Specifically, the preset value is
ε ins Is the dielectric constant, ε, of the gate dielectric layer 152 b Dielectric constant, t, of the barrier layer 122 recess The depth of the groove 122 a.
When the barrier layer 122 is etched, hydrogen, chlorine or ammonia gas may be used to etch in the MOCVD growth chamber in the MOCVD growth system, the depth of the groove 122a is smaller than the thickness of the barrier layer 122, and the cross section of the groove 122a may be a U-shaped, V-shaped or rectangular groove 122 a.
Specifically, the thickness of the barrier layer 122 ranges from 20nm to 40nm, the depth of the recess 122a ranges from 10nm to 30nm, and the thickness of the gate dielectric layer 152 ranges from 15nm to 35 nm. The dielectric constant of barrier layer 122 is between 7-15 and the dielectric constant of gate dielectric layer 152 is between 2-15.
Referring to fig. 6, in the present embodiment, the step of etching the barrier layer 122 between the source 130 and the drain 140 to form a recess 122a includes:
step S132: an insulating dielectric layer 160 is formed between the source 130 and drain 140 based on the barrier layer 122. Specifically, referring to fig. 7, fig. 7 illustrates the semiconductor device 100 fabricated and formed based on the steps S110 to S120 and the step S132.
It is understood that the insulating layer 160 may also cover the source 130 and the drain 140, wherein the insulating medium layer 160 may be a gallium nitride (GaN) layer and may be formed by MOCDV.
Step S134: etching the insulating medium layer 160 between the source 130 and the drain 140 to form an opening 162 penetrating through the insulating medium layer 160 and communicating with the groove 122a, wherein the groove 122a and the opening 162 together form a gate trench. Specifically, referring to fig. 8, fig. 8 shows the semiconductor device 100 formed based on the steps S110 to S120 and the steps S132 to S134.
The shape and size of the opening 162 may be the same as the shape and size of the groove 122a near the end of the opening 162.
When the barrier layer 122 is provided with an insulating dielectric layer 160 on the side away from the substrate, the step of forming the gate dielectric layer 152 based on the groove 122a includes: a dielectric material is deposited based on the recess 122a and extends into the opening 162 of the insulating dielectric layer 160 such that the thickness of the gate dielectric layer 152 is greater than the depth of the recess 122 a. Referring to fig. 9, fig. 9 shows a semiconductor device 100 obtained based on the above steps S110 to S130 and steps S132 to S134.
Step S140: a gate metal layer 154 is formed on the basis of the gate dielectric layer 152.
When the barrier layer 122 is formed with the insulating dielectric layer 160 on the side away from the substrate 110, step S140 may specifically be to deposit a metal material from the side of the gate dielectric layer 152 away from the barrier layer 122, so that the metal material extends to the upper side of the insulating dielectric layer 160 and partially covers the insulating dielectric layer 160, thereby forming the gate metal layer 154.
The gate structure 150 formed by the gate metal layer 154 and the gate dielectric layer 152 may be a T-shaped gate structure, a rectangular gate structure, or a trapezoidal field plate structure, which is not limited in this respect.
By adopting the above method, the gate dielectric layer 152 in the gate structure 150 is manufactured based on the groove 122a, and the thickness of the gate dielectric layer 152 is made to be larger than a preset value, and the preset value is calculated according to the dielectric constant of the gate dielectric layer 152, the dielectric constant of the barrier layer 122 and the depth of the groove 122a, so that the capacitance between the gate metal layer 154 of the gate dielectric layer 152 and the channel layer 124 is reduced, the threshold voltage is not changed, the transfer transconductance curve is flattened, and the linearity of the high-electron-mobility transistor device is improved. When the dielectric material is deposited on the basis of the groove 122a, the dielectric material is extended into the opening 162 of the insulating dielectric layer 160, so that the gate metal layer 154 manufactured on the gate dielectric layer 152 can be positioned in the insulating dielectric layer 160 under the condition that the threshold voltage tends to be unchanged by reducing the gate capacitance, the maximum electric field of the gate metal layer 154 can be prevented from being broken down, and the effect of reducing the electric leakage can be achieved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A semiconductor device, comprising:
a substrate;
the semiconductor layer is manufactured on one side of the substrate and comprises a barrier layer, and a groove is formed on one side, far away from the substrate, of the barrier layer; and
the grid structure comprises a grid dielectric layer and a grid metal layer, the grid dielectric layer is formed based on the groove, the grid metal layer is formed on one side, away from the substrate, of the grid dielectric layer, the thickness of the grid dielectric layer is larger than a preset value, and the preset value is obtained through calculation according to the dielectric constant of the grid dielectric layer, the dielectric constant of the barrier layer and the depth of the groove;
the preset value is
ε ins Is the dielectric constant, epsilon, of the gate dielectric layer b Is the dielectric constant, t, of the barrier layer recess Is the depth of the groove.
2. The semiconductor device according to claim 1, further comprising an insulating dielectric layer formed on a side of the barrier layer away from the substrate, wherein an opening is formed at a position corresponding to the groove of the insulating dielectric layer and is communicated with the groove to form a gate trench, the gate dielectric layer is deposited in the groove and extends into the opening, and the gate metal layer is disposed on a side of the gate dielectric layer away from the substrate and extends out of the gate trench.
3. The semiconductor device of claim 1, wherein a depth of the recess is less than a thickness of the gate dielectric layer.
4. The semiconductor device according to claim 1, wherein the semiconductor layer further comprises a channel layer and a buffer layer, the buffer layer is formed on a side of the substrate, the channel layer is formed on a side of the buffer layer away from the substrate, and the barrier layer is formed on a side of the channel layer away from the buffer layer.
5. The semiconductor device of claim 1, wherein the barrier layer has a dielectric constant between 7-15 and the gate dielectric layer has a dielectric constant between 2-15.
6. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate;
forming a semiconductor layer including a barrier layer on one side of the substrate;
manufacturing a source electrode and a drain electrode on the basis of the barrier layer, etching the barrier layer between the source electrode and the drain electrode to form a groove, and forming a grid dielectric layer on the basis of the groove, so that the thickness of the grid dielectric layer is larger than a preset value, wherein the preset value is obtained by calculation according to the dielectric constant of the grid dielectric layer, the dielectric constant of the barrier layer and the depth of the groove;
manufacturing a grid metal layer based on the grid dielectric layer;
the preset value is
ε ins Is the dielectric constant, epsilon, of the gate dielectric layer b Is the dielectric constant, t, of the barrier layer recess Is the depth of the groove.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the step of etching the barrier layer between the source and drain electrodes to form a groove comprises:
manufacturing an insulating medium layer positioned between the source electrode and the drain electrode on the basis of the barrier layer;
and etching the insulating medium layer between the source electrode and the drain electrode to form an opening which penetrates through the insulating medium layer and is communicated with the groove, wherein the groove and the opening form a gate groove together.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming a gate metal layer on the basis of the gate dielectric layer comprises:
and depositing a metal material from one surface of the gate dielectric layer far away from the barrier layer, so that the metal material extends to the upper part of the insulating dielectric layer and partially covers the insulating dielectric layer to form a gate metal layer.
9. The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming a gate dielectric layer based on the recess comprises:
and depositing a dielectric material based on the groove, extending the dielectric material into the opening of the insulating dielectric layer, and enabling the thickness of the gate dielectric layer to be larger than the depth of the groove.
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| US20080093626A1 (en) * | 2006-10-20 | 2008-04-24 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
| CN104409497A (en) * | 2014-11-26 | 2015-03-11 | 西安电子科技大学 | La base gate based AlGaN/GaN high electron mobility transistor and manufacturing method |
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| JP2006222414A (en) * | 2005-01-14 | 2006-08-24 | Matsushita Electric Ind Co Ltd | Semiconductor apparatus |
| US20080093626A1 (en) * | 2006-10-20 | 2008-04-24 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
| CN104409497A (en) * | 2014-11-26 | 2015-03-11 | 西安电子科技大学 | La base gate based AlGaN/GaN high electron mobility transistor and manufacturing method |
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