CN111372394A - Method for improving deviation of multilayer PCB (printed circuit board) and multilayer PCB - Google Patents
Method for improving deviation of multilayer PCB (printed circuit board) and multilayer PCB Download PDFInfo
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- CN111372394A CN111372394A CN202010173521.2A CN202010173521A CN111372394A CN 111372394 A CN111372394 A CN 111372394A CN 202010173521 A CN202010173521 A CN 202010173521A CN 111372394 A CN111372394 A CN 111372394A
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000008602 contraction Effects 0.000 claims abstract description 26
- 238000010030 laminating Methods 0.000 claims description 2
- 238000005553 drilling Methods 0.000 abstract description 3
- IYZWUWBAFUBNCH-UHFFFAOYSA-N 2,6-dichlorobiphenyl Chemical compound ClC1=CC=CC(Cl)=C1C1=CC=CC=C1 IYZWUWBAFUBNCH-UHFFFAOYSA-N 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000691 measurement method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
Abstract
The embodiment of the invention discloses a method for improving the deviation of a multilayer PCB (printed circuit board), which comprises the following steps: target holes are formed in the long side of the multilayer PCB and the short side of the multilayer PCB; measuring the expansion and contraction values among all layers of the multilayer PCB; and adjusting the inner layer compensation coefficient of the multilayer PCB according to the expansion and contraction value. By applying the technical scheme of the embodiment of the invention, target holes are formed in the long side of the multilayer PCB and the short side of the multilayer PCB; measuring the expansion and contraction values among all layers of the multilayer PCB; the inner layer compensation coefficient of the multilayer PCB is adjusted according to the expansion and contraction value, and the layer deviation of the multilayer PCB can be adjusted through the inner layer compensation coefficient, so that the layer deviation of the multilayer PCB can be reduced, the condition that the layer deviation is scrapped due to expansion and contraction among core plates of the PCB can be avoided, and meanwhile, the drilling efficiency can be improved.
Description
Technical Field
The invention relates to the technical field of PCB manufacturing, in particular to a method for improving the layer deviation of a multilayer PCB and the multilayer PCB.
Background
A Printed Circuit Board (PCB) is an important electronic component, a support for an electronic component, and a carrier for electrical connection of the electronic component.
In the production process of the multilayer PCB, how to achieve the non-deviation between the layers is a great problem. With the continuous development of the PCB industry, people find in the process that the multilayer PCB formed by stacking different core board thicknesses is often consistent in the four corner layers after lamination, the improvement effect is low, and even batch scrapping can be caused in severe cases. Therefore, how to improve the layer bias of the multilayer PCB becomes a technical problem to be solved urgently in the field.
Disclosure of Invention
The embodiment of the invention provides a method for improving the layer deviation of a multilayer PCB (printed circuit board) and the multilayer PCB, aiming at solving the problem of the layer deviation of the multilayer PCB in the prior art.
In a first aspect, an embodiment of the present invention provides a method for improving layer bias of a multilayer PCB, where the method for improving layer bias of the multilayer PCB includes:
target holes are formed in the long side of the multilayer PCB and the short side of the multilayer PCB;
measuring the expansion and contraction values among all layers of the multilayer PCB;
and adjusting the inner layer compensation coefficient of the multilayer PCB according to the expansion and contraction value.
The further technical scheme is that the measuring of the expansion and contraction value among each layer of the multilayer PCB comprises the following steps:
and measuring the expansion and shrinkage values among all layers of the multilayer PCB by laminating X-RAY.
The further technical scheme is that the adjusting the inner layer compensation coefficient of the multilayer PCB according to the expansion and contraction value comprises the following steps:
calculating the inner layer compensation coefficient of the multilayer PCB by the following formula k ═ a/d × 10000-0.5%%, wherein k is the inner layer compensation coefficient, a is the expansion and contraction value and d is the target hole distance.
The further technical scheme is that at least one group of target holes are formed in the long edge of the multilayer PCB and the short edge of the multilayer PCB.
The further technical proposal is that target holes on the long side of the multilayer PCB are collinear; and target holes on the short sides of the multilayer PCB are collinear.
The further technical proposal is that target holes on the long edge of the multilayer PCB are positioned on the base number layer or the even number layer of the multilayer PCB; the target holes on the short sides of the multilayer PCB are positioned on the base number layer or the even number layer of the multilayer PCB.
In a second aspect, an embodiment of the present invention further provides a multilayer PCB, where target holes are formed in both a long side and a short side of the multilayer PCB, and the target holes are applied to the method for improving the layer offset of the multilayer PCB according to any one of claims 1 to 6.
The further technical scheme is that at least one group of target holes are formed in the long edge of the multilayer PCB and the short edge of the multilayer PCB.
The further technical proposal is that target holes on the long side of the multilayer PCB are collinear; and target holes on the short sides of the multilayer PCB are collinear.
The further technical proposal is that target holes on the long edge of the multilayer PCB are positioned on the odd layers or even layers of the multilayer PCB; the target holes on the short sides of the multilayer PCB are positioned on odd layers or even layers of the multilayer PCB.
The embodiment of the invention provides a method for improving the deviation of a multilayer PCB (printed circuit board), which comprises the following steps: target holes are formed in the long side of the multilayer PCB and the short side of the multilayer PCB; measuring the expansion and contraction values among all layers of the multilayer PCB; and adjusting the inner layer compensation coefficient of the multilayer PCB according to the expansion and contraction value. By applying the technical scheme of the embodiment of the invention, target holes are formed in the long side of the multilayer PCB and the short side of the multilayer PCB; measuring the expansion and contraction values among all layers of the multilayer PCB; the inner layer compensation coefficient of the multilayer PCB is adjusted according to the expansion and contraction value, and the layer deviation of the multilayer PCB can be adjusted through the inner layer compensation coefficient, so that the layer deviation of the multilayer PCB can be reduced, the condition that the layer deviation is scrapped due to expansion and contraction among core plates of the PCB can be avoided, and meanwhile, the drilling efficiency can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a method for improving a layer bias of a multi-layer PCB according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a multilayer PCB board according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Referring to fig. 1-2, fig. 1 is a schematic flow chart illustrating a method for improving a layer bias of a multi-layer PCB according to an embodiment of the present invention. As shown, the method includes the following steps S1-S3.
And S1, forming target holes on the long edge of the multilayer PCB and the short edge of the multilayer PCB.
In specific implementation, target holes are formed in the long edge of the multilayer PCB and the short edge of the multilayer PCB. At least one group of target holes are formed in the long edge of the multilayer PCB and the short edge of the multilayer PCB. Meanwhile, target holes on the long edges of the multilayer PCB are collinear; and target holes on the short sides of the multilayer PCB are collinear.
Further, the target holes on the long side of the multilayer PCB are positioned on the base number layer or the even number layer of the multilayer PCB; the target holes on the short sides of the multilayer PCB are positioned on the base number layer or the even number layer of the multilayer PCB. In the implementation, the engineering CAM is required to add a set of target holes on even layers or odd layers respectively when manufacturing the inner layer data of the multi-layer PCB, and the target holes are designed on the same straight line.
It should be noted that the group of target holes described in the embodiment of the present invention means that two opposite sides of the PCB respectively include at least 2 target holes, that is, two sides of the long side or the short side each include at least 2 target holes as a group.
It should be noted that how many groups of target holes are determined according to the number of layers of the multilayer PCB design, for example, 1 group of target holes is respectively located on the long side and the short side of the multilayer PCB with 4 layers, 2 groups of target holes are respectively located on the long side and the short side of the multilayer PCB with 6 layers, 3 groups of target holes are respectively located on the long side and the short side of the multilayer PCB with 8 layers, and so on.
And S2, measuring the expansion and contraction values among the layers of the multilayer PCB.
In a specific implementation, the expansion and contraction values among all layers of the multilayer PCB are measured.
In one embodiment, the amount of shrinkage and expansion between layers of the multi-layer PCB is measured by stitching X-RAY. It should be noted that the above stitching X-RAY measurement is only one alternative measurement method provided by the present invention, and those skilled in the art may also adopt other measurement methods without departing from the scope of the present invention.
And S3, adjusting the inner layer compensation coefficient of the multilayer PCB according to the expansion and contraction value.
In a specific implementation, the inner layer compensation coefficient of the multilayer PCB is adjusted according to the expansion and contraction value. And adjusting the layer deviation of the multilayer PCB through the inner layer compensation coefficient.
In one embodiment, the inner layer compensation coefficient of the multi-layer PCB is calculated by the following formula k ═ a/d ×. 10000-0.5%%, where k is the inner layer compensation coefficient, a is the expansion and contraction value, and d is the target hole distance.
By applying the technical scheme provided by the embodiment of the invention, target holes are formed in the long side of the multilayer PCB and the short side of the multilayer PCB; measuring the expansion and contraction values among all layers of the multilayer PCB; the inner layer compensation coefficient of the multilayer PCB is adjusted according to the expansion and contraction value, and the layer deviation of the multilayer PCB can be adjusted through the inner layer compensation coefficient, so that the layer deviation of the multilayer PCB can be reduced, the condition that the layer deviation is scrapped due to expansion and contraction among core plates of the PCB can be avoided, and meanwhile, the drilling efficiency can be improved.
Referring to fig. 2, an embodiment of the present invention further provides a multi-layer PCB 10, wherein target holes 11 are formed on both a long side of the multi-layer PCB 10 and a short side of the multi-layer PCB 10, and the target holes 11 are applied to a method for improving a layer offset of the multi-layer PCB as provided in the above embodiments.
In one embodiment, at least one set of target holes 11 is formed on both the long side of the multi-layer PCB 10 and the short side of the multi-layer PCB 10.
In one embodiment, the target holes 11 on the long side of the multilayer PCB board 10 are collinear; the target holes 11 on the short sides of the multilayer PCB 10 are collinear.
In one embodiment, the target holes 11 on the long side of the multilayer PCB 10 are located on the odd or even layers of the multilayer PCB 10; the target holes 11 on the short sides of the multi-layered PCB 10 are located at odd or even layers of the multi-layered PCB 10. In the implementation, the engineering CAM is required to add a set of target holes 11 on even layers or odd layers respectively and to be designed on the same straight line when manufacturing the inner layer data of the multi-layer PCB 10.
It should be noted that how many groups are determined according to the number of layers designed for the multilayer PCB 10, for example, 1 group of target holes 11 is respectively arranged on the long side and the short side of the multilayer PCB 10 with 4 layers, 2 groups of target holes 11 are respectively arranged on the long side and the short side of the multilayer PCB 10 with 6 layers, 3 groups of target holes 11 are respectively arranged on the long side and the short side of the multilayer PCB 10 with 8 layers, and so on.
It is understood that the steps in the method according to the embodiment of the present invention may be sequentially adjusted, combined, and deleted according to actual needs. The units in the device of the embodiment of the invention can be merged, divided and deleted according to actual needs.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, while the invention has been described with respect to the above-described embodiments, it will be understood that the invention is not limited thereto but may be embodied with various modifications and changes.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method of improving layer deflection of a multi-layer PCB, comprising:
target holes are formed in the long side of the multilayer PCB and the short side of the multilayer PCB;
measuring the expansion and contraction values among all layers of the multilayer PCB;
and adjusting the inner layer compensation coefficient of the multilayer PCB according to the expansion and contraction value.
2. The method for improving the layer bias of the multi-layer PCB as recited in claim 1, wherein the measuring the shrinkage and expansion values among the layers of the multi-layer PCB comprises:
and measuring the expansion and shrinkage values among all layers of the multilayer PCB by laminating X-RAY.
3. The method for improving the layer bias of the multi-layer PCB of claim 2, wherein the adjusting the inner layer compensation coefficient of the multi-layer PCB according to the shrinkage value comprises:
calculating the inner layer compensation coefficient of the multilayer PCB by the following formula k ═ a/d × 10000-0.5%%, wherein k is the inner layer compensation coefficient, a is the expansion and contraction value and d is the target hole distance.
4. The method for improving the layer bias of the multi-layer PCB according to claim 3, wherein at least one set of target holes are formed on both the long side and the short side of the multi-layer PCB.
5. The method for improving the layer bias of the multi-layer PCB of claim 4, wherein the target holes on the long side of the multi-layer PCB are collinear; and target holes on the short sides of the multilayer PCB are collinear.
6. The method for improving the layer bias of the multi-layer PCB according to claim 5, wherein the target holes on the long side of the multi-layer PCB are positioned on the base layer or the even layer of the multi-layer PCB; the target holes on the short sides of the multilayer PCB are positioned on the base number layer or the even number layer of the multilayer PCB.
7. A multi-layer PCB board is characterized in that target holes are formed in the long side of the multi-layer PCB board and the short side of the multi-layer PCB board, and the target holes are applied to the method for improving the layer deviation of the multi-layer PCB board as claimed in any one of claims 1 to 6.
8. The multi-layer PCB of claim 7, wherein at least one set of target holes is formed on each of the long side and the short side of the multi-layer PCB.
9. The multilayer PCB board of claim 8, wherein the target holes on the long sides of the multilayer PCB board are collinear; and target holes on the short sides of the multilayer PCB are collinear.
10. The multilayer PCB of claim 9, wherein the target holes on the long side of the multilayer PCB are located at odd or even layers of the multilayer PCB; the target holes on the short sides of the multilayer PCB are positioned on odd layers or even layers of the multilayer PCB.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010173521.2A CN111372394A (en) | 2020-03-13 | 2020-03-13 | Method for improving deviation of multilayer PCB (printed circuit board) and multilayer PCB |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010173521.2A CN111372394A (en) | 2020-03-13 | 2020-03-13 | Method for improving deviation of multilayer PCB (printed circuit board) and multilayer PCB |
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| CN111372394A true CN111372394A (en) | 2020-07-03 |
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| CN202010173521.2A Pending CN111372394A (en) | 2020-03-13 | 2020-03-13 | Method for improving deviation of multilayer PCB (printed circuit board) and multilayer PCB |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113778513A (en) * | 2021-09-15 | 2021-12-10 | 定颖电子(黄石)有限公司 | Automatic generation method, device and equipment of PCB drilling program and storage medium |
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| CN103702516A (en) * | 2013-12-17 | 2014-04-02 | 梅州市志浩电子科技有限公司 | Printed circuit board factor calculation method and calculation system |
| CN104918424A (en) * | 2015-07-03 | 2015-09-16 | 深圳市迅捷兴电路技术有限公司 | Method for stabilizing size of circuit board with core boards of different thicknesses |
| CN105376963A (en) * | 2015-11-04 | 2016-03-02 | 江门崇达电路技术有限公司 | Method for grabbing internal layer compensation coefficients |
| CN106659001A (en) * | 2016-11-21 | 2017-05-10 | 深圳市五株科技股份有限公司 | Multilayer PCB expansion and shrinkage measuring compensation method |
| CN106852030A (en) * | 2017-03-14 | 2017-06-13 | 奥士康精密电路（惠州）有限公司 | A kind of method of determination PCB internal layer film penalty coefficients |
| CN109600941A (en) * | 2019-01-28 | 2019-04-09 | 鹤山市世安电子科技有限公司 | A kind of PCB multilayer circuit board interlayer change in size measurement method |
-
2020
- 2020-03-13 CN CN202010173521.2A patent/CN111372394A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103702516A (en) * | 2013-12-17 | 2014-04-02 | 梅州市志浩电子科技有限公司 | Printed circuit board factor calculation method and calculation system |
| CN104918424A (en) * | 2015-07-03 | 2015-09-16 | 深圳市迅捷兴电路技术有限公司 | Method for stabilizing size of circuit board with core boards of different thicknesses |
| CN105376963A (en) * | 2015-11-04 | 2016-03-02 | 江门崇达电路技术有限公司 | Method for grabbing internal layer compensation coefficients |
| CN106659001A (en) * | 2016-11-21 | 2017-05-10 | 深圳市五株科技股份有限公司 | Multilayer PCB expansion and shrinkage measuring compensation method |
| CN106852030A (en) * | 2017-03-14 | 2017-06-13 | 奥士康精密电路（惠州）有限公司 | A kind of method of determination PCB internal layer film penalty coefficients |
| CN109600941A (en) * | 2019-01-28 | 2019-04-09 | 鹤山市世安电子科技有限公司 | A kind of PCB multilayer circuit board interlayer change in size measurement method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113778513A (en) * | 2021-09-15 | 2021-12-10 | 定颖电子(黄石)有限公司 | Automatic generation method, device and equipment of PCB drilling program and storage medium |
| CN113778513B (en) * | 2021-09-15 | 2024-02-23 | 超颖电子电路股份有限公司 | Automatic generation method, device, equipment and storage medium for PCB drilling program |
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Application publication date: 20200703 |