JPH0699334A - Correcting method for machining position of multilayer substrate - Google Patents

Correcting method for machining position of multilayer substrate

Info

Publication number
JPH0699334A
JPH0699334A JP4249298A JP24929892A JPH0699334A JP H0699334 A JPH0699334 A JP H0699334A JP 4249298 A JP4249298 A JP 4249298A JP 24929892 A JP24929892 A JP 24929892A JP H0699334 A JPH0699334 A JP H0699334A
Authority
JP
Japan
Prior art keywords
point
machining position
marks
mark
line segment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4249298A
Other languages
Japanese (ja)
Inventor
Shusuke Tateishi
秀典 立石
Akira Busujima
明 毒島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Mechanics Ltd
Original Assignee
Hitachi Seiko Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Seiko Ltd filed Critical Hitachi Seiko Ltd
Priority to JP4249298A priority Critical patent/JPH0699334A/en
Publication of JPH0699334A publication Critical patent/JPH0699334A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To drill with high accuracy circuit patterns on a multilayer substrate by comparing measurement results obtained before and after laminating four marks forming a min. rectangle surrounding a machining position with each other and by correcting the machining position specified by programs based on the comparison result. CONSTITUTION:A plurality of measuring marks P11 to P76 are placed in matrix shape at predetermined intervals on a prelaminated printed substrate 1. The distance from the reference position to each mark P11 to P76 is measured. Next, in machining the laminated multilayered substrate, the distance from the reference position to each mark P11 to P76 is again measured to compare measurement results obtained before and after laminating four marks, P34, P35, P44, and P45, forming tire min. rectangle surrounding the machining position H1 with each other. The machining position H1 specified by programs is corrected to the actual machining position based on the comparison result.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多層基板に穴明けを行
うのに好適な加工位置補正方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing position correcting method suitable for making a hole in a multilayer substrate.

【0002】[0002]

【従来の技術】プリント基板は、配線の高密度化ととも
に多層化が進められている。プリント基板の穴明け加工
においても多層基板の加工が増加している。この多層基
板の穴明け加工は、個別に形成されたプリント基板とプ
リプレグとを工具に積層し、高温高圧下で加熱圧着した
後に行なっている。
2. Description of the Related Art Printed circuit boards are being multilayered as the wiring density is increased. Processing of multi-layered boards is also increasing in the drilling of printed boards. The drilling of the multilayer substrate is performed after the individually formed printed circuit board and prepreg are laminated on a tool and thermocompression bonded under high temperature and high pressure.

【0003】[0003]

【発明が解決しようとする課題】多層基板においては、
加熱圧着工程が入るため、伸縮による変形が発生し、し
かも、その変形は多層基板1枚ごとに異なっている。こ
のため、加工プログラムで指定された位置にそのまま穴
明けを行うと、形成された配線パターンと穴の位置がず
れてしまうため、加工不良が発生する。
In the case of a multi-layer substrate,
Since the thermocompression bonding step is included, deformation due to expansion and contraction occurs, and the deformation is different for each multilayer substrate. For this reason, if a hole is directly formed at the position designated by the machining program, the formed wiring pattern and the position of the hole are misaligned with each other, resulting in defective machining.

【0004】本発明の目的は、上記の事情に鑑み、加熱
圧着時の伸縮により変形が生じた多層基板の配線パター
ンに対して精度良く穴明けが行えるようにした多層基板
の加工位置補正方法を提供することにある。
In view of the above-mentioned circumstances, an object of the present invention is to provide a method for correcting a processing position of a multi-layer substrate, which is capable of accurately punching a wiring pattern of the multi-layer substrate which is deformed by expansion and contraction during thermocompression bonding. To provide.

【0005】[0005]

【課題を解決するための手段】上記の目的を達成するた
め、本発明においては、積層前のプリント基板に所定の
間隔で複数の測定用のマークをマトリックス状に配置す
るとともに、基準位置から各マークまでの距離を計測
し、積層後の多層基板を加工する際に、再び前記基準位
置から各マークまでの距離を計測し、加工位置を囲む最
小の矩形を形成する4個のマークの積層前後の測定結果
を比較するとともに、その比較結果に基づいて、プログ
ラムから指定された加工位置を補正する。
In order to achieve the above object, according to the present invention, a plurality of measurement marks are arranged in a matrix at predetermined intervals on a printed circuit board before lamination, and each measurement mark is arranged from a reference position. Before and after stacking four marks that measure the distance to the mark and measure the distance from the reference position to each mark again when processing the laminated multilayer board to form the smallest rectangle surrounding the processing position. The measurement results are compared, and the machining position designated by the program is corrected based on the comparison result.

【0006】[0006]

【作用】上記における補正方法の原理を図3に基づいて
説明する。点P1と点P2を結ぶ線分Aと、点P3と点
P4を結ぶ線分Bが、点P1と点P3が距離V1、点P
2と点P4が距離V2だけ離れているとき、各線分A、
Bの同一比率α内分点R1、R2の距離を求める。線分
Aと、点P1と点R1を結ぶ線分aとの比は、 A:a=1:α ・・・(1) となる。同様に、線分Bと、点P3と点R2を結ぶ線分
bの比も、 B:b=1:α ・・・(2) となる。
The principle of the above correction method will be described with reference to FIG. A line segment A connecting the points P1 and P2, a line segment B connecting the points P3 and P4, a distance V1 between the points P1 and P3, and a point P
2 and the point P4 are separated by a distance V2, each line segment A,
The distances of the same ratio α internal division points R1 and R2 of B are calculated. The ratio of the line segment A to the line segment a connecting the points P1 and R1 is as follows: A: a = 1: α (1) Similarly, the ratio of the line segment B and the line segment b connecting the points P3 and R2 is also B: b = 1: α (2).

【0007】ここで、線分Bを距離V2だけ平行移動さ
せ、点P2と点P4を重ねる。そして、点P3、点R2
の移動後の位置を、それぞれ点P31、点R21とする
と、点P3と点P31の間には、 P3=P1+V1 ・・・(3) P3=P31+V2 ・・・(4) の関係が成り立つ。そして、点P31と点P1の距離V
11は、 V11=V1+V2 ・・・(5) で求めることができる。
Here, the line segment B is translated by the distance V2, and the point P2 and the point P4 are overlapped. Then, the point P3 and the point R2
Assuming that the positions after the movement of P are point P31 and point R21, respectively, the relationship of P3 = P1 + V1 (3) P3 = P31 + V2 (4) is established between the points P3 and P31. Then, the distance V between the point P31 and the point P1
11 can be obtained by V11 = V1 + V2 (5)

【0008】ここで、三角形P1P2P31と、三角形
R1P2R21は相似形であるから、点R1と点R21
の距離V12は、 V12=(A−a)/A・(V1−V2) =(1−α)(V1−V2) ・・・(6) である。よって、(6)式により、点R1と点R2の距
離V13は、 V13=(1−α)V1+αV2 ・・・(7) により求めることができる。
Since the triangle P1P2P31 and the triangle R1P2R21 are similar figures, the points R1 and R21 are the same.
The distance V12 is V12 = (A−a) / A · (V1−V2) = (1−α) (V1−V2) (6). Therefore, from the equation (6), the distance V13 between the points R1 and R2 can be obtained by the following equation: V13 = (1-α) V1 + αV2 (7)

【0009】[0009]

【実施例】以下、本発明の一実施例を図に基づいて説明
する。図1は本発明における測定用のマークの配置を示
すもので、1はプリント基板。P11ないしP76は測
定用のマークで、所定の間隔でマトリックス状に形成さ
れている。これらのマークP11ないしP76は、例え
ば、穴明け加工により形成する。そして、例えば、穴明
け加工時の基準位置から各マークP11ないしP76ま
での位置を、積層前後に測定し記録する。積層前の各マ
ークを、それぞれ点P11ないし点P76、積層後の各
マークを、それぞれ点P11gないし点P76gとす
る。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the arrangement of measurement marks in the present invention, where 1 is a printed circuit board. P11 to P76 are marks for measurement, which are formed in a matrix at predetermined intervals. These marks P11 to P76 are formed by, for example, drilling. Then, for example, the positions from the reference position during punching to the marks P11 to P76 are measured and recorded before and after the stacking. The marks before lamination are designated as points P11 to P76, and the marks after lamination are designated as points P11g to P76g, respectively.

【0010】いま、加工プログラムで指定された加工位
置H1が、点P34、点P35、点P44、点P45で
囲まれた領域内にあるとする。前記各点P34、点P3
5、点P44、点P45で囲まれた領域を拡大すると図
2のようになる。図2において、点P34、点P35、
点P44、点P45に対する点P34g、点P35g、
点P44g、点P45gの移動量をそれぞれV1、V
2、V3、V4とする、また、点P34と点P35を結
ぶ線分をA1、点P35と点P45を結ぶ線分をB1、
点P45と点P44を結ぶ線分をC1、点P44と点P
34を結ぶ線分をD1とし、点P34gと点P35gを
結ぶ線分をA2、点P35gと点P45gを結ぶ線分を
B2、点P45gと点P44gを結ぶ線分をC2、点P
44gと点P34gを結ぶ線分をD2とする。
Now, it is assumed that the machining position H1 designated by the machining program is in the area surrounded by the points P34, P35, P44 and P45. The points P34 and P3
FIG. 2 is an enlarged view of the area surrounded by 5, point P44, and point P45. In FIG. 2, points P34, P35,
Point P34g, point P35g for point P44, point P45,
The movement amounts of point P44g and point P45g are V1 and V, respectively.
2, V3, V4, the line segment connecting the points P34 and P35 is A1, the line segment connecting the points P35 and P45 is B1,
The line segment connecting the points P45 and P44 is C1, and the point P44 and the point P are
A line segment connecting 34 is D1, a line segment connecting point P34g and point P35g is A2, a line segment connecting point P35g and point P45g is B2, a line segment connecting point P45g and point P44g is C2, and point P is
A line segment connecting 44g and the point P34g is defined as D2.

【0011】いま、積層前の状態でプログラムにより指
定された加工位置H1に対する積層後の実加工位置H2
を求める。前記各点P34、点P35、点P44、点P
45と、点P34g、点P35g、点P44g、点P4
5gのの間には、 P34g=P34+V1 ・・・(8) P35g=P35+V2 ・・・(9) P44g=P44+V3 ・・(10) P45g=P45+V4 ・・(11) の関係がある。
Now, the actual machining position H2 after the lamination with respect to the machining position H1 designated by the program before the lamination.
Ask for. Each point P34, point P35, point P44, point P
45, point P34g, point P35g, point P44g, point P4
There is a relationship of P34g = P34 + V1 (8) P35g = P35 + V2 (9) P44g = P44 + V3 ... (10) P45g = P45 + V4 ... (11) between 5g.

【0012】加工プログラムで指定された加工位置H1
を通り、線分A1と平行な線分A11を引き、線分B
1、D1との交点を求め、それぞれ点R1、点R2とす
る。同様に、加工位置H1を通り、線分B1と平行な線
分B11を引き、線分A1、C1との交点を求め、それ
ぞれ点S1、点S2とする。線分B1と、点P35と点
R1を結ぶ線分b1の比を、1:αとする。また、線分
A1と、点P35と点S1を結ぶ線分a1の比を、1:
βとする。すると、点R1に対する点R11のずれ量V
11は、 V11=R11−R1 =(1−α)V2+αV4 ・・(12) また、点R2に対する点R21のずれ量V41は、 V41=R21−R2 =(1−α)V1+αV3 ・・(13) で求められる。
The machining position H1 designated by the machining program
Line segment A1 parallel to line segment A1 and draw line segment B
The intersections with 1 and D1 are obtained, and are defined as points R1 and R2, respectively. Similarly, a line segment B11 that passes through the processing position H1 and is parallel to the line segment B1 is drawn, and the intersections with the line segments A1 and C1 are obtained, which are set as points S1 and S2, respectively. The ratio of the line segment B1 and the line segment b1 connecting the points P35 and R1 is set to 1: α. Further, the ratio of the line segment A1 and the line segment a1 connecting the points P35 and S1 is 1:
Let β. Then, the shift amount V of the point R11 with respect to the point R1
11 is V11 = R11-R1 = (1-α) V2 + αV4 ··· (12) Further, the deviation amount V41 of the point R21 with respect to the point R2 is V41 = R21−R2 = (1-α) V1 + αV3 ··· (13) Required by.

【0013】よって、加工位置H1に対する実加工位置
H2のずれ量V0は、 V0=H1−H2 =(1−β)V11+βV41 =V2+α(V4−V2)+β(V1−V2)+αβ(V2−V4+V3 −V1) ・・(14) で求められる。したがって、加工プログラムで加工位置
H1を指令されたとき、その実加工位置H2は、 H2=P35+V2+α(V4−V2)+β(V1−V2)+αβ(V2− V4+V3−V1) ・・(15) で求めることができる。このようにして実加工位置H2
を求め、補正することにより、先に形成された回路パタ
ーンに対し、正確に穴明けをすることができる。
Therefore, the deviation amount V0 of the actual machining position H2 with respect to the machining position H1 is: V0 = H1-H2 = (1-β) V11 + βV41 = V2 + α (V4-V2) + β (V1-V2) + αβ (V2-V4 + V3- V1) ··· (14) Therefore, when the machining position H1 is commanded by the machining program, the actual machining position H2 is obtained by H2 = P35 + V2 + α (V4-V2) + β (V1-V2) + αβ (V2-V4 + V3-V1) ··· (15) You can In this way, the actual machining position H2
By obtaining and correcting the above, it is possible to accurately make a hole in the previously formed circuit pattern.

【0014】なお、上記測定用のマークP11ないしP
76の測定用の基準位置は、加工機の原点位置、プログ
ラム上の原点位置、あるいは基板に圧入される基準ピン
の軸心位置など都合の良い位置を設定すれば良い。ま
た、各マークは、積層される複数のプリント基板の内、
外層の1枚にのみ形成するばよい。また、マークの形成
位置は、外層の回路パターンが形成されない位置、ある
いは、複数のプリント基板を接続する桟に形成すること
ができる。
The measuring marks P11 to P11
The reference position for measurement of 76 may be set at a convenient position such as the origin position of the processing machine, the origin position on the program, or the axial center position of the reference pin press-fitted into the board. In addition, each mark is a plurality of printed circuit boards that are stacked,
It only has to be formed on one of the outer layers. Further, the mark can be formed at a position where the outer layer circuit pattern is not formed, or at a crosspiece that connects a plurality of printed boards.

【0015】[0015]

【発明の効果】以上述べた如く、本発明によれば、積層
前のプリント基板に所定の間隔で複数の測定用のマーク
をマトリックス状に配置するとともに、基準位置から各
マークまでの距離を計測し、積層後の多層基板を加工す
る際に、再び前記基準位置から各マークまでの距離を計
測し、加工位置を囲む最小の矩形を形成する4個のマー
クの積層前後の測定結果を比較するとともに、その比較
結果に基づいて、プログラムから指定された加工位置を
補正するようにしたので、積層された多層基板に不規則
な変形があっても、加工位置の近くのマークの測定結果
に基づいて補正することができるので、多層基板の回路
パターンに対し、高精度の穴明けを行うことができる。
As described above, according to the present invention, a plurality of measurement marks are arranged in a matrix on the printed circuit board before lamination at a predetermined interval, and the distance from the reference position to each mark is measured. Then, when processing the laminated multilayer substrate, the distance from the reference position to each mark is measured again, and the measurement results before and after the lamination of the four marks forming the smallest rectangle surrounding the processing position are compared. At the same time, based on the comparison result, the processing position specified by the program is corrected, so even if the laminated multilayer boards have irregular deformation, it is based on the measurement result of the mark near the processing position. Since it can be corrected by the correction, the circuit pattern of the multilayer substrate can be punched with high precision.

【図面の簡単な説明】[Brief description of drawings]

【図1】プリント基板に対する測定用のマークの配置を
示す平面図。
FIG. 1 is a plan view showing the arrangement of measurement marks on a printed circuit board.

【図2】本発明による補正方法を示す説明図。FIG. 2 is an explanatory diagram showing a correction method according to the present invention.

【図3】本発明の考え方を示す模式図。FIG. 3 is a schematic diagram showing the concept of the present invention.

【符号の説明】[Explanation of symbols]

1 プリント基板 H1、H2 加工位置 P11ないしP76 測定用のマーク 1 Printed circuit board H1, H2 Processing position P11 to P76 Mark for measurement

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】積層前のプリント基板に所定の間隔で複数
の測定用のマークをマトリックス状に配置するととも
に、基準位置から各マークまでの距離を計測し、積層後
の多層基板を加工する際に、再び前記基準位置から各マ
ークまでの距離を計測し、加工位置を囲む最小の矩形を
形成する4個のマークの積層前後の測定結果を比較する
とともに、その比較結果に基づいて、プログラムから指
定された加工位置を補正することを特徴とする多層基板
の加工位置補正方法。
1. When a plurality of measuring marks are arranged in a matrix on a printed circuit board before stacking at predetermined intervals, and a distance from a reference position to each mark is measured to process a multilayer board after stacking. In addition, the distance from the reference position to each mark is measured again, and the measurement results before and after stacking the four marks forming the minimum rectangle surrounding the processing position are compared, and based on the comparison result, the program A method for correcting a processing position of a multilayer substrate, which comprises correcting a specified processing position.
JP4249298A 1992-09-18 1992-09-18 Correcting method for machining position of multilayer substrate Pending JPH0699334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4249298A JPH0699334A (en) 1992-09-18 1992-09-18 Correcting method for machining position of multilayer substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4249298A JPH0699334A (en) 1992-09-18 1992-09-18 Correcting method for machining position of multilayer substrate

Publications (1)

Publication Number Publication Date
JPH0699334A true JPH0699334A (en) 1994-04-12

Family

ID=17190902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4249298A Pending JPH0699334A (en) 1992-09-18 1992-09-18 Correcting method for machining position of multilayer substrate

Country Status (1)

Country Link
JP (1) JPH0699334A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006075932A (en) * 2004-09-08 2006-03-23 Hitachi Via Mechanics Ltd Drilling method of work and drilling device
JP2011028182A (en) * 2009-07-29 2011-02-10 Hitachi Via Mechanics Ltd Exposure method of wiring pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006075932A (en) * 2004-09-08 2006-03-23 Hitachi Via Mechanics Ltd Drilling method of work and drilling device
JP2011028182A (en) * 2009-07-29 2011-02-10 Hitachi Via Mechanics Ltd Exposure method of wiring pattern

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