CN111341793A - 显示基板及其制作方法、显示装置 - Google Patents
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Abstract
本公开提供一种显示基板及其制作方法、显示装置,该显示基板包括:衬底基板以及设置于所述衬底基板上的多个像素,每一所述像素包括多个子像素,每一所述子像素包括依次层叠设置的第一有源层、第一栅绝缘层、栅极、第二栅绝缘层、第二有源层、第一绝缘层、源极和漏极;所述源极通过贯穿所述第一绝缘层、所述第二栅绝缘层和所述第一栅绝缘层的过孔与所述第一有源层连接,所述源极和漏极通过贯穿所述第一绝缘层的过孔与所述第二有源层连接。本公开在不改变像素尺寸及开口率的情况下,有效降低薄膜晶体管的漏电流,改善灰阶亮点和Flicker等相关不良。
Description
技术领域
本公开实施例涉及显示技术领域,尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
目前AR(增强现实)/VR(虚拟现实)显示装置发展迅速,对其应用的显示面板要求也急剧增加。AR/VR显示装置多为1000PPI(像素密度)级别产品,其像素尺寸约为10μm(微米),多采用TFT(薄膜晶体管)双栅结构,但随着AR/VR市场需求增加,为实现细腻的画质,消除颗粒感及眩晕效果,对更高PPI的显示面板需求强烈(如1500+PPI)。1500+PPI显示面板的像素尺寸限制在5~6μm,按照原有设计无法再设置双栅结构的薄膜晶体管,只能采用单栅结构。单栅结构的薄膜晶体管漏电流较大,容易产生灰阶亮点和Flicker(闪烁)等不良。
发明内容
本公开实施例提供一种显示基板及其制作方法、显示装置,用于解决高PPI显示装置中使用单栅结构的薄膜晶体管,导致漏电流大,容易产生灰阶亮点和Flicker等不良的问题。
为了解决上述技术问题,本公开是这样实现的:
第一方面,本公开实施例提供了一种显示基板,包括:衬底基板以及设置于所述衬底基板上的多个像素,每一所述像素包括多个子像素,每一所述子像素包括依次层叠设置的第一有源层、第一栅绝缘层、栅极、第二栅绝缘层、第二有源层、第一绝缘层、源极和漏极;所述源极通过贯穿所述第一绝缘层、所述第二栅绝缘层和所述第一栅绝缘层的过孔与所述第一有源层连接,所述源极和漏极通过贯穿所述第一绝缘层的过孔与所述第二有源层连接。
可选的,所述第二有源层在所述衬底基板上的正投影位于所述第一有源层在所述衬底基板上的正投影区域内。
可选的,所述显示基板还包括:数据线和第二绝缘层,所述数据线设置于所述衬底基板的靠近所述第一有源层的一侧,所述第二绝缘层设置于所述数据线和所述第一有源层之间,所述第一有源层通过贯穿所述第二绝缘层的过孔与所述数据线连接。
可选的,所述第一有源层和所述第二有源层在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影区域内。
可选的,所述显示基板还包括:第三绝缘层、像素电极、第四绝缘层和公共电极,所述像素电极通过贯通所述第三绝缘层的过孔与所述漏极连接,所述第四绝缘层设置于所述像素电极和所述公共电极之间。
可选的,所述显示基板的像素密度大于或等于1500像素/英寸。
第二方面,本公开实施例提供了一种显示装置,包括上述第一方面的显示基板。
可选的,所述显示装置为增强现实显示装置或虚拟现实显示装置。
第三方面,本公开实施例提供了一种显示基板的制作方法,包括:
提供衬底基板;
在所述衬底基板上依次形成第一有源层、第一栅绝缘层、栅极、第二栅绝缘层、第二有源层、第一绝缘层、源极和漏极;所述源极通过贯穿所述第一绝缘层、所述第二栅绝缘层和所述第一栅绝缘层的过孔与所述第一有源层连接,所述源极和漏极通过贯穿所述第一绝缘层的过孔与所述第二有源层连接。
可选的,所述第二有源层在所述衬底基板上的正投影位于所述第一有源层在所述衬底基板上的正投影区域内。
可选的,在所述衬底基板上形成第一有源层之前还包括:
在所述衬底基板上形成数据线;
在所述数据线上形成第二绝缘层,并在所述第二绝缘层上形成过孔;所述第一有源层通过贯穿所述第二绝缘层的过孔与所述数据线连接。
可选的,在所述衬底基板上形成源极和漏极之后还包括:
形成第三绝缘层,并在所述第三绝缘层上形成过孔;
形成像素电极,所述像素电极通过贯通所述第三绝缘层的过孔与所述漏极连接;
形成第四绝缘层;
形成公共电极。
本公开实施例中,通过设置上下叠层结构的有源层,在叠层有源层之间设置栅极和栅绝缘层,实现等同于双栅结构效果的薄膜晶体管,在不改变像素尺寸及开口率的情况下,有效降低薄膜晶体管的漏电流,改善灰阶亮点和Flicker(闪烁)等相关不良,带来更好的客户体验。
附图说明
图1为本公开实施例的显示基板的平面示意图;
图2为本公开实施例的显示基板的截面示意图;
图3为本公开一实施例的显示基板的制作方法的流程示意图;
图4-图14为本公开另一实施例的显示基板的制作方法的流程示意图。
具体实施方式
下面将结合本公开实施例中的附图,对本公开实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本公开一部分实施例,而不是全部的实施例。基于本公开中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本公开保护的范围。
为解决高PPI显示装置中使用单栅结构的薄膜晶体管,导致漏电流大,容易产生灰阶亮点和Flicker等不良的问题,请参考图1和图2,本公开实施例提供一种显示基板,包括:衬底基板101以及设置于所述衬底基板101上的多个像素,每一所述像素包括多个子像素,每一所述子像素包括依次层叠设置的第一有源层104、第一栅绝缘层105、栅极106、第二栅绝缘层107、第二有源层108、第一绝缘层109、源极110和漏极111;所述源极110通过贯穿所述第一绝缘层109、所述第二栅绝缘层107和所述第一栅绝缘层105的过孔与所述第一有源层104连接,所述源极110和漏极111通过贯穿所述第一绝缘层109的过孔与所述第二有源层108连接。
本公开实施例中,通过设置上下叠层结构的有源层,在叠层有源层之间设置栅极和栅绝缘层,实现等同于双栅结构效果的薄膜晶体管,在不改变像素尺寸及开口率的情况下,有效降低薄膜晶体管的漏电流,改善灰阶亮点和Flicker(闪烁)等相关不良,带来更好的客户体验。
本公开实施例中,可选的,所述衬底基板101可以为玻璃基板或者其他材质的基板。
本公开实施例中,所述第一有源层104用于形成等同于双栅结构效果的薄膜晶体管的第一开关。所述第一有源层104可以采用poly(多晶硅),或者,为其他半导体材料,例如IGZO(铟镓锌氧化物)等。
本公开实施例中,可选的,第一栅绝缘层105和第二栅绝缘层107可以采用相同的绝缘材料,也可以采用不同的材料。
本公开实施例中,栅极106用于控制薄膜晶体管的导通,可选的,栅极106采用金属材料形成。
本公开实施例中,所述第二有源层108用于形成等同于双栅结构效果的薄膜晶体管的第二开关。所述第二有源层108可以采用poly,或者,为其他半导体材料,例如IGZO等。所述第二有源层108可以与第一有源层104的材料相同,也可以不同。
本公开实施例中,所述第一绝缘层105为层间绝缘层,用于间隔源极、漏极与第二有源层108,并用于形成过孔。
本公开实施例中,源极110和漏极111可以采用金属材料形成,其中,源极110和漏极111可以与栅极106采用相同的金属材料,也可以采用不同的金属材料。
本公开实施例中,可选的,请参考图2,所述第二有源层108在所述衬底基板101上的正投影位于所述第一有源层104在所述衬底基板101上的正投影区域内,从而进一步提高像素的开口率。
本公开实施例中,可选的,请参考图1和图2,所述显示基板还包括:数据线102和第二绝缘层103,所述数据线102设置于所述衬底基板101的靠近所述第一有源层104的一侧,所述第二绝缘层103设置于所述数据线102和所述第一有源层104之间,所述第一有源层104通过贯穿所述第二绝缘层103的过孔与所述数据线102连接。所述数据线102用于向薄膜晶体管传输数据信号,同时还可以起到隔离衬底基板101中的金属离子的作用。
本公开实施例中,可选的,所述第一有源层104和所述第二有源层108在所述衬底基板101上的正投影位于所述数据线102在所述衬底基板101上的正投影区域内,即所述数据线102可以复用为第一有源层104和第二有源层108的遮光层,避免第一有源层104和第二有源层108被背光的光线照射,提高薄膜晶体管的性能。
当然,在本公开的其他一些实施例中,数据线102也可以与源极110和漏极111同层同材料设置,通过一次构图工艺形成,以节省掩膜数量。
本公开实施例中,可选的,所述显示基板还包括:第三绝缘层112、像素电极113、第四绝缘层114和公共电极115,所述像素电极113通过贯通所述第三绝缘层112的过孔与所述漏极111连接,所述第四绝缘层114设置于所述像素电极113和所述公共电极115之间。
本公开实施例中,可选的,所述第三绝缘层112可以为平坦化层,同时用于隔离源极110和漏极111。
本公开实施例中,可选的,所述第四绝缘层114可以为PVX(钝化)层。
本公开实施例中,可选的,所述像素电极113和所述公共电极114用于形成像素驱动电场,本公开实施例中的公共电极114上形成有条状镂空。所述像素电极113和所述公共电极114可以采用相同的透明导电材料形成,所述透明导电材料例如为ITO(氧化铟锡)等。
本公开实施例中,可选的,所述显示基板的像素密度大于或等于1500PPI(像素/英寸),可用于形成高PPI显示装置。
本公开实施例还提供一种显示装置,包括上述任一实施例中的显示基板。
可选的,所述显示装置为AR(增强现实)显示装置或VR(虚拟现实)显示装置。
请参考图3,本公开实施例还提供一种显示基板的制作方法,包括:
步骤31:提供衬底基板;
步骤32:在所述衬底基板上依次形成第一有源层、第一栅绝缘层、栅极、第二栅绝缘层、第二有源层、第一绝缘层、源极和漏极;所述源极通过贯穿所述第一绝缘层、所述第二栅绝缘层和所述第一栅绝缘层的过孔与所述第一有源层连接,所述源极和漏极通过贯穿所述第一绝缘层的过孔与所述第二有源层连接。
本公开实施例中,通过形成上下叠层结构的有源层,在叠层有源层之间形成栅极和栅绝缘层,实现等同于双栅结构效果的薄膜晶体管,在不改变像素尺寸及开口率的情况下,有效降低薄膜晶体管的漏电流,改善灰阶亮点和Flicker(闪烁)等相关不良,带来更好的客户体验。
本公开实施例中,可选的,所述第二有源层在所述衬底基板上的正投影位于所述第一有源层在所述衬底基板上的正投影区域内。
本公开实施例中,可选的,在所述衬底基板上形成第一有源层之前还包括:
步骤301:在所述衬底基板上形成数据线;
步骤302:在所述数据线上形成第二绝缘层,并在所述第二绝缘层上形成过孔;所述第一有源层通过贯穿所述第二绝缘层的过孔与所述数据线连接;所述第一有源层和所述第二有源层在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影区域内。
本公开实施例中,可选的,在所述衬底基板上形成源极和漏极之后还包括:
步骤33:形成第三绝缘层,并在所述第三绝缘层上形成过孔;
步骤34:形成像素电极,所述像素电极通过贯通所述第三绝缘层的过孔与所述漏极连接;
步骤35:形成第四绝缘层;
步骤36:形成公共电极。
请参考图4-图14,图4-图14为本公开另一实施例的显示基板的制作方法的流程示意图,该方法包括:
步骤41:请参考图4,在衬底基板(图未示出)上形成数据线102;
步骤42:请参考图5,在所述数据线102上形成第二绝缘层(图未示出),并在所述第二绝缘层上形成过孔A1;
步骤43:请参考图6,在所述第二绝缘层上形成第一有源层104,所述第一有源层104通过过孔A1与所述数据线102连接;
步骤44:请参考图7,在所述第一有源层104上形成第一栅绝缘层(图未示出),并在第一栅绝缘层上形成栅极106;与栅极106同时形成的还包括栅线;
步骤45:请参考图8,在所述栅极106上形成第二栅绝缘层(图未示出),并在所述第二栅绝缘层上形成第二有源层108;
步骤46:请参考图9,在所述第二有源层108上形成第一绝缘层(图未示出),并在所述第一绝缘层上形成过孔A2;
步骤47:请参考图10,形成贯通第一绝缘层、第二栅绝缘层和第一栅绝缘层的过孔A3;
步骤48:请参考图11,形成源极110和漏极111,其中,源极110通过过孔A2与第二有源层108连接,漏极111通过过孔A2与第二有源层108连接,源极110通过过孔A3与第一有源层104连接。
步骤49:请参考图12,形成第二绝缘层(图未示出),并在所述第二绝缘层上形成过孔A4;
步骤410:请参考图13,形成像素电极113,所述像素电极113通过贯通所述第三绝缘层的过孔A4与所述漏极111连接;
步骤411:请参考图14,形成第三绝缘层(图未示出),并在第三绝缘层上形成公共电极115。
上面结合附图对本公开的实施例进行了描述,但是本公开并不局限于上述的具体实施方式,上述的具体实施方式仅仅是示意性的,而不是限制性的,本领域的普通技术人员在本公开的启示下,在不脱离本公开宗旨和权利要求所保护的范围情况下,还可做出很多形式,均属于本公开的保护之内。
Claims (12)
1.一种显示基板,其特征在于,包括:衬底基板以及设置于所述衬底基板上的多个像素,每一所述像素包括多个子像素,每一所述子像素包括依次层叠设置的第一有源层、第一栅绝缘层、栅极、第二栅绝缘层、第二有源层、第一绝缘层、源极和漏极;所述源极通过贯穿所述第一绝缘层、所述第二栅绝缘层和所述第一栅绝缘层的过孔与所述第一有源层连接,所述源极和漏极通过贯穿所述第一绝缘层的过孔与所述第二有源层连接。
2.如权利要求1所述的显示基板,其特征在于,所述第二有源层在所述衬底基板上的正投影位于所述第一有源层在所述衬底基板上的正投影区域内。
3.如权利要求1所述的显示基板,其特征在于,还包括:数据线和第二绝缘层,所述数据线设置于所述衬底基板的靠近所述第一有源层的一侧,所述第二绝缘层设置于所述数据线和所述第一有源层之间,所述第一有源层通过贯穿所述第二绝缘层的过孔与所述数据线连接。
4.如权利要求3所述的显示基板,其特征在于,所述第一有源层和所述第二有源层在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影区域内。
5.如权利要求1所述的显示基板,其特征在于,还包括:第三绝缘层、像素电极、第四绝缘层和公共电极,所述像素电极通过贯通所述第三绝缘层的过孔与所述漏极连接,所述第四绝缘层设置于所述像素电极和所述公共电极之间。
6.如权利要求1所述的显示基板,其特征在于,所述显示基板的像素密度大于或等于1500像素/英寸。
7.一种显示装置,其中,包括如权利要求1-6任一项所述的显示基板。
8.如权利要求7所述的显示装置,其特征在于,所述显示装置为增强现实显示装置或虚拟现实显示装置。
9.一种显示基板的制作方法,其特征在于,包括:
提供衬底基板;
在所述衬底基板上依次形成第一有源层、第一栅绝缘层、栅极、第二栅绝缘层、第二有源层、第一绝缘层、源极和漏极;所述源极通过贯穿所述第一绝缘层、所述第二栅绝缘层和所述第一栅绝缘层的过孔与所述第一有源层连接,所述源极和漏极通过贯穿所述第一绝缘层的过孔与所述第二有源层连接。
10.如权利要求9所述的制作方法,其特征在于,所述第二有源层在所述衬底基板上的正投影位于所述第一有源层在所述衬底基板上的正投影区域内。
11.如权利要求9所述的制作方法,其特征在于,在所述衬底基板上形成第一有源层之前还包括:
在所述衬底基板上形成数据线;
在所述数据线上形成第二绝缘层,并在所述第二绝缘层上形成过孔;所述第一有源层通过贯穿所述第二绝缘层的过孔与所述数据线连接;所述第一有源层和所述第二有源层在所述衬底基板上的正投影位于所述数据线在所述衬底基板上的正投影区域内。
12.如权利要求9所述的制作方法,其特征在于,在所述衬底基板上形成源极和漏极之后还包括:
形成第三绝缘层,并在所述第三绝缘层上形成过孔;
形成像素电极,所述像素电极通过贯通所述第三绝缘层的过孔与所述漏极连接;
形成第四绝缘层;
形成公共电极。
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CN113809099A (zh) * | 2021-09-02 | 2021-12-17 | 武汉华星光电技术有限公司 | 一种阵列基板及显示面板 |
CN114690493A (zh) * | 2022-03-18 | 2022-07-01 | 武汉华星光电技术有限公司 | 显示面板 |
WO2022151576A1 (zh) * | 2021-01-15 | 2022-07-21 | 武汉华星光电技术有限公司 | 显示面板 |
WO2023130501A1 (zh) * | 2022-01-06 | 2023-07-13 | 惠州华星光电显示有限公司 | 阵列基板及液晶显示面板 |
Citations (2)
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US20190326382A1 (en) * | 2018-04-19 | 2019-10-24 | Lg Display Co., Ltd. | Electro-luminescent display device with improved contact structure |
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US20190326382A1 (en) * | 2018-04-19 | 2019-10-24 | Lg Display Co., Ltd. | Electro-luminescent display device with improved contact structure |
Cited By (7)
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---|---|---|---|---|
WO2021196999A1 (zh) * | 2020-04-03 | 2021-10-07 | 京东方科技集团股份有限公司 | 显示基板及其制作方法、显示装置 |
WO2022151576A1 (zh) * | 2021-01-15 | 2022-07-21 | 武汉华星光电技术有限公司 | 显示面板 |
US11796874B2 (en) | 2021-01-15 | 2023-10-24 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Display panel |
CN113809099A (zh) * | 2021-09-02 | 2021-12-17 | 武汉华星光电技术有限公司 | 一种阵列基板及显示面板 |
WO2023130501A1 (zh) * | 2022-01-06 | 2023-07-13 | 惠州华星光电显示有限公司 | 阵列基板及液晶显示面板 |
CN114690493A (zh) * | 2022-03-18 | 2022-07-01 | 武汉华星光电技术有限公司 | 显示面板 |
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