CN111312819A - 一种堆叠纳米线或片环栅器件及其制备方法 - Google Patents

一种堆叠纳米线或片环栅器件及其制备方法 Download PDF

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CN111312819A
CN111312819A CN201911113939.8A CN201911113939A CN111312819A CN 111312819 A CN111312819 A CN 111312819A CN 201911113939 A CN201911113939 A CN 201911113939A CN 111312819 A CN111312819 A CN 111312819A
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silicon substrate
gate
stacked
fin
stacked nanowire
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CN111312819B (zh
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李永亮
程晓红
张青竹
殷华湘
王文武
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Institute of Microelectronics of CAS
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Abstract

本发明公开了一种堆叠纳米线或片环栅器件，包括：硅衬底；堆叠纳米线或片，形成在硅衬底上方，且沿第一方向延伸，堆叠纳米线或片包括若干上下层叠的纳米线或片；栅堆叠，栅堆叠包围每个堆叠纳米线或片，且沿第二方向延伸，栅堆叠沿第一方向两侧的侧壁上形成有第一侧墙；源/漏区，位于每个栅堆叠沿第一方向的两侧；沟道区，包括位于第一侧墙之间的堆叠纳米线或片；其中，堆叠纳米线或片与硅衬底之间具有向内凹入的凹口结构，凹口结构内形成有隔离物，隔离物能够将堆叠纳米线或片与硅衬底隔离；确保硅基沟道，或，Ge等高迁移率沟道在保持高性能的条件下降低漏电流，从而改善器件特性。同时，本发明还提供一种堆叠纳米线或片环栅器件的制备方法。

Description

一种堆叠纳米线或片环栅器件及其制备方法
技术领域
本发明涉及半导体技术领域，具体涉及一种堆叠纳米线或片环栅器件及其制备方法。
背景技术
随着器件特征尺寸进入到5纳米技术节点，小尺度量子效应造成迁移率退化，以及器件不断微缩带来的应变工程出现饱和效应，使得器件的性能随着器件尺寸的微缩，而逐步退化；SiGe或Ge高迁移率沟道材料因具有更高的载流子迁移率，成为了新型三维器件研究的热点。
但是，由于Ge等高迁移率材料的禁带宽度较小，存在比硅基沟道更严重的漏电问题，从而降低了器件性能。
发明内容
为了克服现有技术中由硅基沟道，或，Ge等高迁移率沟道材料制备的堆叠纳米线或片环栅器件存在严重漏电的技术问题，本发明提供一种堆叠纳米线或片环栅器件及其制备方法。
本发明所述的堆叠纳米线或片环栅器件，包括：硅衬底；
堆叠纳米线或片，堆叠纳米线或片形成在硅衬底上方，且沿第一方向延伸，堆叠纳米线或片包括若干上下层叠的纳米线或片；
栅堆叠，栅堆叠包围每个堆叠纳米线或片，且沿第二方向延伸，栅堆叠沿第一方向两侧的侧壁上形成有第一侧墙；
源/漏区，源/漏区位于每个栅堆叠沿第一方向的两侧；
沟道区，沟道区包括位于第一侧墙之间的堆叠纳米线或片；
其中，堆叠纳米线或片与硅衬底之间具有向内凹入的凹口结构，凹口结构内形成有隔离物，隔离物能够将堆叠纳米线或片与硅衬底隔离。
优选地，隔离物为氧化物。
优选地，堆叠纳米线或片为Si1-yGey；其中，0≤y≤1。
优选地，硅衬底与凹口结构之间，或，硅衬底与凹口结构之间以及栅堆叠与凹口结构之间具有硅刻蚀结构。
优选地，硅衬底与凹口结构之间，或，硅衬底与凹口结构之间以及栅堆叠与凹口结构之间具有应变缓冲结构；其中，应变缓冲结构为Si1-zGez，0≤z≤0.8。
同时，本发明还提供一种堆叠纳米线或片环栅器件的制备方法，包括以下步骤：
提供硅衬底，并在硅衬底上形成交替堆叠的牺牲层和材料层；
沿第一方向，在硅衬底上形成若干第一鳍部，以及位于若干第一鳍部上的若干第二鳍部；
在硅衬底上形成凹口结构；
在凹口结构上形成隔离物，以将第一鳍部和硅衬底隔离；
沿第二方向，在若干第一鳍部和第二鳍部上形成牺牲栅，以牺牲栅两侧的第一侧墙；
在第一侧墙两侧的第二鳍部，或，第一鳍部和第二鳍部上刻蚀并生长源漏外延层，形成源/漏区；
进行替代栅处理，形成堆叠纳米线或片环栅器件。
优选地，在硅衬底上形成交替堆叠的牺牲层和材料层前，在硅衬底上形成应变缓冲层，其中，应变缓冲层为Si1-zGez，0≤z≤0.8，层厚为0.5至3.5μm。
优选地，在硅衬底上形成凹口结构的步骤包括：
对若干第一鳍部和第二鳍部进行O2等离子体钝化处理；
采用偏各向同性刻蚀工艺，在硅衬底上形成凹口结构。
优选地，在硅衬底上形成凹口结构的步骤包括：
在若干第一鳍部和第二鳍部沿第一方向和第二方向的侧壁上形成第二侧墙；
采用偏各向同性刻蚀工艺，在硅衬底上形成凹口结构。
优选地，在硅衬底上形成凹口结构后，并在凹口结构上形成隔离物前，在硅衬底上形成第三鳍部。
优选地，在凹口结构上形成隔离物的步骤包括：
在O2基气氛中，对第一鳍部、第二鳍部、凹口结构和第三鳍部进行氧化处理；
循环上述操作若干次，在凹口结构上形成隔离物，以将第一鳍部和硅衬底隔离。
优选地，氧化处理的氧化温度为600至900℃，氧化时间为30至60s，循环次数为1至5次。
优选地，进行替代栅处理的步骤包括：
在已形成的结构上沉积氧化介质层，并对氧化介质层进行平坦化处理；
去除牺牲栅；并去除栅极区域内的牺牲层，或，牺牲层和第一鳍部，形成沟道区；
在沟道区上依次形成栅极介质层和栅极。
优选地，材料层为Si、Si1-yGey或Ge，层厚为8至25nm；牺牲层为Si1-xGex，层厚为5至25nm；其中，0≤y≤1，0≤x≤0.8。
综上所述，本发明所述的堆叠纳米线或片环栅器件，提供了一种新的高迁移率沟道堆叠纳米线或片环栅器件结构，具体地，在硅衬底上方，且在堆叠纳米线或片下方的凹口结构内形成有氧化物进行隔离，可以确保硅基沟道，或，Ge等高迁移率沟道在保持高性能的条件下降低漏电流，从而改善器件特性。
本发明提供的堆叠纳米线或片环栅器件的制备方法，同样具有可将硅基沟道，或，Ge等高迁移率沟道，通过其下方凹口结构内的氧化物，与硅衬底进行隔离，在保持高性能的条件下降低漏电流的优点。
附图说明
图1是在硅衬底上交替形成牺牲层和材料层后结构示意图；
图2是在硅衬底上形成应变缓冲层，以及交替形成牺牲层和材料层后结构示意图；
图3是在图1基础上，形成第一鳍部和第二鳍部后结构示意图；
图4是在图2基础上，形成第一鳍部和第二鳍部后结构示意图；
图5是在图3基础上，形成凹口结构后结构示意图；
图6是在图4基础上，形成凹口结构后结构示意图；
图7是在图5基础上，形成第三鳍部后结构示意图；
图8是在图6基础上，形成第三鳍部后结构示意图；
图9是在图3基础上，形成第一鳍部和第二鳍部侧壁上的第二侧墙后结构示意图；
图10是在图9基础上，形成凹口结构后结构示意图；
图11是在图10基础上，形成第三鳍部后结构示意图；
图12是在图7基础上，形成凹口结构内的氧化物后结构示意图；
图13是在图12基础上，形成浅槽隔离后结构示意图；
图14是在图13基础上，形成第一侧墙，并去除掉牺牲栅后结构剖视图；
图15是本发明涉及的堆叠纳米线或片环栅器件的第一种具体实施例；
图16是本发明涉及的堆叠纳米线或片环栅器件的第二种具体实施例；
图17是本发明涉及的堆叠纳米线或片环栅器件的第三种具体实施例；
图18是本发明涉及的堆叠纳米线或片环栅器件的第四种具体实施例；
图19是本发明涉及的堆叠纳米线或片环栅器件的制备方法流程图。
其中，1为硅衬底，2为牺牲层，3为材料层，4为第一鳍部，5为第二鳍部，6为凹口结构，7为第三鳍部，8为氧化物，9为第一侧墙，10为应变缓冲层，11为第二侧墙，12为浅槽隔离，13为沟道区，14为栅极介质层，15为栅极。
具体实施方式
下面结合附图说明根据本发明的具体实施方式。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是，本发明还可以采用其他不同于在此描述的其他方式来实施，因此，本发明并不限于下面公开的具体实施例的限制。
为了克服现有技术中由硅基沟道，或，Ge等高迁移率沟道材料制备的堆叠纳米线或片环栅器件存在严重漏电的技术问题，本发明提供了一种新的高迁移率沟道堆叠纳米线或片环栅器件结构，具体地，在硅衬底上方，且在堆叠纳米线或片下方的凹口结构内形成有氧化物进行隔离，可以确保硅基沟道，或，Ge等高迁移率沟道在保持高性能的条件下降低漏电流，从而改善器件特性；同时，本发明还提供了一种堆叠纳米线或片环栅器件的制备方法。
本发明所述的堆叠纳米线或片环栅器件，如图15至图18所示，包括：硅衬底1；
堆叠纳米线或片，堆叠纳米线或片形成在硅衬底1上方，且沿第一方向延伸，堆叠纳米线或片包括若干上下层叠的纳米线或片；
栅堆叠，栅堆叠包围每个堆叠纳米线或片，且沿第二方向延伸，栅堆叠沿第一方向两侧的侧壁上形成有第一侧墙9；
源/漏区，源/漏区位于每个栅堆叠沿第一方向的两侧；
沟道区13，沟道区13包括位于第一侧墙9之间的堆叠纳米线或片；
其中，堆叠纳米线或片与硅衬底1之间具有向内凹入的凹口结构6，凹口结构6内形成有隔离物，隔离物能够将堆叠纳米线或片与硅衬底1隔离。
本实施例中，在平行于衬底所在平面内，凹口结构6可以为沿垂直于堆叠纳米线或片延伸的方向，在堆叠纳米线或片和硅衬底1之间，形成的由两侧向内凹入的对称结构；当然，也可以为非对称结构；栅堆叠包括：栅极介质层14，以及位于栅极介质层14上的栅极15。
进一步地，隔离物为氧化物8。
本实施例中，隔离物为氧化物8，对形成的凹口结构6进行氧化处理，以在凹口结构6上形成氧化物8，即将凹口结构6进行氧化夹断；具体地，可以将凹口结构6整体氧化形成氧化物8，也可仅将凹口结构6中宽度较小的部分氧化形成氧化物8，其中，氧化物8的夹断高度应大于3nm，才能将堆叠纳米线或片和硅衬底1隔离，优选地，氧化物8的夹断高度为10nm。
进一步地，堆叠纳米线或片为Si1-yGey；其中，0≤y≤1。
本实施例中，堆叠纳米线或片为Si1-yGey，当y等于0时，堆叠纳米线或片的制备材料为Si；当y等于1时，堆叠纳米线或片的制备材料为Ge，当y大于0且小于1时，堆叠纳米线或片为具有一定Ge浓度的SiGe，即沟道区13可以为硅基沟道，也可以为Ge等高迁移率材料沟道。
进一步地，硅衬底1与凹口结构6之间，或，硅衬底1与凹口结构6之间以及栅堆叠与凹口结构6之间具有硅刻蚀结构。
本实施例中，在制备半导体器件过程中，未在硅衬底1上形成应变缓冲层10，在后续形成的半导体器件中，若刻蚀凹口结构6后，又继续向下硅衬底1，则会在凹口结构6的上方和凹口结构6的下方，存在由刻蚀硅衬底1后形成的硅刻蚀结构；如图15所示，若在后续进行释放时，未去除掉凹口结构6上方的硅刻蚀结构，则会在硅衬底1与凹口结构6之间以及栅堆叠与凹口结构6之间均保留硅刻蚀结构；
如图16所示，若在后续进行释放时，去除牺牲层2且一并去除掉凹口结构6上方的硅刻蚀结构，则仅会在硅衬底1与凹口结构6之间保留硅刻蚀结构。
进一步地，硅衬底1与凹口结构6之间，或，硅衬底1与凹口结构6之间以及栅堆叠与凹口结构6之间具有应变缓冲结构；其中，应变缓冲结构为Si1-zGez，0≤z≤0.8。
本实施例中，在制备半导体器件过程中，在硅衬底1上形成了应变缓冲层10，在后续形成的半导体器件中，若刻蚀应变缓冲层10形成凹口结构6后，又继续向下应变缓冲层10，则会在凹口结构6的上方和凹口结构6的下方，存在由刻蚀应变缓冲层10后形成的应变缓冲结构；如图17所示，若在后续进行释放时，未去除掉凹口结构6上方的应变缓冲结构，则会在硅衬底1与凹口结构6之间以及栅堆叠与凹口结构6之间均保留应变缓冲结构；
如图18所示，若在后续进行释放时，去除牺牲层2且一并去除掉凹口结构6上方的应变缓冲结构，则仅会在硅衬底1与凹口结构6之间保留应变缓冲结构。
需要说明的是，无论是通过刻蚀硅衬底1，还是通过刻蚀应变缓冲层10的方式，在形成凹口结构6后，均可以不再继续向下刻蚀硅衬底1或应变缓冲层10，这样，不会在硅衬底1和凹口结构6之间形成对应的硅刻蚀结构或应变缓冲结构。
采用上述技术方案，在硅衬底1上方，且在堆叠纳米线或片下方的凹口结构6内具有氧化物8进行隔离，可以确保硅基沟道，或，Ge等高迁移率沟道在保持高性能的条件下降低漏电流，从而改善器件特性。
同时，本发明还提供一种堆叠纳米线或片环栅器件的制备方法，如图19所示，包括以下步骤：
S1、如图1所示，提供硅衬底1，并在硅衬底1上形成交替堆叠的牺牲层2和材料层3；
本步骤中，可以采用减压外延或分子束外延工艺，现在硅衬底1上外延生长一层牺牲层2，然后在牺牲层2上外延生长一层材料层3，根据具体工况，还可以在硅衬底1上外延两层或多层，由牺牲层2和材料层3交替堆叠的叠层，优选叠层的层数为两层或三层；其中，具体地，材料层3为Si1-yGey，其层厚为8至25nm，优选地，材料层3的层厚为10至20nm；牺牲层2为Si1- xGex，其层厚为5至25nm，其中，0≤y≤1，0≤x≤0.8，优选地，x的取值范围为0≤x≤0.7。
进一步地，牺牲层2的层数可与材料层3的层数相等，还可以为，牺牲层2的层数可与材料层3的层数多一层，即在顶层材料层3上再形成一层牺牲层2，这样可在后续处理过程中，保护沟道区13不受刻蚀、清洗等工艺的影响。
在其他可选实施例中，如图2所示，在硅衬底1上形成交替堆叠的牺牲层2和材料层3前，在硅衬底1上形成应变缓冲层10，以为沟道区13提供应力；其中，应变缓冲层10为Si1- zGez，0≤z≤0.8，层厚为0.5至3.5μm；同时，为方便后续操作，在应变缓冲层10外延生长后，采用化学机械抛光等工艺对其进行平坦化，改善其表面的粗糙度；具体地，应变缓冲层10中Ge的浓度可以为均匀分布，还可以是越远离硅衬底1，Ge的浓度越高，优选地，Ge的厚度每增加1μm，应变缓冲层10中Ge的浓度增加10%。
S2、沿第一方向，在硅衬底1上形成若干第一鳍部4，以及位于若干第一鳍部4上的若干第二鳍部5；
本步骤中，如图3所示，若未在硅衬底1上形成应变缓冲层10，则可以采用干法各向异性刻蚀材料层3、牺牲层2和硅衬底1，对应形成若干第一鳍部4，以及位于若干第一鳍部4上的若干第二鳍部5；具体地，第一鳍部4是刻蚀硅衬底1形成的突出结构部分，第二鳍部5是刻蚀牺牲层2和材料层3形成的突出结构部分；
如图4所示，若在硅衬底1上形成交替堆叠的牺牲层2和材料层3前，在硅衬底1上形成了应变缓冲层10，则可以采用干法各向异性刻蚀材料层3、牺牲层2和应变缓冲层10，对应形成若干第一鳍部4，以及位于若干第一鳍部4上的若干第二鳍部5；具体地，第一鳍部4是刻蚀应变缓冲层10形成的突出结构部分，第二鳍部5是刻蚀牺牲层2和材料层3形成的突出结构部分。
S3、在硅衬底1上形成凹口结构6；
其中，具体地，在硅衬底1上形成凹口结构6的步骤包括：
S311、对若干第一鳍部4和第二鳍部5进行O2等离子体钝化处理；
本步骤中，对若干第一鳍部4和第二鳍部5进行O2等离子体钝化处理，以在第一鳍部4和第二鳍部5的外侧形成保护层，避免后续刻蚀凹口结构6时，损伤第一鳍部4和第二鳍部5。
S312、采用偏各向同性刻蚀工艺，在硅衬底1上形成凹口结构6。
本步骤中，如图5所示，若未在硅衬底1上形成应变缓冲层10，则采用偏各向同性刻蚀工艺，向下刻蚀硅衬底1，以在硅衬底1上形成凹口结构6；如图6所示，若在硅衬底1上形成交替堆叠的牺牲层2和材料层3前，在硅衬底1上形成了应变缓冲层10，则采用偏各向同性刻蚀工艺，向下刻蚀应变缓冲层10，以形成凹口结构6；待凹口结构6形成后，可以采用HF溶液去除因刻蚀牺牲层2和材料层3沉积在第二鳍部5顶部的硬掩膜。
在其他可选实施例中，在硅衬底1上形成凹口结构6的步骤还可以为：
S321、如图9所示，在若干第一鳍部4和第二鳍部5沿第一方向和第二方向的侧壁上形成第二侧墙11；
本步骤中，在若干第一鳍部4和第二鳍部5沿第一方向和第二方向的侧壁上形成第二侧墙11，避免后续刻蚀凹口结构6时，损伤第一鳍部4和第二鳍部5，具体地，在已形成的结构上沉积第二侧墙材料，并通过各向异性刻蚀工艺形成第二侧墙11，优选地，第二侧墙11的材料为SiN，形成后第二侧墙11底部的宽度范围为5至20nm。
S322、采用偏各向同性刻蚀工艺，在硅衬底1上形成凹口结构6。
本步骤中，如图10和图11所示，采用偏各向同性刻蚀工艺，在硅衬底1上形成凹口结构6的具体操作，与步骤S312中大致相同，在此不再赘述，不同的是，采用本步骤形成凹口结构6后，需要去除第一鳍部4和第二鳍部5侧壁上的第二侧墙11；具体地，可以通过H3PO4溶液高选择比的去除掉位于第一鳍部4和第二鳍部5侧壁上，且材料为SiN的第二侧墙11。
进一步地，在其他可选实施例中，在硅衬底1上形成凹口结构6后，继续在硅衬底1上形成第三鳍部7：具体地，如图7所示，若未在硅衬底1上形成应变缓冲层10，则在刻蚀硅衬底1，并形成凹口结构6后，继续向下刻蚀硅衬底1，以形成第三鳍部7；如图8所示，若在硅衬底1上形成交替堆叠的牺牲层2和材料层3前，在硅衬底1上形成了应变缓冲层10，则在刻蚀应变缓冲层10，并形成凹口结构6后，继续向下刻蚀应变缓冲层10，以形成第三鳍部7。
需要说明的是，若需要在硅衬底1上形成第三鳍部7，则无论是步骤S312中，去除第二鳍部5顶部的硬掩膜；还是步骤S322中，去除第一鳍部4和第二鳍部5侧壁上的第二侧墙11，以及第二鳍部5顶部的硬掩膜，均须在形成第三鳍部7后进行，以避免第一鳍部4和第二鳍部5在刻蚀过程中损伤。
S4、在凹口结构6上形成隔离物，以将第一鳍部4和硅衬底1隔离；
其中，具体地，在凹口结构6上形成隔离物的步骤包括：
S41、在O2基气氛中，对第一鳍部4、第二鳍部5、凹口结构6和第三鳍部7进行氧化处理；
S42、循环上述操作若干次，在凹口结构6内形成隔离物，以将第一鳍部4和硅衬底1隔离，形成的具体结构参见图12。
步骤S41和步骤S42中，氧化处理的氧化温度可为600至900℃，氧化时间可为30至60s，在这样的氧化处理条件下，循环步骤S41和步骤S42 中的操作1至5次，即可在第一鳍部4和硅衬底1之间形成隔离物；具体地，氧化温度、氧化时间和循环次数，可根据具体情况设置，只要可将第一鳍部4和硅衬底1通过之间的隔离物进行完全隔离即可。
需要说明的是，若在步骤S312或S322之后，并在步骤S4之前，未在硅衬底1上形成第三鳍部7，则步骤S41，需要改为仅在O2基气氛中，对第一鳍部4、第二鳍部5和凹口结构6进行氧化处理。
进一步地，如图13所示，在若干第三鳍部7，或，若干第一鳍部4之间的沟槽内淀积浅槽隔离12，并对浅槽隔离12进行平坦化和腐蚀处理；具体地，浅槽隔离12的材料可为SiN、Si3N4、SiO2或SiCO，其沉积的厚度应足以埋入突出的第二鳍部5，可以采用化学机械抛光等工艺对其进行平坦化，直至露出第二鳍部5的顶部，之后可以采用HF溶液对其进行腐蚀处理，以露出全部高度的第二鳍部5，以方便进行后续替代栅处理。
S5、沿第二方向，在若干第一鳍部4和第二鳍部5上形成牺牲栅，以及牺牲栅两侧的第一侧墙9；
本步骤中，在若干第一鳍部4和第二鳍部5上沉积牺牲栅的栅极材料，其中，栅极材料可以为多晶硅；然后可以采用湿法刻蚀或干法刻蚀工艺，刻蚀栅极材料形成牺牲栅；再沉积第一侧墙9的第一侧墙材料，之后可以采用湿法刻蚀或干法刻蚀工艺，刻蚀第一侧墙材料形成第一侧墙9。
S6、在第一侧墙9两侧的第二鳍部5，或，第一鳍部4和第二鳍部5，上刻蚀并生长源漏外延层，形成源/漏区；
本步骤中，先刻蚀牺牲栅两侧的第二鳍部5，或，第一鳍部4和第二鳍部5，形成凹陷区；再在牺牲栅两侧的凹陷区内生长源漏区材料，形成源/漏区。
S7、进行替代栅处理，形成堆叠纳米线或片环栅器件。
其中，具体地，进行替代栅处理的步骤包括：
S71、在已形成的结构上沉积氧化介质层，并对氧化介质层进行平坦化处理；
本步骤中，在已形成的结构上沉积一层氧化介质层，氧化介质层的材料可为SiO2，其厚度应足以埋入突出的牺牲栅，沉积之后，在对其进行平坦化处理，以露出牺牲栅的顶部。
S72、去除牺牲栅；并去除栅极区域内的牺牲层2，或，牺牲层2和第一鳍部4，形成沟道区13；
本步骤中，可以采用干法或湿法刻蚀工艺去除掉栅极区域内的牺牲栅，形成的具体结构参见图14，去除牺牲栅后，露出了栅极区域内由牺牲层2和材料层3交替构成的叠层，以及第一鳍部4的顶部；如图16和图18所示，可高选择比地去除露出的牺牲层2，这样会在栅极区域内保留与牺牲层2制备材料不同的第一鳍部4；如图15和图17所示，还可以无选择比的去除牺牲层2和第一鳍部4，以释放出沟道区13。
需要说明的是，图12至图14仅示出了未在硅衬底1上形成应变缓冲层10情况下，对应的形成隔离物至去除掉牺牲栅步骤的示意图，不代表仅可以在不含应变缓冲层10的情况下实现，形成隔离物至去除掉牺牲栅的步骤也可在含有应变缓冲层10的情况下实现。
S73、在沟道区13上依次形成栅极介质层14和栅极15。
本步骤中，可通过原子层沉积等工艺，在沟道区13上沉积一层栅极介质层14，其中，优选地，栅极介质层14为高介电常数层，具体地，高介电常数层可HfO2（二氧化铪）、ZrO2（二氧化锆）、TiO2（二氧化钛）或Al2O3（三氧化二铝）等介电常数较高的材料，沉积之后，并在栅极介质层14上形成栅极15，其中，栅极15可为TaN（氮化钽）、TiN(氮化钛)、TiAlC（碳铝钛）等满足要求的任意一种或几种物质的叠层；其中，栅极介质层14和栅极15的层厚可根据具体情况设置。
综上所述，本发明提供的堆叠纳米线或片环栅器件的制备方法，同样具有可将硅基沟道，或，Ge等高迁移率沟道，通过其下方凹口结构6内的氧化物8，与硅衬底1进行隔离，在保持高性能的条件下降低漏电流的优点。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

1.一种堆叠纳米线或片环栅器件，其特征在于，包括：硅衬底；
堆叠纳米线或片，所述堆叠纳米线或片形成在所述硅衬底上方，且沿第一方向延伸，所述堆叠纳米线或片包括若干上下层叠的纳米线或片；
栅堆叠，所述栅堆叠包围每个所述堆叠纳米线或片，且沿第二方向延伸，所述栅堆叠沿第一方向两侧的侧壁上形成有第一侧墙；
源/漏区，所述源/漏区位于每个栅堆叠沿第一方向的两侧；
沟道区，所述沟道区包括位于所述第一侧墙之间的堆叠纳米线或片；
其中，所述堆叠纳米线或片与硅衬底之间具有向内凹入的凹口结构，所述凹口结构内形成有隔离物，所述隔离物能够将所述堆叠纳米线或片与硅衬底隔离。
2.根据权利要求1所述的堆叠纳米线或片环栅器件，其特征在于，所述隔离物为氧化物。
3.根据权利要求1所述的堆叠纳米线或片环栅器件，其特征在于，所述堆叠纳米线或片为Si1-yGey；其中，0≤y≤1。
4.根据权利要求1所述的堆叠纳米线或片环栅器件，其特征在于，所述硅衬底与凹口结构之间，或，所述硅衬底与凹口结构之间以及所述栅堆叠与凹口结构之间具有硅刻蚀结构。
5.根据权利要求1所述的堆叠纳米线或片环栅器件，其特征在于，所述硅衬底与凹口结构之间，或，所述硅衬底与凹口结构之间以及所述栅堆叠与凹口结构之间具有应变缓冲结构；其中，所述应变缓冲结构为Si1-zGez，0≤z≤0.8。
6.一种堆叠纳米线或片环栅器件的制备方法，其特征在于，包括以下步骤：
提供硅衬底，并在所述硅衬底上形成交替堆叠的牺牲层和材料层；
沿第一方向，在所述硅衬底上形成若干第一鳍部，以及位于若干所述第一鳍部上的若干第二鳍部；
在所述硅衬底上形成凹口结构；
在所述凹口结构上形成隔离物，以将所述第一鳍部和所述硅衬底隔离；
沿第二方向，在若干所述第一鳍部和第二鳍部上形成牺牲栅，以及所述牺牲栅两侧的第一侧墙；
在所述第一侧墙两侧的第二鳍部，或，所述第二鳍部和第一鳍部上刻蚀并生长源漏外延层，形成源/漏区；
进行替代栅处理，形成堆叠纳米线或片环栅器件。
7.根据权利要求6所述的堆叠纳米线或片环栅器件的制备方法，其特征在于，在所述硅衬底上形成交替堆叠的牺牲层和材料层前，在所述硅衬底上形成应变缓冲层，其中，所述应变缓冲层为Si1-zGez，0≤z≤0.8，层厚为0.5至3.5μm。
8.根据权利要求6或7所述的堆叠纳米线或片环栅器件的制备方法，其特征在于，在所述硅衬底上形成所述凹口结构的步骤包括：
对若干所述第一鳍部和第二鳍部进行O2等离子体钝化处理；
采用偏各向同性刻蚀工艺，在所述硅衬底上形成所述凹口结构。
9.根据权利要求6或7所述的堆叠纳米线或片环栅器件的制备方法，其特征在于，在所述硅衬底上形成所述凹口结构的步骤包括：
在若干所述第一鳍部和第二鳍部沿第一方向和第二方向的侧壁上形成第二侧墙；
采用偏各向同性刻蚀工艺，在所述硅衬底上形成所述凹口结构。
10.根据权利要求6或7所述的堆叠纳米线或片环栅器件的制备方法，其特征在于，在所述硅衬底上形成所述凹口结构后，并在所述凹口结构上形成所述隔离物前，在所述硅衬底上形成第三鳍部。
11.根据权利要求10所述的堆叠纳米线或片环栅器件的制备方法，其特征在于，在所述凹口结构上形成所述隔离物的步骤包括：
在O2基气氛中，对所述第一鳍部、第二鳍部、凹口结构和第三鳍部进行氧化处理；
循环上述操作若干次，在所述凹口结构上形成隔离物，以将所述第一鳍部和硅衬底隔离。
12.根据权利要求11所述的堆叠纳米线或片环栅器件的制备方法，其特征在于，所述氧化处理的氧化温度为600至900℃，氧化时间为30至60s，循环次数为1至5次。
13.根据权利要求6所述的堆叠纳米线或片环栅器件的制备方法，其特征在于，进行所述替代栅处理的步骤包括：
在已形成的结构上沉积氧化介质层，并对所述氧化介质层进行平坦化处理；
去除所述牺牲栅；并去除所述栅极区域内的牺牲层，或，牺牲层和第一鳍部，形成沟道区；
在所述沟道区上依次形成栅极介质层和栅极。
14.根据权利要求6所述的堆叠纳米线或片环栅器件的制备方法，其特征在于，所述材料层为Si1-yGey，层厚为8至25nm；所述牺牲层为Si1-xGex，层厚为5至25nm；其中，0≤y≤1，0≤x≤0.8。
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