CN111308935A

CN111308935A - Automatic testing device and method for priority management product

Info

Publication number: CN111308935A
Application number: CN202010125492.2A
Authority: CN
Inventors: 段长亮; 孙永滨; 许先音; 曹宗生
Original assignee: China Techenergy Co Ltd
Current assignee: China Techenergy Co Ltd
Priority date: 2020-02-27
Filing date: 2020-02-27
Publication date: 2020-06-19
Anticipated expiration: 2040-02-27
Also published as: CN111308935B

Abstract

The invention relates to an automatic testing device and method for a priority management product, belongs to the field of automatic testing, and solves the problems of long testing time and low efficiency in the prior art. The device comprises an upper computer and at least one lower computer; the upper computer is used for setting truth table instructions, outputting the truth table instructions to the lower computer and controlling the lower computer to test; and the lower computer is used for obtaining an input logic truth table and an output logic truth table according to the set truth table instruction, generating a plurality of test cases, sequentially outputting input logic values in the test cases to an input channel of the tested product according to a preset time interval, sequentially collecting output logic values of an output channel of the tested product, comparing the output logic values with corresponding output logic values in the test cases, obtaining an optimal logic state of the tested product, and uploading the optimal logic state to the upper computer. The device can test the product priority automatically, and test time is short, has improved efficiency of software testing.

Description

Automatic testing device and method for priority management product

Technical Field

The invention relates to the technical field of automatic testing, in particular to a device and a method for automatically testing priority management products.

Background

Aiming at the test and verification of the input and output logics of the priority management product, the traditional method is realized by adopting a universal standard control board card and combining with the software programming of an upper computer. The method comprises the steps of respectively injecting all test cases, namely all input logic combinations and all output logic combinations into a lower computer control board card one by one through upper computer software programming, then outputting corresponding input logic values through corresponding DO channels of the control board card, injecting the corresponding input logic values into an input channel of a tested product, simultaneously acquiring the logic state of the preferred output channel of the tested product by using a DI acquisition channel of the control board card, sending the logic state to an upper computer, and judging the correctness of the input logic state and the output logic state of the tested product by using the upper computer.

The prior art has the following defects that firstly, all test cases are injected into a lower computer by adopting the software programming of the upper computer, the realization mode is complex, and the programming development of a test device is difficult; secondly, when the test is executed, all test cases need to be manually generated, so that the preparation time of the test cases is long, and the efficiency is low.

Disclosure of Invention

In view of the above analysis, the present invention provides an automatic testing apparatus and method for priority management products, so as to solve the problems of complex testing method, long time consumption and low efficiency of the existing priority management products.

In one aspect, the invention provides an automatic testing device for priority management products, which is characterized by comprising an upper computer and at least one lower computer; the upper computer is used for setting a truth table instruction, outputting the truth table instruction to the lower computer and controlling the lower computer to test; the lower computer is used for obtaining an input logic truth table and an output logic truth table according to a set truth table instruction, the input logic truth table and the output logic truth table comprise a plurality of groups of input logic values and corresponding output logic values, and each group of input logic values and corresponding output logic values generate a test case; and the lower computer is also used for sequentially outputting the input logic values in the test cases to the input channel of the tested product according to a preset time interval, sequentially acquiring the output logic values of the output channel of the tested product, comparing the output logic values with the output logic values in the corresponding test cases to obtain the optimal logic state of the tested product, and uploading the optimal logic state to the upper computer.

Furthermore, the upper computer is connected with a plurality of lower computers in a cascading mode to realize multichannel expansion.

Further, the set truth table instruction comprises a truth table input type parameter, an input channel parameter and an input and output logic relationship table, and the truth table input type comprises digital quantity input, serial port input and network port input.

Further, the lower computer comprises a main processing module, an output module and an acquisition module; the main processing module comprises an FPGA chip and an Ethernet interface chip;

the FPGA chip is connected with the upper computer through an Ethernet interface chip, receives a truth table instruction output by the upper computer, scans and expands the set input and output logic relation table and supplements irrelevant logic item information to obtain an input and output logic truth table, and further generates a plurality of test cases;

the FPGA chip is also used for inputting input logic values in a plurality of test cases corresponding to the set truth table input type to the corresponding output channel in the output module at preset time intervals according to the truth table input type parameters and the input channel parameters, and then inputting the input logic values to the input channel of the tested product;

the FPGA chip is also used for receiving the output logic values of the output channels of the tested products sequentially acquired by the acquisition module, comparing the output logic values with the output logic values in the corresponding test cases, obtaining the optimal logic state of the tested products and uploading the optimal logic state to the upper computer.

Further, the output module includes a DO output module, a serial port communication module, and an ethernet communication module, and each of the output modules includes at least two output channels for outputting an input logic value in the test case corresponding to the truth table input type.

Furthermore, each channel of the DO output module comprises an optical coupling isolation circuit, a driving circuit and an electromagnetic relay;

the optical coupling isolator is used for receiving a level signal which is output by the FPGA chip and corresponds to an input logic value and converting the level signal into a corresponding voltage signal;

the driving circuit is used for receiving the voltage signal and generating corresponding driving current so as to control the opening and closing of the electromagnetic relay;

furthermore, each output channel of the serial port communication module comprises an RS485 bus interface, a CAN bus interface and a program control switching circuit;

the input ends of the RS485 bus interface and the CAN bus interface are connected with the output end of the FPGA chip and used for receiving an input logic value data packet which is output by the FPGA chip and accords with a serial port communication protocol of a tested product and outputting the input logic value data packet to an input channel of the tested product;

the program-controlled switching circuit comprises a controller and two first signal relays and two second signal relays which are connected in parallel, wherein the input ends of the first signal relays and the second signal relays are respectively connected with the output ends of an RS485 bus interface and a CAN bus interface, and the opening and closing of the first signal relays and the second signal relays are controlled through truth table input type parameters received by the controller, so that the input logic value data packets corresponding to the truth table input type parameters are selected and output from the other ends of the first signal relays or the second signal relays.

Furthermore, each output channel of the ethernet communication module includes an ethernet physical layer, a data link layer chip and a network transformer;

the input ends of the Ethernet physical layer and the data link layer chip are connected with the output end of the FPGA chip and used for receiving an input logic value data packet which is output by the FPGA chip and accords with an Ethernet communication protocol of a tested product and outputting the input logic value data packet to an input channel of the tested product;

the network transformer is used for providing electrical isolation protection for the Ethernet physical layer chip and the data link layer chip.

Furthermore, the output end of the output channel of the tested product is connected with the input end of the corresponding acquisition channel in the acquisition module, each acquisition channel of the acquisition module comprises an optical coupling isolation circuit, and the optical coupling isolation circuit is used for converting the 24V/48V logic level signal output by the tested product into an LVTTL level signal and outputting the LVTTL level signal to the FPGA chip.

According to the technical scheme, the invention has the following beneficial effects:

1. the invention adopts the FPGA chip to automatically generate a plurality of test cases to be injected into the input channel of the tested product, and judges the optimal logic state, the realization mode is simple, and the development difficulty of the testing device is reduced;

2. according to the invention, the FPGA chip is adopted to automatically generate a plurality of tests, so that the problems of long test case preparation time and low efficiency caused by manual generation of all test cases are solved;

3. the upper computer and the lower computer are designed in a distributed mode, the device can be conveniently unfolded on a test site, the acquisition cascade mode is connected with the lower computers to realize the expansion of channels, and the priority logic states of a plurality of products can be measured simultaneously.

On the other hand, the invention provides an automatic test method for a priority management product, which comprises the following steps:

setting a truth table instruction, wherein the set truth table instruction comprises a truth table input type parameter, an input channel parameter and an input and output logic relation table, and the truth table input type comprises digital quantity input, serial port input and network port input;

scanning and expanding the set input and output logic relation table according to a set truth table instruction and supplementing irrelevant logic item information to obtain an input and output logic truth table, wherein the input and output logic truth table comprises a plurality of groups of input logic values and corresponding output logic values, and each group of input logic values and corresponding output logic values generate a test case;

inputting input logic values in a plurality of test cases corresponding to the set truth table input type to the corresponding output channel at preset time intervals according to the truth table input type parameters and the input channel parameters, and further inputting the input logic values to the input channel of the tested product;

and acquiring the output logic value of the output channel of the tested product, comparing the output logic value with the output logic value in the corresponding test case to obtain the optimal logic state of the tested product, and uploading the optimal logic state to an upper computer.

The automatic test method of the priority management product in the invention has the same principle as the automatic test device of the priority management product, so the method also has the technical effect corresponding to the device.

In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.

FIG. 1 is a diagram illustrating an automatic testing apparatus for priority management products according to an embodiment of the present invention;

FIG. 2 is a flow chart of a method for automatically testing a priority management product according to an embodiment of the present invention;

fig. 3 is a schematic diagram of the lower computer module according to the embodiment of the present invention;

FIG. 4 is a schematic diagram of a main processing module according to an embodiment of the present invention;

FIG. 5 is a diagram of a DO output module according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of an optical coupling isolation circuit and a driving circuit in a DO output module according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a serial communication module according to an embodiment of the present invention;

fig. 8 is a schematic diagram of an ethernet communication module according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of an acquisition module according to an embodiment of the present invention;

fig. 10 is a schematic diagram of an optical coupling and isolating circuit in an acquisition module according to an embodiment of the present invention.

Detailed Description

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.

Device embodiment

The invention discloses an automatic testing device for priority management products. As shown in fig. 1, the apparatus includes an upper computer and at least one lower computer; the upper computer is used for setting a truth table instruction, outputting the truth table instruction to the lower computer and controlling the lower computer to test; the lower computer is used for obtaining an input logic truth table and an output logic truth table according to a set truth table instruction, the input logic truth table and the output logic truth table comprise a plurality of groups of input logic values and corresponding output logic values, and each group of input logic values and corresponding output logic values generate a test case; and the lower computer is also used for sequentially outputting the input logic values in the test cases to the input channel of the tested product according to a preset time interval, sequentially acquiring the output logic values of the output channel of the tested product, comparing the output logic values with the output logic values in the corresponding test cases to obtain the optimal logic state of the tested product, and uploading the optimal logic state to the upper computer.

Preferably, the upper computer is connected with the plurality of lower computers in a cascading mode to realize multichannel expansion, and the multichannel expansion measuring device can be used for measuring the optimal logic states of a plurality of products simultaneously.

Specifically, the set truth table instruction comprises a truth table input type parameter, an input channel parameter and an input and output logic relationship table, and the truth table input type comprises digital quantity input, serial port input and network port input.

Specifically, when the tested product comprises an input instruction for inputting digital quantity, setting the truth table input type as digital quantity input; when the tested product comprises an input instruction input through serial port communication, setting the truth table input type as serial port input; when the tested product comprises an input command input through Ethernet communication, the truth table input type is set as the network port input.

Preferably, as shown in fig. 3, the lower computer includes a main processing module, an output module, an acquisition module, and a power management module; as shown in fig. 4, the main processing module includes an FPGA chip and an ethernet interface chip, and specifically, the FPGA chip adopts an EP4CE22F17I7N chip.

The FPGA chip is connected with the upper computer through an Ethernet interface chip, receives a truth table instruction output by the upper computer, scans and expands the set input and output logic relation table and supplements irrelevant logic item information to obtain an input and output logic truth table, and further generates a plurality of test cases; the upper computer and the lower computer adopt 100M TCP/IP protocol Ethernet communication.

Wherein, the input and output logic relation table includes irrelevant logic items, exemplarily, the input and output logic relation table includes, as shown in table 1, input logic values corresponding to four output channels in the output module and output logic values corresponding to two acquisition channels in the acquisition module, X represents irrelevant logic items,

TABLE 1

The FPGA chip scans the input logic value in the output module first, and the input logic value corresponding to the scan output channel 1 is a determined logic value "1", as shown in table 2:

TABLE 2

Channel 4	Channel 3	Channel 2	Channel 1
				？	？	？	1

Then continuing to scan channel 2, determining that the input logical value for channel 2 is the extraneous logical item "X", then unrolling the extraneous item, as shown in Table 3:

TABLE 3

Channel 4	Channel 3	Channel 2	Channel 1
				？	？	0	1
？	？	1	1

Then continuing to scan channel 3, determining that the input logic value of channel 3 is the extraneous item "X", then unrolling the extraneous item, as shown in Table 4:

TABLE 4

Channel 4	Channel 3	Channel 2	Channel 1
				？	0	0	1
？	0	1	1
				？	1	0	1
？	1	1	1

Then, the channel 4 is scanned continuously, and if the input logic value of the channel 4 is determined to be "1", the expansion process is not performed, as shown in table 5:

TABLE 5

Channel 4	Channel 3	Channel 2	Channel 1
				1	0	0	1
1	0	1	1
				1	1	0	1
1	1	1	1

And scanning the output logic values in the same mode to obtain a complete input and output logic truth table. As known to those skilled in the art, there are no extraneous logic terms in the output logic value.

the FPGA chip is also used for receiving output logic values of the output channels of the tested products sequentially acquired by the acquisition module, comparing the output logic values with output logic values in corresponding test cases, judging whether the output logic values are consistent, if so, the preferred logic state of the tested products is qualified, and if not, the preferred logic state of the tested products is unqualified, and uploading the preferred logic values to an upper computer; preferably, after the input logic value is input into the input channel of the tested product and is delayed for 500ms, the acquisition module automatically acquires the output logic value of the output channel of the tested product.

The main processing module also comprises an EEPROM storage chip used for storing parameter configuration information, including lower computer network parameters and input and output channel parameters. For example, in order to realize network communication between an upper computer and a lower computer, ip addresses of the upper computer and the lower computer must be set first, and the ip addresses of the lower computer are stored in an EEPROM (electrically erasable programmable read-only memory) storage chip, so that the stored ip addresses of the lower computer can be automatically configured when the lower computer is powered on again, repeated setting is avoided, and operation is simplified; the input and output channel parameters are the number of input channels and the number of output channels contained in the tested product.

For example, the truth table instruction output by the upper computer is shown in table 6, where the logic value of the input channel in the table includes 20 bytes, corresponding to the output channel in the 20 output modules, as shown in table 7; specifically, as shown in table 8, each byte includes 8 bits, with 0-3 bits identifying the input logic value and 4-7 bits identifying the truth table input type parameter; similarly, the theoretical output logic value in table 6 includes 4 bytes corresponding to 4 acquisition channels in the acquisition module, as shown in table 7; specifically, as shown in table 9, each byte includes 8 bits, 0-3 bits identify the output logic value, and 4-7 bits are undefined; namely, the truth table instruction includes the truth table input type parameter, the input channel parameter and the input and output logic relationship table. The bytes included in the input channel logic value and the bytes of the theoretical output logic value may be set according to actual measurement requirements.

TABLE 6

TABLE 7

TABLE 8

TABLE 9

For example, the table of the logical relationship between input and output in the truth table command received by the lower computer is shown in table 10, the input portion A, B, C, D represents the input logical values corresponding to four output channels in the output module, the output portions Y1 and Y2 represent the output logical values corresponding to two output channels in the acquisition module, and X in the table represents an unrelated item; the lower computer scans and expands the input and output logic relation table in the received truth table instruction, and the input and output logic truth table obtained after supplementing irrelevant logic items is shown in table 11, wherein the input and output corresponding to the serial numbers 1-16 represent the generated 16 test cases.

Watch 10

TABLE 11

In order to meet different input requirements of a tested product, the output module comprises a DO output module, a serial port communication module and an Ethernet communication module, and the DO output module, the serial port communication module and the Ethernet communication module respectively comprise at least two output channels for outputting input logic values in test cases corresponding to truth table input types.

Preferably, when the product to be tested contains an input instruction of digital quantity input, the set input logic value is output through a DO output module, as shown in fig. 5, each channel of the DO output module includes an optical coupling isolation circuit, a driving circuit and an electromagnetic relay;

as shown in fig. 6, the optical coupling isolation circuit is configured to receive a level signal output by the FPGA chip and corresponding to an input logic value and convert the level signal into a corresponding voltage signal; illustratively, the optocoupler-isolation circuit receives a level signal of the LVTTL output by the FPGA chip, for example, a level signal of 3.3V, and obtains a voltage signal of 5V after conversion.

As shown in fig. 6, the driving circuit is configured to receive a voltage signal and generate a corresponding driving current, so as to control the opening and closing of the electromagnetic relay;

specifically, when the FPGA chip outputs a 3.3V level signal, the driving circuit generates a corresponding driving current to control the electromagnetic relay to be closed, an output input logic value is 1, when the level signal output by the FPGA chip is 0V, the driving circuit does not generate a corresponding driving current, the electromagnetic relay is disconnected, and an output input logic value is 0.

Preferably, when the tested product contains an input instruction input by the serial port, the set input logic value is output through the serial port communication module. Illustratively, the FPGA chip combines the input logic values into a data packet conforming to a serial communication protocol corresponding to the product to be tested, and then sends the data packet to an input channel of the product to be tested through a serial communication module.

For example, after receiving a truth table instruction issued by the upper computer, the lower computer determines, according to the truth table input type parameter, that a certain set of input logic values is transmitted to the product to be tested through the RS485 serial port output channel, and the input logic value is "1". The communication protocol of the RS485 serial bus input instruction of the product to be tested is shown in table 7:

TABLE 7

Initial symbol	Instruction logic state	CRC check value
			1byte	1byte	1byte

The input logic value instruction set according to the communication protocol of the RS485 serial bus input instruction of the product to be tested is shown in table 8:

TABLE 8

The FPGA chip encapsulates the instruction into a data packet with 2 bytes according to the communication protocol and sends the data packet to a tested product through a serial port. The byte corresponding to the "input logic value" command in the data packet is "0000 _ 0010".

As shown in fig. 7, each output channel of the serial port communication module includes an RS485 bus interface, a CAN bus interface, and a program control switching circuit;

Preferably, when the tested product contains an input command of the ethernet input, the set input logic value is output through the ethernet communication module. Illustratively, the FPGA chip combines the input logic values into a data packet conforming to an ethernet communication protocol corresponding to the product to be tested, and then sends the data packet to an input channel of the product to be tested through an ethernet communication module; specifically, the input logic value instruction is determined, corresponding bytes are set according to the Ethernet communication protocol of the product to be tested, and the set bytes corresponding to the input logic value are packaged into a data packet.

As shown in fig. 8, each output channel of the ethernet communication module includes an ethernet physical layer and data link layer chip and a network transformer; the Ethernet physical layer chip and the data link layer chip support the custom protocol communication based on the data link layer, thereby providing corresponding interface support for the custom communication protocol of the tested product.

Preferably, the output end of the output channel of the tested product is connected with the input end of the corresponding acquisition channel in the acquisition module, as shown in fig. 9, each acquisition channel of the acquisition module includes an optical coupling isolation circuit. As shown in fig. 10, the optical coupler isolation circuit is configured to convert a 24V/48V logic level signal output by a product to be tested into an LVTTL level signal and output the LVTTL level signal to an FPGA chip, and the FPGA chip converts the received LVTTL level signal into a corresponding output logic value 0 or 1.

Compared with the prior art, the automatic test device for the priority management product, provided by the invention, has the advantages that firstly, the FPGA chip is adopted to automatically generate a plurality of test cases to be injected into the input channel of the tested product, and the optimal logic state is judged, so that the implementation mode is simple, and the development difficulty of the test device is reduced; secondly, a plurality of tests are automatically generated by adopting the FPGA chip, so that the problems of long test case preparation time and low efficiency caused by manually generating all test cases are solved; and finally, the upper computer and the lower computer are designed in a distributed mode, so that the device can be conveniently unfolded on a test site, and the acquisition cascade mode is connected with a plurality of lower computers to realize the expansion of channels, so that the priority logic states of a plurality of products can be measured simultaneously.

Method embodiment

Another embodiment of the present invention discloses an automatic test method for priority management products, as shown in fig. 2, including the following steps:

and acquiring an output logic value of the output channel of the tested product, comparing the output logic value with the output logic value in the corresponding test case, judging whether the output logic value is consistent, if so, judging that the preferred logic state of the tested product is qualified, and if not, judging that the preferred logic state of the tested product is unqualified, and uploading the qualified logic value to an upper computer.

Preferably, after the input logic value is input into the input channel of the tested product and is delayed for 500ms, the acquisition module automatically acquires the output logic value of the output channel of the tested product.

Compared with the prior art, the automatic test method for the priority management product, provided by the invention, has the advantages that firstly, the FPGA chip is adopted to automatically generate a plurality of test cases to be injected into the input channel of the tested product, and the optimal logic state is judged, so that the implementation mode is simple, and the development difficulty of a test device is reduced; secondly, a plurality of tests are automatically generated by adopting the FPGA chip, so that the problems of long test case preparation time and low efficiency caused by manually generating all test cases are solved; and finally, the upper computer and the lower computer are designed in a distributed mode, and the plurality of lower computers are connected in a collecting cascade mode to realize the expansion of the channel, so that the priority logic states of a plurality of products can be measured simultaneously.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims

1. An automatic testing device for priority management products is characterized by comprising an upper computer and at least one lower computer;

the upper computer is used for setting a truth table instruction, outputting the truth table instruction to the lower computer and controlling the lower computer to test;

the lower computer is used for obtaining an input logic truth table and an output logic truth table according to a set truth table instruction, the input logic truth table and the output logic truth table comprise a plurality of groups of input logic values and corresponding output logic values, and each group of input logic values and corresponding output logic values generate a test case;

and the lower computer is also used for sequentially outputting the input logic values in the test cases to the input channel of the tested product according to a preset time interval, sequentially acquiring the output logic values of the output channel of the tested product, comparing the output logic values with the output logic values in the corresponding test cases to obtain the optimal logic state of the tested product, and uploading the optimal logic state to the upper computer.

2. The apparatus of claim 1, wherein the upper computer is connected to the plurality of lower computers in a cascade manner to implement multi-channel expansion.

3. The apparatus as claimed in claim 1 or 2, wherein the set truth table command includes truth table input type parameters including digital quantity input, serial port input and network port input, input channel parameters and input and output logic relation table.

4. The automated testing device of claim 3, wherein the lower computer comprises a main processing module, an output module and an acquisition module; the main processing module comprises an FPGA chip and an Ethernet interface chip;

the FPGA chip is also used for inputting an input logic value in a test case corresponding to the set truth table input type to a corresponding output channel in the output module at a preset time interval according to the truth table input type parameter and the input channel parameter, and further inputting the input logic value to an input channel of a tested product;

5. The apparatus of claim 4, wherein the output module comprises a DO output module, a serial communication module and an Ethernet communication module, each of which comprises at least two output channels for outputting the input logic values of the test cases corresponding to the truth table input types.

6. The automated testing device of claim 5, wherein each channel of said DO output module comprises an optical coupling isolation circuit, a driving circuit and an electromagnetic relay;

the driving circuit is used for receiving the voltage signal and generating corresponding driving current so as to control the opening and closing of the electromagnetic relay.

7. The automatic testing device of claim 5, wherein each output channel of the serial communication module comprises an RS485 bus interface, a CAN bus interface and a program control switching circuit;

8. The automated testing device of claim 5, wherein each output channel of the Ethernet communication module comprises an Ethernet physical layer and data link layer chip and a network transformer;

9. The automatic testing device of a priority management product according to any one of claims 4 to 8, wherein the output end of the output channel of the tested product is connected with the input end of the corresponding acquisition channel in the acquisition module, each acquisition channel of the acquisition module comprises an optical coupling isolation circuit, and the optical coupling isolation circuit is used for converting the 24V/48V logic level signal output by the tested product into an LVTTL level signal and outputting the LVTTL level signal to the FPGA chip.

10. An automatic test method for priority management products is characterized by comprising the following steps: