CN111292678B

CN111292678B - Display device and pixel circuit

Info

Publication number: CN111292678B
Application number: CN202010126033.6A
Authority: CN
Inventors: 赖柏君; 张玮轩; 陈勇志
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-07-30
Filing date: 2020-02-20
Publication date: 2021-11-30
Anticipated expiration: 2040-02-20
Also published as: TWI732254B; CN111292678A; TW202105353A

Abstract

The invention discloses a display device and a pixel circuit. The pixel circuit comprises a data updating unit and a light emitting unit coupled to the data updating unit. In a first stage of a frame display period, the light-emitting unit is reset and does not emit light, and the data updating unit transmits first pixel data updated in a previous frame display period to the light-emitting unit. In a second stage of a frame display period, the light-emitting unit emits light according to the first pixel data received in the first stage, and the data updating unit updates the stored first pixel data into a second pixel data for a next frame display period.

Description

Display device and pixel circuit

Technical Field

The invention relates to a display device and a pixel circuit.

Background

In the conventional display device, the pixel data is updated at the same time as the pixel unit displays the updated pixel data. However, when the frequency of updating the picture of the display device is reduced, this may cause the picture to be discontinuous, so that the viewer may have a poor experience.

In order to provide better experience for the viewer, it is necessary to improve the above problems.

Disclosure of Invention

The embodiment of the invention discloses a pixel circuit for a display device. The pixel circuit comprises a data updating unit and a light emitting unit coupled to the data updating unit. In a first stage of a frame display period, the light-emitting unit is reset and does not emit light, and the data updating unit transmits first pixel data updated in a previous frame display period to the light-emitting unit. In a second stage of a frame display period, the light-emitting unit emits light according to the first pixel data received in the first stage, and the data updating unit updates the stored first pixel data into a second pixel data for a next frame display period.

Another embodiment of the present invention discloses a display device including a plurality of the above pixel circuits.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments is made with reference to the accompanying drawings:

drawings

Fig. 1 shows a block diagram of a display device according to an embodiment of the invention.

Fig. 2 shows a block diagram of a pixel circuit according to an embodiment of the invention.

FIG. 3 shows a timing diagram of signals according to an embodiment of the invention.

Fig. 4 shows a block diagram of a pixel circuit according to another embodiment of the invention.

Fig. 5 shows a block diagram of a pixel circuit according to yet another embodiment of the invention.

Fig. 6 shows a block diagram of a pixel circuit according to yet another embodiment of the invention.

Description of reference numerals:

10: display device

DL 1-DLm: data line

SL1 to SLn: scanning line

P11-Pmn, 20, 40, 50, 60: pixel circuit

T1: a first transistor

T2: second transistor

T3: a third transistor

T4: a fourth transistor

T5: fifth transistor

T6: sixth transistor

T7: seventh transistor

T8: eighth transistor

T9: ninth transistor

T10: the tenth transistor

T11: eleventh transistor

T12: twelfth transistor

C1: first capacitor

C2: second capacitor

Detailed Description

Referring to fig. 1, fig. 1 is a block diagram illustrating a display device according to an embodiment of the invention. The display device 10 includes a plurality of scan lines SL 1-SLn, a plurality of data lines DL 1-DLm, and a plurality of pixel circuits P11-Pmn, wherein m and n are positive integers. The scan lines SL1 to SLn are interlaced with the data lines DL1 to DLm. Each pixel circuit Pij is coupled to one of the scan lines SLi and one of the data lines DLj, where i is 1, 2.

Referring to fig. 2, fig. 2 is a block diagram of a pixel circuit according to an embodiment of the invention. The present embodiment is described by taking the pixel circuit in the nth scan line (i.e., the scan line SLi, i ═ N) as an example, however, the pixel circuit 20 may be used to implement any of the pixel circuits P11 to Pmn in fig. 1. The pixel circuit 20 includes a data update unit 201 and a light emitting unit 203. The light emitting unit 203 is coupled to the data updating unit 201. The frame display period includes a first stage and a second stage. The frame display period is a time when the display device 10 displays a complete screen. In the first phase, the light emitting unit 203 resets a first pixel data currently displayed without emitting light, and the data updating unit 201 transmits a second pixel data stored during a previous frame display period to the light emitting unit 203. In the second phase, the light emitting unit 203 emits light according to the second pixel data, and the data updating unit 201 updates the stored second pixel data to a third pixel data. From the perspective of the display device 10, in the first phase of the current frame display period, the light-emitting units of all the pixel circuits P11-Pmn reset the pixel data without emitting light, and the data update units of all the pixel circuits P11-Pmn simultaneously transmit the second pixel data stored/updated in the previous frame display period to the light-emitting units (at this time, the display device 10 still does not display a second frame constituted by the second pixel data); in the second phase, the light emitting units of all the pixel circuits P11-Pmn emit light according to the second pixel data received in the first phase at the same time (the display device 10 displays a second frame constituted by the second pixel data), and the data updating units of all the pixel circuits P11-Pmn update the second pixel data to the third pixel data by scanning lines according to a set of scanning signals. In other words, the display screen change of the display device 10 during the frame display is a transition from the first screen composed of the first pixel data to the non-display to a transition from the non-display to the second screen composed of the second pixel data. It should be noted that since the conversion/update of the display screen is performed by all the pixel circuits to write/update the pixel data at the same time, the viewer does not visually experience the update one by one.

The circuit details of the data update unit 201 and the light emitting unit 203 will be further described below.

The data update unit 201 includes a first capacitor C1, a first transistor T1, a second transistor T2, and a third transistor T3. A first terminal of the first capacitor C1 is coupled to one of the data lines for receiving a data voltage Vdata. A first terminal of the first transistor T1 is coupled to a second terminal of the first capacitor C1. A second terminal of the first transistor T1 is coupled to a reference voltage Vref. A gate terminal of the first transistor T1 is for receiving a previous Scan signal Scan [ N-1 ]. A first terminal of the second transistor T2 is coupled to the second terminal of the first capacitor C1. A gate terminal of the second transistor T2 is for receiving a current Scan signal Scan [ N ]. A first terminal of the third transistor T3 is coupled to a first voltage OVDD. A second terminal of the third transistor T3 is coupled to a second terminal of the second transistor T2. A gate terminal of the third transistor T3 is coupled to the second terminal of the first capacitor C1.

The light emitting unit 203 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a second capacitor C2, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a light emitting device D. A first terminal of the fourth transistor T4 is coupled to the second terminal of the second transistor T2. A gate terminal of the fourth transistor T4 is for receiving a first control signal EM 1. A first terminal of the fifth transistor T5 is for receiving the data voltage Vdata. A second terminal and a gate terminal of the fifth transistor are coupled to a second terminal of the fourth transistor T4. A first terminal of the sixth transistor T6 is coupled to the first voltage OVDD. A second terminal of the sixth transistor T6 is coupled to the second terminal of the fourth transistor T4. A gate terminal of the sixth transistor T6 is for receiving a second control signal EM 2. A first terminal of the second capacitor C2 is coupled to the second terminal of the fourth transistor T4. A first terminal of the seventh transistor T7 is coupled to the second terminal of the fourth transistor T4. A gate terminal of the seventh transistor T7 is coupled to a second terminal of the second capacitor C2. A first terminal of the eighth transistor T8 is coupled to the second terminal of the second capacitor C2. A second terminal of the eighth transistor T8 is coupled to a second terminal of the seventh transistor T7. A gate terminal of the eighth transistor T8 is for receiving the first control signal EM 1. A first terminal of the ninth transistor T9 is coupled to the reference voltage Vref (low potential, e.g., -3.3V). A second terminal of the ninth transistor T9 is coupled to the second terminal of the seventh transistor T7. A gate terminal of the ninth transistor T9 is for receiving the first control signal EM 1. A first terminal of the light emitting device D is coupled to a second terminal of the ninth transistor T9. A second terminal of the light emitting device D is coupled to a second voltage OVSS.

The operation and principle of the pixel circuit 20 will be described below in conjunction with the signal timing diagram shown in fig. 3.

The first stage ST1 of the frame display period includes a reset time rst and a data transfer time dt. In the reset time rst, the first control signal EM1 is changed from a logic high level to a logic low level, the second control signal EM2 is changed from a low level to a high level, the Scan signals Scan [1] Scan [ n ] maintain the high level, and the data voltage Vdata is set to a high voltage VdataH (e.g., an upper limit of the allowable data voltage Vdata, for example, 4V in the case where the data voltage Vdata ranges from 1V to 4V) and is greater than or greater than the reference voltage Vref. The fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the light emitting element D are turned off. The voltage Va at the first end (point a) of the second capacitor C2 can be expressed as: va, VdataH, Vth5 | wherein Vth5 is the threshold voltage of the fifth transistor T5, and | … | is the absolute value operation. The voltage Vb at the second end (point b) of the second capacitor C2 and the voltage Vc at the first end (point C) of the light emitting element D are both similar to the reference voltage Vref, so that the voltage across the first end and the second end of the second capacitor C2 is reset to a larger voltage to ensure the correctness of the subsequent pixel data writing.

In the data transfer time dt of the first stage ST1, the first control signal EM1 is maintained at a low level, the second control signal EM2 is maintained at a high level, the Scan signals Scan [1] Scan [ n ] are maintained at a high level, and the data voltage Vdata is set to a low voltage VdataL (e.g., the lower limit of the allowable data voltage Vdata, which is 1V if the range of the data voltage Vdata is 1V to 4V). The third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the light emitting element D are turned off. The voltage Va at the first end (point a) of the second capacitor C2 can be expressed as: Va-Vdata 1-VdataL + Vref + | Vth5 | where Vdata1 is the voltage of the pixel data stored in the first capacitor C1 during the previous frame display period (i.e., the second pixel data mentioned above), and Vth7 is the threshold voltage of the seventh transistor T7. The voltage Vb at the second end (point b) of the second capacitor C2 and the voltage Vc at the first end (point C) of the light emitting element D are similar to the reference voltage Vref.

In the second stage ST2, the first control signal EM1 is changed from low level to high level, the second control signal EM2 is changed from high level to low level, and the Scan signal Scan [1]]～Scan[n]It will be sequentially switched from high to low and then from low to high (i.e., a pulse). During the second stage ST2, since the fourth transistor T4 is turned off, the light emitting unit 203 can be isolated from the data updating unit 201, and since the sixth transistor T6 and the light emitting device D are turned on, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off, the current Id passing through the light emitting device D can be represented as

That is, the light emitting unit D can emit light according to the pixel data Vdata1 stored during the previous frame display period. When the previous Scan line SL (N-1) is scanned, the Scan signal Scan [ N-1]]Will change from high level to low level, Scan signal Scan [ N ]]The first transistor T1, the third transistor T3, the sixth transistor T6 and the light emitting element D are turned on while the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T2 are turned on while the high level is maintainedThe transistor T8 and the ninth transistor T9 are turned off. The voltage Vd of the first terminal (point D) of the second transistor T2 is approximately the reference voltage Vref, the voltage Vd of the second terminal (point e) of the second transistor T2 is approximately the first voltage OVDD, and the data refresh unit 201 is reset without affecting the light emitting unit D. When the scanning line SLN on which the pixel circuit is located is scanned, the scanning signal Scan [ N-1]]Will change from low level to high level, Scan the signal Scan [ N ]]From high to low, the data voltage Vdata is set to the voltage Vdata2 for the pixel data during the next frame (i.e., the third pixel data). The second transistor T2, the third transistor T3, the sixth transistor T6 and the light emitting element D are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off. The voltages Vd and Ve at the first end (point d) and the second end (point e) of the second transistor T2 are both the first voltage OVDD- | Vth3 | wherein Vth3 is the threshold voltage of the third transistor T3. The first capacitor C1 is updated according to the voltage Vdata2 for the pixel data during the next frame display. Meanwhile, the light emitting unit D still emits light according to the pixel data Vdata1 stored during the previous frame display period, and is not affected by the pixel data updated by the first capacitor C1. When the next Scan line SL (N +1) is scanned, the Scan signal Scan [ N-1]]Maintain high level, Scan signal Scan [ N ]]When the voltage level is changed from the low level to the high level, the third transistor T3, the sixth transistor T6 and the light emitting device D are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off. At this time, the voltage Vc1 of the first capacitor C1 is Vdata 2-OVDD + | Vth3 | to complete the update of the pixel data.

Referring to fig. 4, fig. 4 is a block diagram of a pixel circuit according to another embodiment of the invention. In the pixel circuit 40, the circuit structure of the light emitting unit 403 is similar to that of the light emitting unit 203 of the pixel circuit 20, and therefore, the description thereof is omitted. Only data update section 401 will be described below.

The data update unit 401 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1. A first terminal of the first transistor T1 is coupled to the reference voltage Vref. A gate terminal of the first transistor T1 is for receiving the first control signal EM 1. A second terminal of the second transistor T2 is coupled to a second terminal of the first transistor. A second terminal of the second transistor T2 is coupled to the data voltage Vdata. A gate terminal of the second transistor T2 is for receiving the Scan signal Scan [ N ] of the current stage. A first terminal of the third transistor T3 is coupled to the first voltage OVDD. A second terminal of the third transistor T3 is coupled to the second terminal of the first transistor T1. A gate terminal of the third transistor T3 is for receiving the Scan signal Scan [ N-1] of the previous stage. A first terminal of the first capacitor C1 is coupled to the second terminal of the first transistor T1. A first terminal of the fourth transistor T4 is coupled to a second terminal of the first capacitor C1. A second terminal of the fourth transistor T4 is coupled to the reference voltage Vref. A gate terminal of the fourth transistor T4 is for receiving the Scan signal Scan [ N-1] of the previous stage. A first terminal of the fifth transistor T5 is coupled to the second terminal of the first capacitor C1. A second terminal of the fifth transistor T5 is coupled to the light emitting unit 403. A gate terminal of the fifth transistor T5 is for receiving the Scan signal Scan [ N-1] of the current stage. A first terminal of the sixth transistor T6 is coupled to the first voltage OVDD. A second terminal of the sixth transistor T6 is coupled to the second terminal of the fifth transistor T5. A gate terminal of the sixth transistor T6 is coupled to the second terminal of the first capacitor C1.

Compared to the data update unit 201, the data update unit 401 can further enhance the ability to maintain the pixel data stored by the first capacitor C1.

Referring to fig. 5, fig. 5 is a block diagram of a pixel circuit according to another embodiment of the invention. In the pixel circuit 50, the circuit structure of the data update unit 501 is similar to that of the data update unit 201 of the pixel circuit 20, and therefore, the description thereof is omitted. Only the light emitting unit 503 will be described below.

In the light emitting unit 503, the first terminal of the ninth transistor T9 is used for receiving the first control signal EM1 instead of being coupled to the reference voltage Vref. Compared to the light emitting unit 203, the light emitting unit 503 can further improve the ability to reset the pixel data in the second capacitor C2.

Referring to fig. 6, fig. 6 is a block diagram of a pixel circuit according to another embodiment of the invention. In the pixel circuit 60, the circuit structure of the data update unit 601 is similar to that of the data update unit 401 of the pixel circuit 40, and therefore, the description thereof is omitted. Only the light emitting unit 603 will be described below.

In the light emitting unit 603, the first terminal of the twelfth transistor T12 is used for receiving the first control signal EM1, rather than being coupled to the reference voltage Vref. Compared to the light emitting unit 403, the light emitting unit 603 can further improve the capability of resetting the pixel data in the second capacitor C2.

It should be noted that the transistors in the above embodiments are described by taking PMOS transistors as examples. In other embodiments, the transistors may be NMOS transistors, with modifications to the circuitry. The light emitting device D may be an organic light emitting diode or other types of light emitting diodes, and the invention is not limited thereto.

According to the display device and the pixel circuit, the pixel data of the next frame can be updated while the pixel data is displayed, and a user does not have the watching experience of updating one by one.

While the present invention has been described with reference to the above embodiments, it is not intended to be limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims.

Claims

1. A pixel circuit for a display device, comprising:

a data update unit; and

a light emitting unit coupled to the data updating unit,

wherein the light emitting unit is reset and does not emit light in a first stage of a frame display period, the data updating unit transmits a first pixel data updated in a previous frame display period to the light emitting unit, the light emitting unit emits light according to the first pixel data received in the first stage in a second stage of the frame display period, the data updating unit updates the stored first pixel data to a second pixel data for a next frame display period,

wherein the light emitting unit comprises a first transistor, a second transistor, a third transistor, a first capacitor, a fourth transistor, a fifth transistor, a sixth transistor and a light emitting device,

wherein a first terminal of the first transistor is coupled to the data update circuit, a gate terminal of the first transistor is configured to receive a first control signal, a first terminal of the second transistor is configured to receive a data voltage, a second terminal and a gate terminal of the second transistor are coupled to a second terminal of the first transistor, a first terminal of the third transistor is coupled to a first voltage, a second terminal of the third transistor is coupled to the second terminal of the first transistor, a gate terminal of the third transistor is configured to receive a second control signal, a first terminal of the first capacitor is coupled to the second terminal of the first transistor, a first terminal of the fourth transistor is coupled to the second terminal of the first transistor, a gate terminal of the fourth transistor is coupled to a second terminal of the first capacitor, a first terminal of the fifth transistor is coupled to the second terminal of the first capacitor, a second terminal of the fifth transistor is coupled to a second terminal of the fourth transistor, a gate terminal of the fifth transistor is configured to receive the first control signal, a first terminal of the sixth transistor is coupled to a reference voltage, a second terminal of the sixth transistor is coupled to the second terminal of the fourth transistor, a gate terminal of the sixth transistor is configured to receive the first control signal, a first terminal of the light emitting device is coupled to a second terminal of the sixth transistor, and a second terminal of the light emitting device is coupled to a second voltage.

2. The pixel circuit according to claim 1, wherein the light emitting cell is replaced with a light emitting device comprising a first transistor, a second transistor, a third transistor, a first capacitor, a fourth transistor, a fifth transistor, a sixth transistor and a light emitting element, wherein a first terminal of the first transistor is coupled to the data update circuit, a gate terminal of the first transistor is for receiving a first control signal, a first terminal of the second transistor is for receiving a data voltage, a second terminal and a gate terminal of the second transistor are coupled to a second terminal of the first transistor, a first terminal of the third transistor is coupled to a first voltage, a second terminal of the third transistor is coupled to the second terminal of the first transistor, a gate terminal of the third transistor is for receiving a second control signal, a first terminal of the first capacitor is coupled to the second terminal of the first transistor, a first terminal of the fourth transistor is coupled to the second terminal of the first transistor, a gate terminal of the fourth transistor is coupled to a second terminal of the first capacitor, a first terminal of the fifth transistor is coupled to the second terminal of the first capacitor, a second terminal of the fifth transistor is coupled to a second terminal of the fourth transistor, a gate terminal of the fifth transistor is configured to receive the first control signal, a first terminal of the sixth transistor is configured to receive the first control signal, a second terminal of the sixth transistor is coupled to the second terminal of the fourth transistor, a gate terminal of the sixth transistor is configured to receive the first control signal, a first terminal of the light emitting device is coupled to a second terminal of the sixth transistor, and a second terminal of the light emitting device is coupled to a second voltage.

3. The pixel circuit according to claim 1 or 2, wherein in a reset time of the first stage of the frame display period, the first control signal is changed from high level to low level, the second control signal is changed from low level to high level, the data voltage is set to an allowable upper limit value of the data voltage, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are turned on, and the first transistor, the third transistor, and the light emitting element are turned off; and

in a data transfer time of the first stage of the frame display period, the first control signal maintains a low level, the second control signal maintains a high level, the data voltage is set to a lower limit value allowable by the data voltage, the first transistor, the fourth transistor, the fifth transistor and the sixth transistor are turned on, and the second transistor, the third transistor and the light emitting element are turned off.

4. The pixel circuit according to claim 1 or 2, wherein in the second phase of the frame display period, the first control signal is changed from low level to high level, the second control signal is changed from high level to low level, the third transistor and the light emitting element are turned on, and the first transistor, the second transistor, the fourth transistor, the fifth transistor and the sixth transistor are turned off.

5. The pixel circuit of claim 1, wherein the data update unit comprises a first capacitor, a first transistor, a second transistor, and a third transistor,

a first terminal of the first capacitor is configured to receive a data voltage, a first terminal of the first transistor is coupled to a second terminal of the first capacitor, a second terminal of the first transistor is coupled to a reference voltage, a gate terminal of the first transistor is configured to receive a previous scan signal, a first terminal of the second transistor is coupled to the second terminal of the first capacitor, a gate terminal of the second transistor is configured to receive a current scan signal, a first terminal of the third transistor is coupled to a first voltage, a second terminal of the third transistor is coupled to a second terminal of the second transistor and the light emitting unit, and a gate terminal of the third transistor is coupled to the second terminal of the first capacitor.

6. The pixel circuit according to claim 5, wherein during a reset time of the first phase of the frame display period, the previous stage scan signal and the current stage scan signal are maintained at a high level, the data voltage is set to an upper limit value allowable for the data voltage, and the first transistor, the second transistor, and the third transistor are turned off; and

in a data transfer time of the first stage of the frame display period, the previous stage scan signal and the current stage scan signal are maintained at a high level, the data voltage is set to a lower limit value allowable for the data voltage, the first transistor and the second transistor are turned off, and the third transistor is turned on.

7. The pixel circuit according to claim 5, wherein during the second phase of the frame display period, a current stage scan signal is switched from high to low, the current stage scan signal is maintained at high, the first transistor and the third transistor are turned on, and the second transistor is turned off;

when the previous stage scanning signal is changed from low level to high level and the current stage scanning signal is changed from high level to low level, the data voltage is set to a voltage corresponding to the second pixel data during the next frame display period, the second transistor and the third transistor are turned on, and the first transistor is turned off; and

when the previous stage scan signal is maintained at a high level and the current stage scan signal is changed from a low level to a high level, the third transistor is turned on, and the first transistor and the second transistor are turned off.

8. The pixel circuit of claim 1, wherein the data update unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor,

wherein a first terminal of the first transistor is coupled to a reference voltage, a gate terminal of the first transistor is configured to receive a first control signal, a first terminal of the second transistor is coupled to a second terminal of the first transistor, a second terminal of the second transistor is configured to receive a data voltage, a gate terminal of the second transistor is configured to receive a scan signal of a current stage, a first terminal of the third transistor is coupled to a first voltage, a second terminal of the third transistor is coupled to the second terminal of the first transistor, a gate terminal of the third transistor is configured to receive a scan signal of a previous stage, a first terminal of the first capacitor is coupled to the second terminal of the first transistor, a first terminal of the fourth transistor is coupled to a second terminal of the first capacitor, a second terminal of the fourth transistor is coupled to the reference voltage, a gate terminal of the fourth transistor is configured to receive the scan signal of the previous stage, a first terminal of the fifth transistor is coupled to the second terminal of the first capacitor, a second terminal of the fifth transistor is coupled to the light emitting unit, a gate terminal of the fifth transistor is configured to receive the current-level scan signal, a first terminal of the sixth transistor is coupled to the first voltage, a second terminal of the sixth transistor is coupled to the second terminal of the fifth transistor, and a gate terminal of the sixth transistor is coupled to the second terminal of the first capacitor.

9. A display device, comprising:

multiple pixel circuits each including a data update unit and a coupling

To a light emitting unit of the data update unit,

wherein the light emitting units are reset and do not emit light in a first stage of a frame display period, the data updating units transmit a plurality of first pixel data updated in a previous frame display period to the light emitting units, the light emitting units emit light according to the first pixel data received in the first stage in a second stage of the frame display period, the data updating units update the stored first pixel data into a plurality of second pixel data for a next frame display period,