CN115472114A

CN115472114A - Electronic device

Info

Publication number: CN115472114A
Application number: CN202210018344.XA
Authority: CN
Inventors: 曾名骏; 郭拱辰; 陈联祥
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2021-05-25
Filing date: 2022-01-07
Publication date: 2022-12-13

Abstract

The present disclosure provides an electronic device including a pixel circuit and a protection circuit. The pixel circuit includes a driving transistor. The protection circuit includes a first connection transistor, a first switching transistor, and a logic circuit. The first connection transistor is coupled with the driving transistor. The first switch transistor is coupled to the first connection transistor. The logic circuit is coupled to the first switch transistor. The electronic device of the present disclosure may provide pixel protection function through a protection circuit coupled to the pixel circuit.

Description

Electronic device

Technical Field

The present disclosure relates to electronic devices, and particularly to an electronic device with element protection function.

Background

With the development of technology, electronic devices are designed to be light, thin, short and small. As a result, the reliability of the device may be increasingly difficult, and the device of the electronic device may have to be damaged due to the safety-related problems, such as continuous high current and high temperature.

Disclosure of Invention

The present disclosure is directed to an electronic device, which can provide a device protection function through a protection circuit coupled to a pixel circuit.

According to some embodiments of the present disclosure, an electronic device of the present disclosure includes a pixel circuit and a protection circuit. The pixel circuit includes a driving transistor. The protection circuit includes a first connection transistor, a first switching transistor, and a logic circuit. The first connecting transistor is coupled with the driving transistor. The first switch transistor is coupled to the first connection transistor. The logic circuit is coupled to the first switch transistor.

According to some embodiments of the present disclosure, the electronic device of the present disclosure may detect an operation signal (e.g., a scan signal and/or a reset signal) of the pixel circuit through the protection circuit, and when an abnormality occurs in the operation signal of the pixel circuit, the protection circuit may turn off the driving transistor of the pixel circuit of the abnormal pixel, so as to provide a function of element protection.

In order to make the aforementioned and other features and advantages of the disclosure more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic view of an electronic device according to some embodiments of the present disclosure;

FIG. 2 is another schematic diagram of an electronic device according to some embodiments of the present disclosure;

FIG. 3 is a circuit diagram of an electronic device according to some embodiments of the present disclosure;

FIG. 4 is a timing diagram of signals of some embodiments of the present disclosure;

FIG. 5 is a circuit diagram of an electronic device according to some embodiments of the present disclosure;

fig. 6 is a circuit diagram of an electronic device according to some embodiments of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, in which it is noted that, for the sake of clarity and brevity of the drawings, the various drawings in the present disclosure depict only some of the electronic devices and are not necessarily drawn to scale. In addition, the number and size of the components in the drawings are merely illustrative and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that differ in function but not name. In the following specification and claims, the words "comprise", "comprising", "includes" and "includes" are open-ended words, and thus should be interpreted to mean "including, but not limited to …".

In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, with respect to bonding, connecting, and the like, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, unless otherwise specified, with respect to the structure between which they are disposed. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed. Furthermore, the terms "electrically connected" and "coupled" include any direct and indirect electrical connection.

The use of ordinal numbers such as "first," "second," etc., in the specification and claims to modify an element is not by itself intended to imply that it is not intended to be, or that any preceding elements are included in the composition or order of importance in a given element or method of manufacture, but are merely used to distinguish one element having a certain name from another element having a same name. The claims may not use the same words in the specification and accordingly, a first element in a specification may be a second element in a claim. It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure.

It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure. Features of the various embodiments may be combined and matched as desired, without departing from the spirit or ambit of the invention.

In the following embodiments, the electronic device may include a display device, an antenna device, a sensing device, or a splicing device, but not limited thereto. The electronic device can be a bendable or flexible electronic device. The electronic device comprises a diode element, wherein the diode element may or may not emit light. The diode element may include, for example, a PN diode or a PIN diode, but is not limited thereto. The electronic device may include, for example, liquid Crystal (LC), light emitting diode (led), quantum Dot (QD), fluorescence (Fluorescence), phosphorescence (Phosphor), other suitable materials, or combinations thereof, but the disclosure is not limited thereto. The light emitting diode may, for example, comprise an organic light emitting diode or an inorganic light emitting diode. The light emitting diode may include, for example, an Active-matrix Organic light-emitting diode (AMOLED), an Organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (qd), but the disclosure is not limited thereto. The antenna device may be, for example, a liquid crystal antenna, but the disclosure is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but the disclosure is not limited thereto. It should be noted that the electronic device can be any permutation and combination of the foregoing, but the disclosure is not limited thereto.

In the following embodiments, the first terminal, the second terminal and the control terminal of the Transistor may refer to a source, a gate and a drain of a Thin-Film Transistor (TFT), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and the like.

Fig. 1 is a schematic view of an electronic device according to some embodiments of the present disclosure. Referring to fig. 1, an electronic device 100 includes a pixel circuit 110 and a protection circuit 120. The pixel circuit 110 includes a driving transistor 111, a pixel switching transistor 112, a scan transistor 113, a reset transistor 114, a diode element 115, and a storage capacitor (Cst) 116. In this embodiment, the first terminal of the driving transistor 111 is coupled to the operating voltage VDD. The second terminal of the driving transistor 111 is coupled to the first terminal of the pixel switching transistor 112. The control terminal of the driving transistor 111 is coupled to the first terminal of the driving transistor 111, and is coupled to the scan transistor 113, the reset transistor 114 and the protection circuit 120 through a circuit node N1. A second terminal of the pixel switching transistor 112 is coupled to a first terminal of the diode element 115. The control terminal of the pixel switching transistor 112 may receive the control signal EM. The first terminal of the scan transistor 113 may receive driving data (or display data) Din. The control terminal of the scan transistor 113 may receive the scan signal Sn. A second terminal of the scan transistor 113 is coupled to the control terminal of the driving transistor 111 via a circuit node N1. A first terminal of the reset transistor 114 is coupled to the reset voltage VRST. The second terminal of the reset transistor 114 is coupled to the control terminal of the driving transistor 111 through the circuit node N1. The control terminal of the reset transistor 114 may receive a reset signal RST. A second terminal of the diode 115 is coupled to a ground voltage VSS. In some embodiments, diode element 115 may include a light emitting diode 115_1. The anode of the led 115_1 is coupled to the second terminal of the pixel switch transistor 112. The cathode of the led 115_1 is coupled to a ground voltage VSS. In some embodiments, diode element 115 may include a plurality of light emitting diodes in series. A first terminal of the storage capacitor 116 is coupled to the first terminal of the driving transistor 111, and a second terminal of the storage capacitor 116 is coupled to the control terminal of the driving transistor 111.

In the present embodiment, the driving transistor 111, the pixel switch transistor 112, the scan transistor 113, and the reset transistor 114 may be P-type thin film transistors or P-type metal oxide semiconductor field effect transistors, but the disclosure is not limited thereto. In addition, in some embodiments, the pixel circuit 110 may further include other transistors, not limited to the 3T1C pixel circuit architecture shown in fig. 1, for example, a circuit architecture composed of seven transistors and two capacitors (7T 2C), or a circuit architecture composed of eight transistors and two capacitors (8T 2C), which is not limited in this disclosure. It is noted that the protection circuit 120 of the present disclosure can be applied to various circuit architectures. In some embodiments, the protection circuit 120 may be on the same substrate as the diode element 115. In some embodiments, the protection circuit 120 may be on a different substrate than the diode device 115.

In the present embodiment, the pixel circuit 110 can be respectively operated in a reset mode and a driving mode (also referred to as a display mode or a light-emitting mode) during, for example, a reset period and a driving period according to the driving data, the control signal EM, the scan signal Sn, and the reset signal RST. In the embodiment, the protection circuit 120 may receive the control signal EM, the scan signal Sn, and the reset signal RST to detect at least one of the scan signal Sn and the reset signal RST. When at least one of the scan signal Sn and the reset signal RST is abnormal in signal (voltage), the protection circuit 120 may provide a turn-off voltage to the control terminal of the driving transistor 111 through the circuit node N1 to turn off the driving transistor 111, so as to effectively protect the diode element 115. In addition, in some embodiments, the protection circuit 120 may also be coupled to other pixel circuits of the electronic device 100.

Fig. 2 is another schematic diagram of an electronic device according to some embodiments of the present disclosure. Referring to fig. 2, the electronic device 200 may include a pixel 210 and a protection circuit 220. The pixel 210 may include a plurality of pixel circuits 210 _1-210 _3, and each of the pixel circuits 210 _1-210 _3may be implemented as the pixel circuit 110 in the embodiment of fig. 1, but the number of the pixel circuits in the pixel 210 is not limited thereto. In some embodiments, the pixel 210 may include one or more pixel circuits. In the present embodiment, the pixel circuits 210_1-210_3 can be pixel circuits corresponding to red, green, or blue sub-pixels, respectively, for example.

In the present embodiment, the protection circuit 220 includes a logic circuit 221, a switching transistor 222, and connection transistors 223 _1to 223_3, wherein the connection transistors 223 _1to 223 _3can be respectively coupled to driving transistors (e.g., the driving transistor 111 of fig. 1) in the pixel circuits 210 _1to 210_3. The logic circuit 221 is coupled to the first terminal of the switching transistor 222. A second terminal of the switch transistor 222 is coupled to control terminals of the transistors 223_1 to 223_3. The control terminal of the switching transistor 222 may receive the control signal EM. The first terminal of the connection transistors 223_1 to 223 _3can receive the protection voltage Vp, wherein the protection voltage Vp can be the operating voltage VDD shown in fig. 1, but the disclosure is not limited thereto. The second terminals of the connecting transistors 223_1 to 223_, 3 are coupled to the pixel circuits 210 _u1 to 210_, 3, respectively. In addition, the logic circuit 221 may receive the control signal EM and at least one of the scan signal and the reset signal (e.g., the scan signal Sn and the reset signal RST shown in fig. 1) to detect at least one of the scan signal and the reset signal.

In the present embodiment, the switch transistor 222 and the connection transistors 223 _1to 223 _3may be a P-type thin film transistor or a P-type mosfet, respectively, but the disclosure is not limited thereto. In this embodiment, when a signal (e.g., a voltage signal) abnormality (e.g., an error trigger abnormality) occurs in at least one of the scan signal and the reset signal, the logic circuit 221 may provide a turn-off voltage to the control terminals of the driving transistors in the pixel circuits 210 u 1 to 210 u 3 through the switch transistor 222 and the connection transistors 223 u 1 to 223 u 3 and the circuit nodes (e.g., the circuit node N1 shown in fig. 1) in the pixel circuits 210 u 1 to 210 u 3 to turn off the driving transistors in the pixel circuits 210 u 1 to 210 u 3, thereby effectively protecting the diode elements (e.g., the diode element 115 shown in fig. 1) in the pixel circuits 210 u 1 to 210 u 3.

Fig. 3 is a circuit diagram of an electronic device according to some embodiments of the present disclosure. Referring to fig. 3, the electronic device 300 may include a pixel 310 and a protection circuit 320. The pixel 310 may include a plurality of pixel circuits 310 _1-310 _3, and each of the pixel circuits 310 _1-310 _3may be implemented as the pixel circuit 110 in the embodiment of fig. 1, but the number of pixel circuits in the pixel 310 is not limited thereto. In some embodiments, pixel 310 may include one or more pixel circuits. In the present embodiment, the pixel circuits 310 _1to 310 _3may be pixel circuits corresponding to a red sub-pixel, a green sub-pixel, or a blue sub-pixel, respectively, for example.

In the embodiment, the protection circuit 320 includes a logic circuit 321, switching

transistors

322 and 324, connection transistors 323 _1to 323_3, and

impedance circuits

325 and 326, wherein the connection transistors 323 _1to 323 _3can be respectively coupled to driving transistors (e.g., the driving transistor 111 of fig. 1) in the pixel circuits 310 _1to 310_3. The logic circuit 321 is coupled to the first terminal of the switching transistor 324. The second terminal of the switch transistor 324 is coupled to the circuit node N31 between the first terminal of the switch transistor 322 and the impedance circuit 325. The second terminal of the switch transistor 322 is coupled to the control terminals of the transistors 323 _1-323 _3and the impedance circuit 326 via the circuit node N32. The control terminals of the switching

transistors

322, 324 may receive the control signal EM. The first terminal of the connection transistors 323_1-323 _3can receive a protection voltage Vp, wherein the protection voltage Vp can be the operating voltage VDD shown in fig. 1, but the disclosure is not limited thereto. The second terminals of the connecting transistors 323_1 through 323 _3are coupled to the pixel circuits 310_1 through 310_3, respectively.

In the present embodiment, the impedance circuit 325 may include

transistors

325, 2. A first terminal of transistor 325_1 is coupled to circuit node N31. The second terminal of the transistor 325_1 is coupled to the control terminal of the transistor 325 _u1 and the first terminal of the transistor 325 _u2. The second terminal of the transistor 325_2 is coupled to the control terminal of the transistor 325 _2and the ground voltage GND. However, in some embodiments, the impedance circuit 325 may be other types of impedance circuits and is not limited to that shown in FIG. 3.

In the present embodiment, the impedance circuit 326 may include a transistor 326_1. The first terminal of the transistor 326V 1 may receive a reference voltage V1, wherein the reference voltage V1 is a high level voltage and may be, for example, a protection voltage Vp. The second terminal of the transistor 326_1 is coupled to the control terminal of the transistor 326 _u1 and the circuit node N32. However, in some embodiments, impedance circuit 326 may be other types of impedance circuits and is not limited to that shown in FIG. 3.

In this embodiment, the logic circuit 321 includes a circuit connection transistor 321_1, a switching circuit 321_2, a circuit switching transistor 321_3, and an impedance circuit 321_4. The circuit connection transistor 321\ u 1 is coupled between the switch transistor 324 and the reference voltage V1. A first terminal of the circuit connection transistor 321_1 may receive the reference voltage V1. A second terminal of the circuit connection transistor 321_1 is coupled to a first terminal of the switch transistor 324. The switching circuit 321_2 is coupled to a control terminal of the circuit connection transistor 321 _1. The circuit switch transistor 321 _3is coupled to the reference voltage V1. A first terminal of the circuit switching transistor 321 \ u 3 may receive the reference voltage V1. The control terminal of the circuit switching transistor 321 \ u 3 may receive the control signal EM. A second terminal of the circuit switch transistor 321_3 is coupled to the switching circuit 321_2. The switching circuit 321_2 includes a scan transistor 321 _21and a reset transistor 321_22. The first terminals of the scan transistor 321 _21and the reset transistor 321 _22are coupled to the second terminal of the circuit switch transistor 321 _3. The control terminal of the scan transistor 321_21 may receive the scan signal Sn. The control terminal of the reset transistor 321_22 may receive a reset signal RST. The second terminals of the scan transistor 321 _21and the reset transistor 321 _22are coupled to the impedance circuit 321 _u4. The impedance circuit 321_4 may include a transistor 321 _u41. The first terminal of the transistor 321_41 is coupled to the control terminal of the transistor 321 _u41, the control terminal of the circuit connection transistor 321 _u1, and the second terminals of the scan transistor 321 _u21 and the reset transistor 321 _u22. A second terminal of the transistor 321_41 is coupled to a ground voltage GND. However, in some embodiments, the impedance circuit 321_4 may be other types of impedance circuits as well, and is not limited to that shown in fig. 3.

In the present embodiment, the circuit connection transistor 321_1, the connection transistors 323 _1to 323_3, the scan transistor 321_21, the reset transistor 321_22, the circuit switch transistor 321_3, the

switch transistors

322 and 324, and the transistors 321_41, 325_1, 325_2, and 326 _1can be P-type thin film transistors or P-type mosfets, respectively, but the present disclosure is not limited thereto.

Referring to fig. 3 and 4 together, fig. 4 is a signal timing diagram of some embodiments of the present disclosure. In some embodiments of the present disclosure, each of the pixel circuits 310 _1through 310 _3may respectively receive the control signal EM, the reset signal RST and the scan signal Sn, so that the operation may be the set mode according to the set period P1 between the time t0 and the time t5 of the control signal EM, the reset signal RST and the scan signal Sn, and the operation may be the driving mode during the driving period P2 between the time t5 and the time t 6. Referring to table 1 below, in the setting period P1, the control signal EM is a high level voltage to turn off the switching transistors 321_3, 322, 324 and 310 _1to 310 _3of the pixel circuits, respectively.

In the reset period PR from time t1 to time t2, the reset signal RST is switched from a high level voltage to a low level voltage to turn on the reset transistors of the pixel circuits 310 _1to 310_3, respectively, thereby resetting the storage capacitors of the pixel circuits 310 _1to 310_3, respectively. In a period PS from time t3 to time t4, the scan signal Sn is switched from a high level voltage to a low level voltage to turn on the scan transistors of the pixel circuits 310 _1to 310_3, respectively, thereby writing the driving data to the storage capacitors of the pixel circuits 310 _1to 310_3, respectively. As in the operation states 1 to 3 of table 1 below, the circuit node N31 maintains a low level voltage and the circuit node N32 maintains a high level voltage to turn off the connection transistors 323 _1to 323_3.

In the driving period P2 between time t5 and time t6, the control signal EM is a low level voltage to turn on the pixel switching transistors of the circuit switching transistor 321_3, the switching transistor 322, the switching transistor 324, and the pixel circuits 310 _1to 310_3, respectively. The reset signal RST and the scan signal Sn are high level voltages respectively to turn off the reset transistors and the scan transistors of the pixel circuits 310 _1to 310_3, respectively. Circuit nodes N31, N32 are high to turn off connecting transistors 323 u 1-323 u 3 as in operating state 4 of table 1 below. It is to be noted that, since the scan transistor 321 xu 21 and the reset transistor 321 xu 22 of the switching circuit 321 xu 2 can also receive the reset signal RST and the scan signal Sn, when a signal (voltage) abnormality (false trigger) occurs in at least one of the reset signal RST and the scan signal Sn, for example, when the voltage of at least one of the reset signal RST and the scan signal Sn is converted from a high-level voltage to a low-level voltage in the driving period P2, at least one of the scan transistor 321 xu 21 and the reset transistor 321 xu 22 is turned on, so that the circuit connecting transistor 321 xu 1 is turned on. As shown in the operation states 5 to 7 in table 1 below, when at least one of the reset signal RST and the scan signal Sn has an abnormal signal (voltage), the circuit nodes N31 and N32 may be switched to low-level voltages, respectively, to turn on the connection transistors 323_1 to 323_3. In contrast, the circuit connecting transistor 321_1 can provide the reference voltage V1 to the control terminal of the connecting transistors 323 _1to 323 _3through the switching

transistors

322 and 324 and the circuit nodes N31 and N32 to turn on the connecting transistors 323 _1to 323_3. Then, the connection transistors 323 _1to 323 _3can respectively provide the protection voltage Vp to the driving transistors of the pixel circuits 310 _1to 310_3, respectively, to turn off the driving transistors. Therefore, the protection circuit 320 can effectively protect the diode elements in the pixel circuits 310 _1to 310 _3of the pixel 310, and can prevent the diode elements in the pixel circuits 310 _1to 310 _3from being damaged due to the voltage signal abnormality of at least one of the reset signal RST and the scan signal Sn, thereby realizing the current overload protection function of the pixel 310.

TABLE 1

In addition, in some embodiments, the switching circuit 321_2 may also include only one of the scan transistor 321 _21and the reset transistor 321_22, and when a signal (voltage) abnormality occurs in one of the scan signal Sn and the reset signal RST, the protection circuit 320 may turn on the connection transistors 323 _1to 323 _3to turn off the driving transistors of the pixel circuits 310 _1to 310_3, respectively, so as to achieve the current overload protection function of the pixel 310.

Fig. 5 is a circuit diagram of an electronic device according to some embodiments of the present disclosure. Referring to fig. 5, the electronic device 500 may include a pixel 510 and a protection circuit 520. The pixel 510 may include a plurality of pixel circuits 510 _1-510 _3, and each of the pixel circuits 510 _1-510 _3may be implemented as the pixel circuit 110 of fig. 1, respectively, but the number of pixel circuits in the pixel 510 of the present disclosure is not limited thereto. In some embodiments, pixel 510 may include one or more pixel circuits. In the present embodiment, the pixel circuits 510 _1to 510 _3may be pixel circuits corresponding to a red sub-pixel, a green sub-pixel, or a blue sub-pixel, respectively, for example.

In the present embodiment, the protection circuit 520 includes a logic circuit 521, switching

transistors

522 and 524, connection transistors 523_1 to 523_3, and

impedance circuits

525 and 526, wherein the connection transistors 523_1 to 523 _u3 may be respectively coupled to driving transistors (e.g., the driving transistor 111 of fig. 1) in the connection transistors 523 _u1 to 523 _u3. The logic circuit 521 is coupled to a first terminal of the switching transistor 524 and a first terminal of the switching transistor 522 through a circuit node N51. A second terminal of the switching transistor 524 is coupled to an impedance circuit 525. A second terminal of the switching transistor 522 is coupled to the control terminals of the transistors 523_1 to 523_3 and the impedance circuit 526 through a circuit node N52. The control terminals of the switching

transistors

522, 524 may receive the control signal EM. The first terminal of the connection transistor 523_1-523 _3may receive the protection voltage Vp, wherein the protection voltage Vp may be the operating voltage VDD shown in fig. 1, but the disclosure is not limited thereto. Second ends of the connecting transistors 523\ u 1 to 523_3 are coupled to the pixel circuits 510_1 to 510_3, respectively.

In the present embodiment, the impedance circuit 525 may include transistors 525_1, 525 _u2. A first terminal of the transistor 525_1 is coupled to a second terminal of the switching transistor 524. The second terminal of the transistor 525_1 is coupled to the control terminal of the transistor 525 _u1 and the first terminal of the transistor 525 _u2. The second terminal of the transistor 525_2 is coupled to the control terminal of the transistor 525 _u2 and the ground voltage GND. However, in some embodiments, the impedance circuit 525 may be other types of impedance circuits and is not limited to that shown in FIG. 5.

In this embodiment, the impedance circuit 526 may include a transistor 526_1. The first terminal of the transistor 526_1 may receive a reference voltage V1, wherein the reference voltage V1 is a high level voltage and may be, for example, a protection voltage Vp. The second terminal of transistor 526_1 is coupled to the control terminal of transistor 526_1 and circuit node N52. However, in some embodiments, the impedance circuit 526 may be other types of impedance circuits and is not limited to that shown in FIG. 5.

In this embodiment, the logic circuit 521 includes a circuit connection transistor 521_1, a switching circuit 521_2, a circuit switching transistor 521_3, and an impedance circuit 521_4. The circuit connection transistor 521_1 is coupled between the circuit node N51 and the reference voltage V1. A first terminal of the circuit connection transistor 521_1 may receive the reference voltage V1. A second terminal of the circuit connection transistor 521_1 is coupled to a first terminal of the switching transistor 524. The switching circuit 521_2 is coupled to a control terminal of the circuit connection transistor 521 _1. The circuit switch transistor 521 \ u 3 is coupled to the reference voltage V1. A first terminal of the circuit switching transistor 521 u 3 may receive the reference voltage V1. The control terminal of circuit switching transistor 521 u 3 may receive control signal EM. A second terminal of the circuit switch transistor 521 u 3 is coupled to the switching circuit 521 u 2. The switching circuit 521_2 includes a scan transistor 521 _21and a reset transistor 521_22. The first terminals of the scan transistor 521 u 1 and the reset transistor 521 u 22 are coupled to the second terminal of the circuit switch transistor 521 u 3. The control terminal of the scan transistor 521_21 may receive a scan signal Sn. The control terminal of the reset transistor 521_22 may receive a reset signal RST. The second terminals of the scan transistor 521 u 21 and the reset transistor 521 u 22 are coupled to the impedance circuit 521 u 4. Impedance circuit 521_4 may include transistor 521 _u41. A first terminal of the transistor 521_41 is coupled to a control terminal of the transistor 521 _u41, a control terminal of the circuit connection transistor 521 _u1, and second terminals of the scan transistor 521 _u21 and the reset transistor 521 _u22. A second terminal of the transistor 521_41 is coupled to a ground voltage GND. However, in some embodiments, the impedance circuit 521_4 may also be other types of impedance circuits and is not limited to that shown in fig. 5.

In this embodiment, the circuit connection transistor 521_1, the connection transistors 523 _1to 523_3, the scan transistor 521_21, the reset transistor 521_22, the circuit switching transistor 521_3, the switching transistor 522, the switching transistor 524, and the transistors 521_41, 525_1, 525_2, and 526 _1may be P-type thin film transistors or P-type mosfets, respectively, but the present disclosure is not limited thereto.

Referring to fig. 4 and fig. 5, the signal timing of fig. 4 can also be applied to the electronic device 500 of fig. 5. In some embodiments of the present disclosure, each of the pixel circuits 510 _1to 510 _3may respectively receive the control signal EM, the reset signal RST and the scan signal Sn, so that the operation may be the set mode according to the set period P1 between the time t0 and the time t5 of the control signal EM, the reset signal RST and the scan signal Sn, and the operation may be the driving mode during the driving period P2 between the time t5 and the time t 6. Referring to table 2 below, in the setting period P1, the control signal EM is a high level voltage to turn off the pixel switching transistors of the circuit switching transistor 521 u 3, the switching transistor 522, the switching transistor 524, and the pixel circuits 510 u 1 to 510 u 3, respectively.

In the reset period PR from time t1 to time t2, the reset signal RST is switched from a high level voltage to a low level voltage to turn on the reset transistors of the pixel circuits 510 _1to 510_3, respectively, thereby resetting the storage capacitors of the pixel circuits 510 _1to 510_3, respectively. In a period PS from time t3 to time t4, the scan signal Sn is switched from a high level voltage to a low level voltage to turn on the scan transistors of the pixel circuits 510 _1to 510_3, respectively, thereby writing drive data to the storage capacitors of the pixel circuits 510 _1to 510_3, respectively. As in the operation states 1 to 3 of table 2 below, the circuit nodes N51 and N52 maintain a high level voltage to turn off the connection transistors 523 u 1 to 523 u 3.

In the driving period P2 between time t5 and time t6, the control signal EM is a low-level voltage to turn on the pixel switching transistors of the circuit switching transistor 521 u 3, the switching transistor 522, the switching transistor 524, and the pixel circuits 510 u 1 to 510 u 3, respectively. The reset signal RST and the scan signal Sn are high level voltages respectively to turn off the reset transistors and the scan transistors of the pixel circuits 510 _1to 510_3, respectively. As in operation state 4 of table 2 below, circuit nodes N51, N52 are high voltage to turn off connecting transistors 523 u 1 to 523_3. It is to be noted that since the scan transistor 521_21 and the reset transistor 521 _22of the switching circuit 521 _u2 can receive the reset signal RST and the scan signal Sn as well, when a signal (voltage) abnormality (false trigger) occurs in at least one of the reset signal RST and the scan signal Sn, for example, when the voltage of at least one of the reset signal RST and the scan signal Sn is converted from a high-level voltage to a low-level voltage during the driving period P2, at least one of the scan transistor 521 _u21 and the reset transistor 521 _u22 is turned on, so that the circuit connecting transistor 521 _u1 is turned on. As shown in the operation states 5 to 7 in table 2 below, when a signal (voltage) abnormality occurs in at least one of the reset signal RST and the scan signal Sn, the circuit nodes N51 and N52 are switched to low-level voltages, respectively, to turn on the connection transistors 523 _1to 523_3. In contrast, the circuit connecting transistor 521_1 can provide the reference voltage V1 to the control terminals of the connecting transistors 523 _1to 523 _3through the switching

transistors

522 and 524 and the circuit nodes N51 and N52 to turn on the connecting transistors 523 _1to 523_3. Then, the connection transistors 523_1 to 523_3 may respectively provide the protection voltages Vp to the driving transistors of the pixel circuits 510_1 to 510_3, respectively, to turn off the driving transistors. Therefore, the protection circuit 520 can effectively protect the diode elements in the pixel circuits 510 _1to 510 _3of the pixel 510, and can prevent the diode elements in the pixel circuits 510 _1to 510 _3from being damaged when at least one of the reset signal RST and the scan signal Sn is abnormal in voltage, thereby realizing the current overload protection function of the pixel 510.

TABLE 2

In addition, in some embodiments, the switching circuit 521_2 may also include only one of the scan transistor 521 _21and the reset transistor 521_22, and when a signal (voltage) abnormality occurs in one of the scan signal Sn and the reset signal RST, the protection circuit 520 may turn on the connection transistors 523 _1to 523 _3to turn off the driving transistors of the pixel circuits 510 _1to 510_3, respectively, so as to achieve the current overload protection function of the pixel 510.

Fig. 6 is a circuit diagram of an electronic device according to a third embodiment of the disclosure. Referring to fig. 6, the electronic device 600 may include a pixel 610 and a protection circuit 620. The pixel 610 may include a plurality of pixel circuits 610 _1through 610_3, and each of the pixel circuits 610 _1through 610 _3may be implemented as the pixel circuit 110 of fig. 1, respectively, but the number of pixel circuits in the pixel 610 of the present disclosure is not limited thereto. In some embodiments, pixel 610 may include one or more pixel circuits. In the present embodiment, the pixel circuits 610 _1to 610 _3may be pixel circuits corresponding to red, green, or blue sub-pixels, respectively, for example.

In the embodiment, the protection circuit 620 includes a logic circuit 621, a switching transistor 622, connection transistors 623_1 to 623 _u3, and

impedance circuits

625 and 626, wherein the connection transistors 623 _u1 to 623 _u3 can be respectively coupled to driving transistors (e.g., the driving transistor 111 in fig. 1) in the connection transistors 623 _u1 to 623 _u3. The logic circuit 621 is coupled to the first terminal of the switch transistor 622 and the impedance circuit 625 through a circuit node N61. The second terminal of the switch transistor 622 is coupled to the control terminals of the transistors 623 u 1 to 623 u 3 and the impedance circuit 626 through a circuit node N62. The control terminal of the switching transistor 622 may receive the control signal EM. The first terminal of the connection transistors 623_1-623 _u3 may receive a protection voltage Vp, wherein the protection voltage Vp may be the operating voltage VDD shown in fig. 1, but the disclosure is not limited thereto. Second ends of the connection transistors 623_1 to 623 _u3 are coupled to the pixel circuits 610 _u1 to 610 _u3, respectively.

In the present embodiment, the impedance circuit 625 may include transistors 625_1, 625_2. A first terminal of transistor 625_1 is coupled to circuit node N61. The second terminal of the transistor 625_1 is coupled to the control terminal of the transistor 625 _u1 and the first terminal of the transistor 625 _u2. The second terminal of the transistor 625_2 is coupled to the control terminal of the transistor 625 _u2 and the ground voltage GND. However, in some embodiments, the impedance circuit 625 may be other types of impedance circuits, and is not limited to the one shown in fig. 6.

In the present embodiment, the impedance circuit 626 may include a transistor 626_1. The first terminal of the transistor 626_1 may receive a reference voltage V1, wherein the reference voltage V1 is a high level voltage and may be, for example, a protection voltage Vp. The second terminal of the transistor 626_1 is coupled to the control terminal of the transistor 626 _1and the circuit node N62. However, in some embodiments, the impedance circuit 626 may be other types of impedance circuits and is not limited to that shown in fig. 6.

In this embodiment, the logic circuit 621 includes a circuit connection transistor 621_1, a switching circuit 621_2, a circuit switching transistor 621_3, and an impedance circuit 621_4. The circuit connection transistor 621_1 is coupled between the circuit node N61 and the reference voltage V1. A first terminal of the circuit connection transistor 621_1 may receive the reference voltage V1. The second terminal of the circuit connection transistor 621_1 is coupled to the first terminal of the switch transistor 622. The switching circuit 621_2 is coupled to the control terminal of the circuit connection transistor 621 _u1. The circuit switch transistor 621_3 is coupled to the reference voltage V1. A first terminal of the circuit switching transistor 621_3 may receive the reference voltage V1. The control terminal of circuit switching transistor 621_3 may receive control signal EM. A second terminal of the circuit switch transistor 621_3 is coupled to the switching circuit 621_2. The switching circuit 621_2 includes a scan transistor 621_21 and a reset transistor 621_22. First terminals of the scan transistor 621_1 and the reset transistor 621_22 are coupled to a second terminal of the circuit switch transistor 621_3. The control terminal of the scan transistor 621_21 may receive the scan signal Sn. The control terminal of the reset transistor 621_22 may receive a reset signal RST. The second terminals of the scan transistor 621_21 and the reset transistor 621 _u22 are coupled to the impedance circuit 621 _u4. Impedance circuit 621_4 may include transistor 621_41. The first terminal of the transistor 621_41 is coupled to the control terminal of the transistor 621 _u41, the control terminal of the circuit connection transistor 621 _u1, and the second terminals of the scan transistor 621 _u21 and the reset transistor 621 _u22. The second terminal of the transistor 621_41 is coupled to the ground voltage GND. However, in some embodiments, impedance circuit 621_4 may be other types of impedance circuits, and is not limited to that shown in fig. 6.

In the present embodiment, the circuit connection transistor 621_1, the connection transistors 623 _u1 to 623 _u3, the scan transistor 621 _u21, the reset transistor 621 _u22, the circuit switch transistor 621 _u3, the switch transistor 622, and the transistors 621 _u41, 625 _u1, 625 _u2, and 626 _u1 may be P-type thin film transistors or P-type metal oxide semiconductor field effect transistors, but the disclosure is not limited thereto.

Referring to fig. 4 and fig. 6 together, the signal timing of fig. 4 can also be applied to the electronic device 600 of fig. 6. In some embodiments of the present disclosure, each of the pixel circuits 610 _1through 610 _3may respectively receive the control signal EM, the reset signal RST and the scan signal Sn, so that the operation may be the set mode according to the set period P1 between the time t0 and the time t5 of the control signal EM, the reset signal RST and the scan signal Sn, and the operation may be the driving mode during the driving period P2 between the time t5 and the time t 6. Referring to table 3 below, in the setting period P1, the control signal EM is a high level voltage to turn off the pixel switching transistors of the circuit switching transistors 621_3, the switching transistor 622, and the pixel circuits 610 _1to 610_3, respectively.

In the reset period PR from time t1 to time t2, the reset signal RST is switched from a high level voltage to a low level voltage to turn on the reset transistors of the pixel circuits 610 _1to 610_3, respectively, thereby resetting the storage capacitors of the pixel circuits 610 _1to 610_3, respectively. In a period PS from time t3 to time t4, the scan signal Sn is switched from a high level voltage to a low level voltage to turn on the scan transistors of the pixel circuits 610 _1to 610_3, respectively, thereby writing driving data to the storage capacitors of the pixel circuits 610 _1to 610_3, respectively. As in the operation states 1 to 3 of table 2 below, the circuit node N61 maintains a low level voltage, and the circuit node N62 maintains a high level voltage to turn off the connection transistors 623\ u 1 to 623_3.

In the driving period P2 between time t5 and time t6, the control signal EM is at a low level voltage to turn on the pixel switching transistors of the circuit switching transistor 621, the switching transistor 622, and the pixel circuits 610\ u 1 to 610_3, respectively. The reset signal RST and the scan signal Sn are high-level voltages respectively to turn off the reset transistors and the scan transistors of the pixel circuits 610 _1to 610_3, respectively. In the following operating state 4 of table 3, the circuit nodes N61 and N62 are at high voltage level to turn off the connection transistors 623 _1to 623_3. It is to be noted that, since the scan transistor 621_21 and the reset transistor 621_22 of the switching circuit 621_2 can also receive the reset signal RST and the scan signal Sn, when a signal (voltage) abnormality (false trigger) occurs in at least one of the reset signal RST and the scan signal Sn, for example, when the voltage of at least one of the reset signal RST and the scan signal Sn is converted from a high-level voltage to a low-level voltage in the driving period P2, at least one of the scan transistor 621 _u21 and the reset transistor 621 _u22 is turned on, so that the circuit connection transistor 621 _u1 is turned on. As shown in the operation states 5 to 7 in table 3 below, when at least one of the reset signal RST and the scan signal Sn has an abnormal signal (voltage), the circuit nodes N61 and N62 are respectively switched to low-level voltages to turn on the connection transistors 623 v1 to 623 v 3. In contrast, the circuit connection transistor 621\ u 1 can provide the reference voltage V1 to the control terminals of the connection transistors 623 \ -u 1 to 623 \ -u 3 through the switching transistor 622 and the circuit nodes N61 and N62 to turn on the connection transistors 623 \ -u 1 to 623 \ -u 3. Then, the connection transistors 623_1 through 623 _u3 can respectively provide the protection voltage Vp to the driving transistors of the pixel circuits 610 _u1 through 610 _u3, respectively, to turn off the driving transistors. Therefore, the protection circuit 620 can effectively protect the diode elements in the pixel circuits 610 _1to 610 _3of the pixel 610, and can prevent the diode elements in the pixel circuits 610 _1to 610 _3from being damaged when at least one of the reset signal RST and the scan signal Sn is abnormal in voltage, thereby realizing the current overload protection function of the pixel 610.

TABLE 3

In addition, in some embodiments, the switching circuit 621_2 may also include only one of the scan transistor 621_21 and the reset transistor 621 _u22, and when a signal (voltage) abnormality occurs in one of the scan signal Sn and the reset signal RST, the protection circuit 620 may turn on the connection transistors 623 _u1 to 623 _u3 to turn off the driving transistors of the pixel circuits 610 _u1 to 610 _u3, thereby implementing a current overload protection function of the pixel 610.

In summary, the electronic device of the present disclosure can self-detect one of the scan signal and the reset signal of the pixel through the protection circuit coupled to the pixel, and when one of the scan signal and the reset signal of the pixel is abnormal or malfunctions, the protection circuit can turn off the abnormal pixel, so as to reduce the problem of diode element damage in the pixel caused by short circuit or high current.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the disclosed embodiments.

Claims

1. An electronic device, comprising:

a pixel circuit including a driving transistor; and

a protection circuit, comprising:

a first connection transistor coupled to the driving transistor;

a first switch transistor coupled to the first connection transistor; and

a logic circuit coupled to the first switching transistor.

2. The electronic device of claim 1, wherein the pixel circuit further comprises:

a pixel switching transistor coupled to the driving transistor and receiving a control signal; and

a diode element coupled to the pixel switching transistor,

wherein the first switching transistor receives the control signal.

3. The electronic device of claim 1, wherein the pixel circuit further comprises:

a first scan transistor coupled to the driving transistor and receiving a scan signal,

wherein the logic circuit receives the scan signal.

4. The electronic device of claim 1, wherein the pixel circuit further comprises:

a first reset transistor coupled to the driving transistor and receiving a reset signal,

wherein the logic circuit receives the reset signal.

5. The electronic device of claim 1, wherein the logic circuit comprises:

a second connection transistor coupled between the first switching transistor and a first reference voltage; and

and a switching circuit coupled to the second connection transistor and receiving at least one of a scan signal and a reset signal.

6. The electronic device of claim 5, wherein the logic circuit further comprises:

a second switching transistor coupled to the first reference voltage,

wherein the switching circuit is coupled between the second switching transistor and the second connecting transistor.

7. The electronic device of claim 6, wherein the switching circuit comprises at least one of a second scan transistor and a second reset transistor for receiving at least one of the scan signal and the reset signal and determining whether to provide the first reference voltage to the second connection transistor according to at least one of the scan signal and the reset signal.

8. The electronic device of claim 5, wherein the protection circuit further comprises:

an impedance circuit coupled to a circuit node between the first switching transistor and the second connecting transistor.

9. The electronic device of claim 8, wherein the protection circuit further comprises:

a third switching transistor coupled between the circuit node and the impedance circuit.

10. The electronic device of claim 8, wherein the protection circuit further comprises:

a third switching transistor coupled between the circuit node and the second connecting transistor.