CN111274180A - Aurora and Rapid IO interface conversion device - Google Patents
Aurora and Rapid IO interface conversion device Download PDFInfo
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- CN111274180A CN111274180A CN202010054421.8A CN202010054421A CN111274180A CN 111274180 A CN111274180 A CN 111274180A CN 202010054421 A CN202010054421 A CN 202010054421A CN 111274180 A CN111274180 A CN 111274180A
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- 239000005441 aurora Substances 0.000 title claims abstract description 32
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 27
- 238000004458 analytical method Methods 0.000 claims abstract description 14
- 238000012423 maintenance Methods 0.000 claims abstract description 7
- 238000004806 packaging method and process Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 9
- 239000000284 extract Substances 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 5
- 238000007405 data analysis Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000009432 framing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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Abstract
The invention provides an Aurora and Rapid IO interface conversion device, which belongs to the field of data transmission equipment. The protocol conversion and interconnection module comprises a data message analysis module, a data distribution module, a message packaging module, an ID table maintenance module and an ID message analysis module. The device can share the data of each chip, is convenient for managing the system and simultaneously improves the flexibility of the system.
Description
Technical Field
The invention relates to data transmission equipment, in particular to an Aurora and Rapid IO interface conversion device.
Background
FPGA (field Programmable Gate array), namely a field Programmable Gate array, has high flexibility, and meanwhile, the FPGA has abundant I/O pins, so that the FPGA has short development period and higher reliability compared with an ASIC (application specific integrated circuit).
Aurora is an extensible lightweight link layer protocol for moving data between point-to-point serial links. This provides a transparent interface to the physical layer, allowing the proprietary protocol or industry standard protocol upper layers to conveniently use the high speed transceiver.
The main characteristics are as follows:
high bandwidth, limited only by the data rate of the transceiver,
supporting a large number of bonding wires, achieving a higher total bandwidth,
supports full duplex and simplex channels,
infinite frame size/flexible framing,
a small logic package, using a standard AXI-ST interface,
built-in flow control and hot plug support.
The high-speed Aurora interface bus is a high-speed serial bus, Aurora is widely applied to applications requiring connection among backplanes, circuit boards and chips, and has high expansibility, but a method for interconnecting a high-speed Aurora interface and a RapidIO interface is still absent in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides an Aurora and Rapid IO interface conversion device, and the device using the interconnection method has the characteristics of high data transmission speed, online configurable priority and high flexibility.
The technical scheme of the invention is as follows:
an Aurora and Rapid IO interface conversion device comprises an FPGA chip, an Aurora interface module, a Rapid IO interface module and a protocol conversion and interconnection module; the Aurora interface module, the Rapid IO interface module and the protocol conversion and interconnection module are arranged in the FPGA chip,
wherein;
the Aurora interface module is used for transmitting and receiving data by the FPGA and more than one chip with Aurora interfaces;
the Rapid IO module is used for the FPGA and more than one chip with a Rapid IO interface to send and receive data;
and the protocol conversion and interconnection module is matched with the input and output data to route the data entering the FPGA.
Further, in the above-mentioned case,
data of each source device passes through the Aurora interface module, the Aurora interface module transmits the data to the protocol conversion and interconnection module through the FIFO, the ID of the data is matched by matching with the ID table maintenance module after passing through the protocol conversion and interconnection module, and the successfully matched data is packaged into a Rapid IO protocol format and is transmitted to each Rapid IO device.
In a still further aspect of the present invention,
and the Aurora interface module simulates read-write control of Aurora according to the interface time sequence of Aurora.
The data of the FPGA is sent and received according to the format of a data head, data and a data tail, wherein the data head comprises a head indicating signal, a source device ID, a destination device ID and a data mark.
The data trailer has a CRC in addition to the trailer indication signal.
When data enter the FPGA from the external chip, the protocol conversion and interconnection module compares the analyzed information of the data with the information of the ID table, and determines the flow direction of the data according to the comparison result.
If two data enter the protocol conversion and interconnection module at the same time, the conversion sequence of the data is determined according to the priority in the ID table, if the priority can not be determined after the comparison of the routing table, the priority is determined according to the size of the ID by adopting a time division multiplexing method, and the ID is sent first when the ID is small.
In a still further aspect of the present invention,
the protocol conversion and interconnection module comprises a data message analysis module, a data distribution module, a message packaging module, an ID table maintenance module and an ID message analysis module;
the data message analysis module analyzes data, firstly extracts a source device ID, a destination device ID, a data length and a data mark in the data, and then analyzes CRC at the tail of the data to determine the correctness of the data, if the CRC is incorrect, the source device needs to resend the data;
the data distribution module arbitrates data by adopting a time division multiplexing method and a priority method according to a maintainable ID table;
the message packaging module is used for carrying out reverse operation on the data message analysis module;
the ID table maintenance module can select two forms of fixed exchange and upper layer issuing according to application requirements, and the content of the ID table comprises a source device ID, a target device ID, a priority and a data mark;
the ID table is issued and updated by an external CPU issuing module.
And the ID message analysis module analyzes the ID data issued by the CPU, wherein the ID message comprises the ID data, the data length and the crc, and the ID message analysis module strips the ID data from the ID message.
The invention has the advantages that
In a system containing an Aurora interface and a Rapid IO interface, the device can be used for sharing data of each chip, thereby facilitating system management and simultaneously improving the flexibility of the system.
Drawings
Fig. 1 is a working block diagram of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention, and based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the scope of the present invention.
As shown in fig. 1, firstly, according to the system requirement, the FPGA fixes the routing table in a fixed format in the external memory of the CPU, or issues the routing table to the FPGA through the routing issue module in the form of an upper computer, and a plurality of chips connected to the FPGA prepare data to be sent, where the data conforms to such a format: data head + data tail.
The data head contains the source ID and destination ID of the chip and the priority, and the data tail is CRC. The chip sends the data to the FPGA according to the Aurora time sequence, the FPGA can realize a plurality of Aurora interfaces for receiving the data sent by the chips and calculating the CRC of the data, if the received data is wrong, the chip at the opposite end is informed to resend the data, and the wrong data at the moment can enter a protocol conversion and interconnection module and is discarded.
If the received data is not wrong, the FPGA receives the data and then sends the data to the data analysis module, the parameters such as the source ID, the destination ID and the like in the data are extracted, the parameters are compared with the parameters in the routing table, and the FPGA sends the data to the corresponding data packaging module according to the comparison result.
The data distribution module processes the data of the plurality of chips according to a first-come first-serve principle, and when the data are processed, the data sent by other chips are cached in the FIFO to wait for the first-come data to be processed. If the data sent by the chips with different source IDs arrive at the same time, the data to be forwarded preferentially is determined according to the priority in the data analysis module, if the priorities are the same, the data to be processed preferentially is determined according to the numerical value of the source ID of the data, other data are cached in the FIFO at the moment, according to a time division multiplexing algorithm, the forwarding of the previous data is waited to be completed, and then the data forwarding of the other source ID is carried out.
When data transmission in the FPGA has errors, the FPGA sends corresponding error codes to the CPU, the CPU selects to clear the errors or terminate the FPGA data transmission according to the error codes, resets the FPGA and records the error codes into a log.
The above description is only a preferred embodiment of the present invention, and is only used to illustrate the technical solutions of the present invention, and not to limit the protection scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (8)
1. An Aurora and Rapid IO interface conversion device is characterized in that,
the system comprises an FPGA chip, an Aurora interface module, a Rapid IO interface module and a protocol conversion and interconnection module; the Aurora interface module, the Rapid IO interface module and the protocol conversion and interconnection module are arranged in the FPGA chip,
wherein;
the Aurora interface module is used for transmitting and receiving data by the FPGA and more than one chip with Aurora interfaces;
the Rapid IO module is used for the FPGA and more than one chip with a Rapid IO interface to send and receive data;
and the protocol conversion and interconnection module is matched with the input and output data to route the data entering the FPGA.
2. The apparatus of claim 1,
data of each source device passes through the Aurora interface module, the Aurora interface module transmits the data to the protocol conversion and interconnection module through the FIFO, the ID of the data is matched by matching with the ID table maintenance module after passing through the protocol conversion and interconnection module, and the successfully matched data is packaged into a Rapid IO protocol format and is transmitted to each Rapid IO device.
3. The apparatus of claim 2,
and the Aurora interface module simulates read-write control of Aurora according to the interface time sequence of Aurora.
4. The apparatus of claim 2,
the data of the FPGA is sent and received according to the format of a data head, data and a data tail, wherein the data head comprises a head indicating signal, a source device ID, a destination device ID and a data mark.
5. The apparatus of claim 4,
the data trailer has a CRC in addition to the trailer indication signal.
6. The apparatus of claim 2,
when data enter the FPGA from the external chip, the protocol conversion and interconnection module compares the analyzed information of the data with the information of the ID table, and determines the flow direction of the data according to the comparison result.
7. The apparatus of claim 6,
if two data enter the protocol conversion and interconnection module at the same time, the conversion sequence of the data is determined according to the priority in the ID table, if the priority can not be determined after the comparison of the routing table, the priority is determined according to the size of the ID by adopting a time division multiplexing method, and the ID is sent first when the ID is small.
8. The apparatus of claim 7,
the protocol conversion and interconnection module comprises a data message analysis module, a data distribution module, a message packaging module, an ID table maintenance module and an ID message analysis module;
the data message analysis module analyzes data, firstly extracts a source device ID, a destination device ID, a data length and a data mark in the data, and then analyzes CRC at the tail of the data to determine the correctness of the data, if the CRC is incorrect, the source device needs to resend the data;
the data distribution module arbitrates data by adopting a time division multiplexing method and a priority method according to a maintainable ID table;
the message packaging module is used for carrying out reverse operation on the data message analysis module;
the ID table maintenance module can select two forms of fixed exchange and upper layer issuing according to application requirements, and the content of the ID table comprises a source device ID, a target device ID, a priority and a data mark;
the ID table is issued and updated by an external CPU issuing module.
And the ID message analysis module analyzes the ID data issued by the CPU, wherein the ID message comprises the ID data, the data length and the crc, and the ID message analysis module strips the ID data from the ID message.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010054421.8A CN111274180A (en) | 2020-01-17 | 2020-01-17 | Aurora and Rapid IO interface conversion device |
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| CN202010054421.8A CN111274180A (en) | 2020-01-17 | 2020-01-17 | Aurora and Rapid IO interface conversion device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113722250A (en) * | 2021-09-15 | 2021-11-30 | 上海赛治信息技术有限公司 | Two-way redundant data exchange method and system based on Aurora protocol |
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2020
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