CN110113265A - More I2C interface interconnected methods and module based on FPGA - Google Patents
More I2C interface interconnected methods and module based on FPGA Download PDFInfo
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- CN110113265A CN110113265A CN201910406279.6A CN201910406279A CN110113265A CN 110113265 A CN110113265 A CN 110113265A CN 201910406279 A CN201910406279 A CN 201910406279A CN 110113265 A CN110113265 A CN 110113265A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/06—Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a kind of more I2C interface interconnected methods and module based on FPGA, belong to data message transmission field, technical problems to be solved are how to realize the high-speed transfer of data between multiple chips with I2C interface, and realize that data transfer procedure priority is configurable.Its method includes: to receive data message by I2C interface；The data message of acquisition is parsed, the routing parameter of data message is extracted；Processing is forwarded to the data message after parsing, routing parameter that data message parses is compared with the routing parameter in configurable swap table, by comparison result by data message forwarding to corresponding chip.Its module includes FPGA plate and the I2C interface submodule being configured on FPGA plate, packet parsing submodule and interconnecting and switching submodule.The present invention can be achieved to interconnect between multiple chips with I2C interface.
Description
Technical field
The present invention relates to data messages to transmit field, specifically a kind of more I2C interface interconnected methods based on FPGA
And module.
Background technique
I2C bus is a kind of simple, bidirectional two-line synchronous serial bus.It only needs both threads that can be connected to always
Information is transmitted between device on line.Main device generates the device that clock is transmitted with opening for starting bus transmissioning data,
It is not constant that the device being addressed any at this time, which is regarded as advocating peace in bus from device from, hair and the relationship received, and
Depending on data transmission direction at this time.If host will be sent data to from device, host is addressed from device first, is then led
It is dynamic to send data to from device, data transmission is finally terminated by host；If host will receive the data from device, first by leading
From device, then host receives the data sent from device for device addressing, finally terminates receive process by host.In such case
Lower host is responsible for generating timer clock and terminates data transmission.
FPGA (FieldProgrammable Gate Array), i.e. field programmable gate array have very high flexible
Property, while FPGA has I/O pin abundant, short relative to the ASIC development cycle, reliability is higher.
How above-mentioned advantage based on FPGA realizes the high-speed transfer of data between multiple chips with I2C interface, and
It realizes that data transfer procedure priority is configurable, is the technical issues that need to address.
Summary of the invention
Technical assignment of the invention be against the above deficiency, provide a kind of more I2C interface interconnected methods based on FPGA and
Module to solve how to realize the high-speed transfer of data between multiple chips with I2C interface, and realizes data transfer procedure
The configurable problem of priority.
In a first aspect, the present invention provides a kind of more I2C interface interconnected methods based on FPGA, exist for realizing data message
Forwarding between multiple chips with I2C interface, comprising:
Data message is received by I2C interface, the format of the data message is heading+data+message trailer, heading
Including source ID, purpose ID and priority, message trailer includes CRC；
The data message of acquisition is parsed, the routing parameter of data message is extracted, routing parameter includes source ID, purpose
ID and priority；
Processing is forwarded to the data message after parsing, the routing parameter that data message is parsed and configurable
Routing parameter in swap table is compared, by comparison result by data message forwarding to corresponding chip.
In the above-described embodiment, it is pre-configured with swap table, includes routing parameter in swap table, after message data is parsed
Routing parameter and swap table in routing parameter compare, and according to comparing result by data message forwarding to corresponding core
Piece, to realize the interconnection between multiple chips with I2C interface.When swap table is maintainable swap table, pass through
The priority level of data message can be artificially arranged in the swap table of configuration；When the interaction configuration for closing swap table, swap table is fixed
When writing extremely in FPGA, according to the mark extracted from data message in swap table, it may be determined that the corresponding number of the data message
According to for top-secret data, so as to carry out unidirectional import operation to data.
More preferably, after receiving data message by I2C interface, the CRC of data message is calculated, and data are judged according to CRC
Whether message is wrong, and wrong data message is abandoned, is parsed to errorless data message.
Before data packet parsing, judged whether by the CRC of data message it is wrong, improve data message transmission
Accuracy rate and speed.
Preferably, the data message after parsing is cached in when receiving the data message of multiple chips by I2C interface
Fifo buffer, and processing is forwarded to the data message after multiple parsings based on the principle first handled is arrived first.
In the above-described embodiment, it supports the transmission of data message between multiple chips with I2C interface, and supports more
A chip transmits data message simultaneously.
Preferably, when receiving the data message of multiple chips simultaneously by I2C interface, if the multiple chip is sent
Data message priority it is different, processing is forwarded to the data message after parsing based on priority；
If the priority of the multiple data message is identical, the data message after parsing is turned based on source ID numerical value
Hair processing, and according to time division multiplexing algorithm, after the data message forwarding processing after the corresponding parsing of a upper source ID, to next
Data message after the corresponding parsing of a source ID is forwarded processing.
Preferably, heading further includes header indicatingjhe number and message flag, message trailer further includes tail portion indication signal.
Second aspect, the present invention provide a kind of more I2C interface interconnection modules based on FPGA, exist for realizing data message
Forwarding between multiple chips with I2C interface including FPGA plate and is configured on FPGA plate:
I2C interface submodule, message, the format of data message are heading+data+message trailer, report for receiving data
Literary head includes source ID, purpose ID and priority, and message trailer includes CRC；
Packet parsing submodule for parsing to data message, and extracts routing parameter, and routing parameter includes source
ID, purpose ID and priority；
Interconnecting and switching submodule, is configured with moderator and swap table, and moderator is used for the road for parsing data message
It is compared by parameter with the routing parameter in swap table, and crosses comparison result for data message forwarding to corresponding chip.
More preferably, further includes:
Judging submodule is connect with I2C interface submodule, packet parsing submodule and interconnecting and switching submodule respectively,
Judge whether data message is wrong for calculating the CRC of data message, and according to the CRC of data message, and by nothing
Data message accidentally is sent to packet parsing submodule, and wrong data message is sent to interconnecting and switching submodule；
Interconnecting and switching submodule is for losing wrong data message.
More preferably, further includes:
Fifo buffer is connected between packet parsing submodule and interconnecting and switching submodule, for passing through I2C interface
Data message when receiving the data message of multiple chips, after buffering parsing.
Preferably, when receiving the data message of multiple chips simultaneously by I2C interface, if received multiple chips
The priority of data message is different, and moderator is used to be forwarded processing to the data message after parsing based on priority；
If the priority of the data message of received multiple chips is identical, moderator is used for based on source ID numerical value to parsing
Data message afterwards is forwarded processing, and the datagram according to time division multiplexing algorithm, after the corresponding parsing of a upper source ID
After literary forward process, processing is forwarded to the data message after the corresponding parsing of next source ID.
Of the invention more I2C interface interconnected methods and system based on FPGA have the advantage that
1, based on FPGA construct interconnection module, the routing parameter for being parsed data message by the interconnection module with can
Routing parameter in the swap table of configuration is compared, by comparison result by data message forwarding to corresponding chip, so that
Data transmission bauds is fast；
2, in swap table include routing parameter, by configure swap table can Configuration Online priority so that chip it
Between data-message transmission strong flexibility；
3, the configuration for closing swap table can be according to the data mark being arranged in swap table when being fixed on swap table in FPGA
Will determines that corresponding data message realizes the logic isolation of data to carry out individual event import operation to data for top-secret data.
Detailed description of the invention
It, below will be to required in being described in embodiment in order to more clearly illustrate the technical solution in the embodiment of the present invention
The attached drawing used is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those skilled in the art, without creative efforts, it can also be obtained according to these attached drawings
His attached drawing.
The following further describes the present invention with reference to the drawings.
Attached drawing 1 is the flow diagram of more I2C interface interconnected methods of the embodiment 1 based on FPGA；
Attached drawing 2 is the structural block diagram of more I2C interface interconnection modules of the embodiment 2 based on FPGA.
Specific embodiment
The present invention will be further explained below with reference to the attached drawings and specific examples, so that those skilled in the art can be with
It more fully understands the present invention and can be practiced, but illustrated embodiment is not as a limitation of the invention, the case where not conflicting
Under, the technical characteristic in the embodiment of the present invention and embodiment can be combined with each other.
It is to be appreciated that " multiple " in embodiments of the present invention, refer to two or more.
The embodiment of the present invention provides more I2C interface interconnected methods and module based on FPGA, more for solving how to realize
The high-speed transfer of data between a chip with I2C interface, and realize that the configurable technology of data transfer procedure priority is asked
Topic.
Embodiment 1:
As shown in Fig. 1, more I2C interface interconnected methods of the invention based on FPGA are applied to configured with I2C interface
The FPGA plate of module, packet parsing submodule and interconnecting and switching submodule has I2C interface multiple for realizing data message
Chip between forwarding, the format of the data message is heading+data+message trailer, heading include header indicatingjhe number,
Source ID, purpose ID, priority and message flag, message trailer include tail portion Warning Mark and CRC.
The interconnected method includes:
S100, data message is received by I2C interface；
S200, the data message of acquisition is parsed, extracts the routing parameter of data message, routing parameter includes source
ID, purpose ID and priority；
S300, processing is forwarded to the data message after parsing, the routing parameter that data message is parsed with can
Routing parameter in the swap table of configuration is compared, by comparison result by data message forwarding to corresponding chip.
In step S300, processing is forwarded to data message based on the principle first handled is arrived first.
In multiple chip interconnection process, the case where sending datagram simultaneously there are multiple chips, therefore in FPGA core
FIFO buffer area is also configured in piece, when receiving the data message of multiple chips by I2C interface, by the datagram after parsing
Text is cached in fifo buffer, and is forwarded processing to the data message after multiple parsings based on the principle first handled is arrived first.
If when the priority difference of multiple data messages, being forwarded place to the data message after parsing based on priority
Reason；If the priority of the multiple data message is identical, place is forwarded to the data message after parsing based on source ID numerical value
Reason, it is preferential to forward the lesser data message of source ID, and the number according to time division multiplexing algorithm, after the corresponding parsing of a upper source ID
After message forward process, processing is forwarded to the data message after the corresponding parsing of next source ID.
In view of received data message, there may be mistakes, and judging submodule is configured in FPGA plate, pass through judgement
Module calculates the CRC of data message, judges whether data message is wrong according to CRC, wrong data message is sent to interconnection
Submodule is exchanged, wrong data message is abandoned by interconnecting and switching submodule, errorless data message is sent to message
Analyzing sub-module parses errorless data message by packet parsing submodule.
More I2C interface interconnected methods based on FPGA of the invention, it can be achieved that data message multiple with I2C interface
Forwarding between chip, to realize the interconnection of multiple chips with I2C interface.
Embodiment 2:
As shown in Fig. 2, a kind of more I2C interface interconnection modules based on FPGA of the invention, including FPGA plate and match
I2C interface submodule, packet parsing submodule and the interconnecting and switching submodule being placed on FPGA plate, I2C interface submodule are used for
Receive data message, the format of data message is heading+data+message trailer, heading include header indicatingjhe number, source ID,
Purpose ID, priority and message flag, message trailer include tail portion indication signal and CRC；Packet parsing submodule is used for data
Message is parsed, and extracts routing parameter, and routing parameter includes source ID, purpose ID and priority；Interconnecting and switching submodule is matched
It is equipped with moderator and swap table, the routing parameter in routing parameter and swap table that moderator is used to parse data message
It is compared, and crosses comparison result for data message forwarding to corresponding chip.
Wherein, moderator is forwarded processing to data message based on the principle first handled is arrived first
In multiple chip interconnection process, the case where sending datagram simultaneously there are multiple chips, therefore in FPGA core
FIFO buffer area is also configured in piece, FIFO buffer area is connected between packet parsing submodule and interconnecting and switching submodule.When
When receiving the data message of multiple chips by I2C interface, the datagram after above-mentioned multiple parsings is cached by fifo buffer
Text, moderator are forwarded processing to the data message after multiple parsings based on the principle first handled is arrived first.
If the priority of above-mentioned multiple data messages is different, moderator is used for based on priority to the datagram after parsing
Text is forwarded processing；If the priority of above-mentioned multiple data messages is identical, moderator based on source ID numerical value to parsing after
Data message is forwarded processing, preferential to forward the lesser data message of source ID, and according to time division multiplexing algorithm, to a upper source
After data message forwarding processing after the corresponding parsing of ID, the data message after the corresponding parsing of next source ID is forwarded
Processing.
In view of received data message, there may be mistakes, and judging submodule, judging submodule are configured in FPGA plate
It is connect respectively with I2C interface submodule, packet parsing submodule and interconnecting and switching submodule, judging submodule is for calculating data
The CRC of message, and judge whether data message is wrong according to the CRC of data message, and errorless data message is sent to report
Wrong data message is sent to interconnecting and switching submodule by literary analyzing sub-module；Interconnecting and switching submodule will be for that will have at this time
Data message accidentally is lost.
More I2C interface interconnection modules based on FPGA of the invention, can by disclosed in embodiment 1 based on the more of FPGA
I2C interface interconnected method to realize multiple interconnections with I2C interface, and realizes that data are quickly transmitted between chip, and supports
Priority is configurable.
Embodiment described above is only to absolutely prove preferred embodiment that is of the invention and being lifted, protection model of the invention
It encloses without being limited thereto.Those skilled in the art's made equivalent substitute or transformation on the basis of the present invention, in the present invention
Protection scope within.Protection scope of the present invention is subject to claims.
Claims (9)
1. more I2C interface interconnected methods based on FPGA, it is characterised in that there is I2C interface multiple for realizing data message
Chip between forwarding, comprising:
Data message is received by I2C interface, the format of the data message is heading+data+message trailer, and heading includes
Source ID, purpose ID and priority, message trailer include CRC；
The data message of acquisition is parsed, extracts the routing parameter of data message, routing parameter include source ID, purpose ID and
Priority；
Processing is forwarded to the data message after parsing, the routing parameter that data message parses is exchanged with configurable
Routing parameter in table is compared, by comparison result by data message forwarding to corresponding chip.
2. more I2C interface interconnected methods according to claim 1 based on FPGA, it is characterised in that connect by I2C interface
After receiving data message, the CRC of data message is calculated, and judge whether data message is wrong according to CRC, by wrong data message
It abandons, errorless data message is parsed.
3. more I2C interface interconnected methods according to claim 1 or 2 based on FPGA, it is characterised in that pass through I2C interface
When receiving the data message of multiple chips, the data message after parsing is cached in fifo buffer, and first handle based on arriving first
Principle processing is forwarded to the data message after multiple parsings.
4. more I2C interface interconnected methods according to claim 3 based on FPGA, it is characterised in that same by I2C interface
When receiving the data message of multiple chips, if the priority for the data message that the multiple chip is sent is different, based on excellent
First grade is forwarded processing to the data message after parsing；
If the priority of the multiple data message is identical, place is forwarded to the data message after parsing based on source ID numerical value
Reason, and according to time division multiplexing algorithm, after the data message forwarding processing after the corresponding parsing of a upper source ID, to next source
Data message after the corresponding parsing of ID is forwarded processing.
5. more I2C interface interconnected methods according to claim 1 or 2 based on FPGA, it is characterised in that heading also wraps
Header indicatingjhe number and message flag are included, message trailer further includes tail portion indication signal.
6. more I2C interface interconnection modules based on FPGA, it is characterised in that there is I2C interface multiple for realizing data message
Chip between forwarding, including FPGA plate and be configured on FPGA plate:
I2C interface submodule, message, the format of data message are heading+data+message trailer, heading for receiving data
Including source ID, purpose ID and priority, message trailer includes CRC；
Packet parsing submodule for parsing to data message, and extracts routing parameter, and routing parameter includes source ID, mesh
ID and priority；
Interconnecting and switching submodule, is configured with moderator and swap table, and the routing that moderator is used to parse data message is joined
Number is compared with the routing parameter in swap table, and crosses comparison result for data message forwarding to corresponding chip.
7. according to more I2C interface interconnection modules based on FPGA of claim 6, it is characterised in that further include:
Judging submodule is connect with I2C interface submodule, packet parsing submodule and interconnecting and switching submodule respectively,
Judge whether data message is wrong for calculating the CRC of data message, and according to the CRC of data message, and will be errorless
Data message is sent to packet parsing submodule, and wrong data message is sent to interconnecting and switching submodule；
Interconnecting and switching submodule is for losing wrong data message.
8. the more I2C interface interconnection modules based on FPGA stated according to claim 6 or 7, it is characterised in that further include:
FIFO buffer area is connected between packet parsing submodule and interconnecting and switching submodule, for receiving by I2C interface
The data message when data message of multiple chips, after buffering parsing.
9. more I2C interface interconnection modules according to claim 9 based on FPGA, it is characterised in that same by I2C interface
When receiving the data message of multiple chips, if the priority of the data message of received multiple chips is different, moderator is used
In being forwarded processing to the data message after parsing based on priority；
If the priority of the data message of received multiple chips is identical, moderator be used for based on source ID numerical value to parsing after
Data message is forwarded processing, and according to time division multiplexing algorithm, the data message after the corresponding parsing of a upper source ID turns
After hair processing, processing is forwarded to the data message after the corresponding parsing of next source ID.
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| CN111274180A (en) * | 2020-01-17 | 2020-06-12 | 济南浪潮高新科技投资发展有限公司 | Aurora and Rapid IO interface conversion device |
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