CN106411463B - A kind of high-speed data transmission apparatus and method based on asynchronous clock - Google Patents
A kind of high-speed data transmission apparatus and method based on asynchronous clock Download PDFInfo
- Publication number
- CN106411463B CN106411463B CN201610765794.XA CN201610765794A CN106411463B CN 106411463 B CN106411463 B CN 106411463B CN 201610765794 A CN201610765794 A CN 201610765794A CN 106411463 B CN106411463 B CN 106411463B
- Authority
- CN
- China
- Prior art keywords
- data
- unit
- clock
- signal
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
Abstract
The invention discloses a kind of high-speed data transmission apparatus based on asynchronous clock, including control unit, transmission unit sends ram cell, receives ram cell, signal conversion unit, clock unit, asks or output unit and multiple data recovery units and communication channel；Its transmission method is also disclosed, the method for the present invention not only can reliably restore high-speed data, and baud rate can be adjusted flexibly according to device, adaptable.
Description
Technical field
The invention belongs to industrial control field more particularly to a kind of high-speed data transmission apparatus and side based on asynchronous clock
Method is mainly used for solving the transmission problem of industrial control field high speed real time data.
Background technique
Industrial control field it is currently a popular the communication protocol of multiple standards, such as RS485, RS232, CAN, communication
The highest RS484 of rate generally also works in 10M hereinafter, so cannot be used for transmitting high speed data.Ethernet can reach
The communication speed of 100M or more, but the CSMA/CD access mechanism in agreement causes real-time and not can guarantee, and is unsuitable for for work
Control field.
In high speed data transfer field, SERDES technology is in occupation of the status of monopolization, transmission rate generally Gbit with
On, this device, chip etc. for resulting in adaptation have very high requirement, so that the rising of its cost is caused, in terms of versatility
Also weaker.
There is the technology that data recovery is carried out using the method for over-sampling in existing data recovery technique, but it is generallyd use
Be clock and data recovery algorithm (CDR), if thinking accurately to realize that CDR must just avoid the 0 or 1 of continuous multidigit.This will have
Complicated coding and decoding means, and the algorithm of clock and data recovery is also very complicated, results in entire technology in this way and realizes very
It is complicated.
Summary of the invention
In order to solve the data transmission problems of 100,000,000 ranks in industrial control field, an object of the present invention is to provide one
High-speed data transmission apparatus of the kind based on asynchronous clock.
The technical solution adopted by the present invention to solve the technical problems is: a kind of high speed data transfer based on asynchronous clock
Device, including a control unit, the transmitting-receiving for completing data controls and the assembling and parsing of data frame；One transmission
Unit, for carrying out data output；One transmission ram cell and a reception ram cell are mentioned for buffering to data
The efficiency and reliability that high transceiver channel is docked with control unit；One signal conversion unit, the Signal Matching for physical layer；
One clock unit, for exporting the same frequency clock of multiple difference certain angles；One is asked or output unit and multiple data
Recovery unit and multiple communication channels, each data recovery unit carry out data sampling with different clocks respectively and resume work.
The number of a kind of high-speed data transmission apparatus based on asynchronous clock, data recovery unit is not less than four
It is a.
A kind of high-speed data transmission apparatus based on asynchronous clock, communication channel receive LVDS, BLVDS or light
Optical fiber signaling.
A kind of high-speed data transmission apparatus based on asynchronous clock, data recovery unit include sampling unit,
Preamble detecting unit, dual port RAM and verification unit；The sampling unit is used for sampled data, and the dual port RAM supports master
Control logic works under different frequencies from data acceptance logic and realizes asynchronous working, and the preamble detecting unit is detecting
By when data buffer storage verified into dual port RAM, and to data, verification by then indicate to receive correct data and on
Data are passed, data are otherwise abandoned.
It is a kind of using time sharing sampling technology the second object of the present invention is to provide, so that can be right in same frequency asynchronous clock domain
The high-speed data transmission method based on asynchronous clock that high-speed data is reliably restored.
The technical solution adopted by the present invention to solve the technical problems is: a kind of high speed data transfer based on asynchronous clock
Method includes the following steps
A), data are filled into according to setting frame format and send in ram cell by control unit, and then starting sends instruction；
B), transmission unit sends data in the rising edge of tranmitting data register after receiving transmission instruction, mono- until sending RAM
Data in member are by until having sent；
C), signal conversion unit changes the Bit circulation that transmission unit is sent into physical link corresponding signal, passes through transmission
Channel is sent to recipient, completes transmission process；
D), after receiving channel receives external input signal, signal conversion unit is first passed around, then by the signal after conversion
It send into chip；
E), the signal for being sent into chip is sent simultaneously at most a data recovery unit, and sampling unit is based on respective reception
Clock carries out data recovery.
Further, the data frame packet contains beginning flag, frame head, address field, variable length data section, check field.
Further, the beginning that data frame is indicated when sampling unit detects specific frame head starts data buffer storage to receipts
In mouth RAM；Verification unit verifies data after frame has received, and can be CRC, sum check etc., when verification passes through, indicate
Data have correctly been restored in this channel, verification not by when abandon data.
Further, data recovery unit is with asking or correct data are transmitted in ram cell by output unit.
Further, control unit receives the reading of data according to the ready signal-obtaining that reception ram cell is sent,
Be finally completed entire data sends and receives recovery
The beneficial effects of the present invention are: control unit completes the transmitting-receiving control of data when work, sends ram cell and connect
The caching that ram cell is responsible for data is received, transmission unit and data recovery unit are each responsible for sending and receiving for data, and signal turns
The Signal Matching work that unit is responsible for physical layer is changed, high-speed data Transmit-Receive Unit only just need to can complete data according to local clock
Work is received and dispatched, the other end of communication also must be interfaced using identical high-speed data Transmit-Receive Unit.
Data transmit-receive is all made of the identical local clock of frequency in transmission method, and a tranmitting data register is 360 °, sends logical
Road sends data in the rising edge of clock, and receiving channel is equipped with n receiving unit, the sampling clock of the sampling unit of each unit
360/n degree is successively differed, to guarantee that data at least can correctly be restored by a unit, is finally reached the data that verification passes through
Control unit.
Compared with prior art, traffic rate of the invention is significantly enhanced, and traffic rate can be with factually border feelings
Condition flexibly determines, adaptable；Communication protocol can customize；Programming difficulty is reduced, can be realized in common fpga chip,
It realizes simple；To high-speed data not only high efficient and reliable, and baud rate can voluntarily be adjusted according to device, there is very strong flexibility.
Detailed description of the invention
Fig. 1 is the structural block diagram of high-speed data transmission apparatus of the present invention；
Fig. 2 is the logic function connection relationship diagram of high-speed data transmission and unit；
Connection schematic diagram of the Fig. 3 between high-speed data Transmit-Receive Unit.
Specific embodiment
In order to more clearly illustrate the present invention program, summary of the invention is carried out with example with reference to the accompanying drawing further
Explanation.It should be appreciated that described herein is specifically that the examples are only for explaining the invention, protection scope is not limited to described
Example.
Shown in referring to Fig.1, the invention discloses a kind of high-speed data transmission apparatus based on asynchronous clock, including
One control unit, the transmitting-receiving for completing data controls and the assembling and parsing of data frame.
One transmission unit carries out data output for the rising edge (or failing edge) in clock, by signal when no output
It is set to often high (or often low).
One transmission ram cell and a reception ram cell, for being buffered to data, with improve transceiver channel with
The efficiency and reliability of control unit docking.
One signal conversion unit, the Signal Matching for physical layer.
One clock unit, for exporting the same frequency clock of multiple difference certain angles, clock unit requires to have enough
Precision.
One is asked or output unit and multiple data recovery units and multiple communication channels, each data recovery unit point
Data sampling is not carried out with different clocks to resume work；If data recovery unit number is n(n >=4), the work of each unit
Making clock interval is 360/n degree, and data transmit-receive is all made of the identical local clock of frequency, and a tranmitting data register period is 360 °,
Sendaisle sends data in rising edge clock, and receiving channel is equipped with n receiving unit, the sampling clock of each unit successively phase
Poor 360 °/n, to guarantee that data at least can correctly be restored by a unit, it is single that the data that verification passes through finally are reached control
Member.
Wherein, the number of the data recovery unit is not less than four.
Wherein, the communication channel is using LVDS, BLVDS or fiber-optic signal, the modes such as communication channel uses, it is desirable that full
Sufficient high-speed and anti-interference ability demand.
In addition, the data recovery unit includes sampling unit, preamble detecting unit, dual port RAM and verification unit；Institute
The sampling unit stated is used for rising edge (or failing edge) sampled data in respective clock, and the dual port RAM supports main control
Logical AND data acceptance logic, which works under different frequencies, realizes asynchronous working, and the preamble detecting unit passes through in detection
When data buffer storage is verified into dual port RAM, and to data, verification by then indicate receive correct data and upload number
According to otherwise abandoning data.
When work, control unit completes the transmitting-receiving control of data, sends ram cell and receives ram cell and is responsible for data
Caching, transmission unit and data recovery unit are each responsible for sending and receiving for data, and signal conversion unit is responsible for physical layer
Signal Matching work, high-speed data Transmit-Receive Unit just need to can only complete the transmitting-receiving work of data according to local clock, communication it is another
It one end also must be interfaced using identical high-speed data Transmit-Receive Unit.
It is provided by the invention to restore that frame head is cooperated to add the implementation method of verification not only simple and reliable using multichannel, and pass through
Dual port RAM realizes being isolated for transceiver channel and primary logical unit, both can make work in different clock domains.In addition lead to
It crosses and the reliability and anti-interference ability of this technological means is also enhanced to the optimization means of physical layer link, have more practical valence
Value.
Referring to shown in Fig. 2, a kind of high-speed data transmission method based on asynchronous clock includes the following steps:
A), data are filled into according to setting frame format and send in ram cell by control unit, and then starting sends instruction,
The data frame packet contains beginning flag, frame head, address field, variable length data section, check field；
B), transmission unit sends data in the rising edge of tranmitting data register after the transmission instruction for receiving control unit, until
The data in ram cell are sent by until having sent；
C), signal conversion unit changes the Bit circulation that transmission unit is sent into physical link corresponding signal, passes through transmission
Channel is sent to recipient, completes transmission process；
D), after receiving channel receives external input signal, first pass around signal conversion unit and (be equivalent to the inverse of transmission unit
Process), then the signal after conversion is sent into chip；
E), the signal for being sent into chip is sent simultaneously at most a data recovery unit, and sampling unit is based on respective reception
Clock carries out data recovery；
F), the beginning that data frame is indicated when sampling unit detects specific frame head, starts data buffer storage to the RAM that closes up
In；Verification unit verifies data after frame has received, and can be CRC, sum check etc., when verification passes through, indicates that this is logical
Road has correctly restored data, verification not by when abandon data；
G), since under same frequency clock, multiple recovery units necessarily have one or more sampling units that can fall into data
In effective figure of signal, so necessarily there is correct data output in data recovery unit, with asking or output unit will be correct
Data are transmitted in ram cell；
H), control unit is final complete according to the reading for receiving the ready signal-obtaining reception data that ram cell is sent
Recovery is sent and received at entire data.
Transmission method of the present invention can realize in the various programmables such as FPGA, CPLD, support single line LVDS, BLVDS,
A variety of physical transmission mediums such as optical fiber, transmission rate can reach 400M, can customize transport protocol, have very strong real-time
Property.
The transmission of high-speed data must be carried out between the system for possessing identical high-speed data Transmit-Receive Unit at two, connect
Relationship as shown in figure 3, the transmission interface of high-speed data Transmit-Receive Unit 1 to be connected to the receiving interface of high-speed data Transmit-Receive Unit 2,
The receiving interface of unit 1 is equally connected to the transmission interface of unit 2.
Data from the transmission interface of unit 1 sending after enter unit 2 receiving interface, then in turn through sampling unit,
Preamble detecting, dual port RAM, verification unit, finally by result that multiple units export by ask or after export correct result.
The above-described embodiments merely illustrate the principles and effects of the present invention, and the embodiment that part uses, for
For those skilled in the art, without departing from the concept of the premise of the invention, can also make it is several deformation and
It improves, these are all within the scope of protection of the present invention.
Claims (9)
1. a kind of high-speed data transmission apparatus based on asynchronous clock, it is characterised in that: including
One control unit, the transmitting-receiving for completing data controls and the assembling and parsing of data frame；
One transmission unit, for carrying out data output；
One transmission ram cell and a reception ram cell improve transceiver channel and control are single for buffering to data
The efficiency and reliability of member docking；
One signal conversion unit, the Signal Matching for physical layer；
One clock unit, for exporting the same frequency clock of multiple difference certain angles；
One is asked or output unit and multiple data recovery units and multiple communication channels, each data recovery unit are used respectively
Different clocks carries out data sampling and resumes work.
2. a kind of high-speed data transmission apparatus based on asynchronous clock according to claim 1, which is characterized in that the number
It is not less than four according to the number of recovery unit.
3. a kind of high-speed data transmission apparatus based on asynchronous clock according to claim 2, which is characterized in that described
Data recovery unit includes sampling unit, preamble detecting unit, dual port RAM and verification unit；The sampling unit is for adopting
Sample data, the dual port RAM support main control logic works under different frequencies from data acceptance logic to realize asynchronous work
Make, the preamble detecting unit verifies data buffer storage when detection passes through into dual port RAM, and to data, verifies
By then indicating to receive correct data and uploading data, data are otherwise abandoned.
4. a kind of high-speed data transmission apparatus based on asynchronous clock according to claim 1, which is characterized in that described
Communication channel uses LVDS, BLVDS or fiber-optic signal.
5. a kind of data transmission method of the high-speed data transmission apparatus based on asynchronous clock as described in claim 1, feature
It is, steps are as follows
A), data are filled into according to setting frame format and send in ram cell by control unit, and then starting sends instruction；
B), transmission unit sends data in the rising edge of tranmitting data register, until sending in ram cell after receiving transmission instruction
Data by until having sent；
C), signal conversion unit changes the Bit circulation that transmission unit is sent into physical link corresponding signal, passes through sendaisle
It is sent to recipient, completes transmission process；
D), after receiving channel receives external input signal, first pass around signal conversion unit, then by the signal after conversion send to
In chip；
E), the signal for being sent into chip is sent simultaneously at most a data recovery unit, and sampling unit is based on respective reception clock
Carry out data recovery.
6. data transmission method according to claim 5, which is characterized in that the data frame packet contains beginning flag, frame
Head, address field, variable length data section, check field.
7. data transmission method according to claim 5, which is characterized in that the table when sampling unit detects specific frame head
The beginning for showing data frame starts data buffer storage into closing in RAM；Verification unit verifies data after frame has received, can
Think CRC, sum check etc., when verification passes through, indicate that data have correctly been restored in this channel, verification not by when abandon number
According to.
8. data transmission method according to claim 5, which is characterized in that data recovery unit with ask or output unit will
Correct data are transmitted in ram cell.
9. data transmission method according to claim 5, which is characterized in that control unit is sent according to ram cell is received
The ready signal-obtaining come receives the reading of data, and be finally completed entire data sends and receives recovery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610765794.XA CN106411463B (en) | 2016-08-31 | 2016-08-31 | A kind of high-speed data transmission apparatus and method based on asynchronous clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610765794.XA CN106411463B (en) | 2016-08-31 | 2016-08-31 | A kind of high-speed data transmission apparatus and method based on asynchronous clock |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106411463A CN106411463A (en) | 2017-02-15 |
| CN106411463B true CN106411463B (en) | 2019-06-07 |
Family
ID=58002976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610765794.XA Active CN106411463B (en) | 2016-08-31 | 2016-08-31 | A kind of high-speed data transmission apparatus and method based on asynchronous clock |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106411463B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108182073B (en) * | 2017-12-29 | 2021-07-02 | 西安智多晶微电子有限公司 | Online downloading circuit based on FPGA |
| CN110034915B (en) * | 2019-04-19 | 2021-09-10 | 哈尔滨工业大学 | High-speed asynchronous serial data transmission method applied to array type ground penetrating radar |
| CN115277870B (en) * | 2021-04-14 | 2023-11-28 | 施耐德电气（中国）有限公司 | Communication data processing device, data communication device, corresponding method and communication system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1808925A (en) * | 2005-01-21 | 2006-07-26 | 华为技术有限公司 | Method and system of primary/standby selection and zero-loss switching for asynchronous signals |
| CN101931482A (en) * | 2010-09-08 | 2010-12-29 | 武汉虹信通信技术有限责任公司 | Clock synchronization method and system of convergent type video optical transmitter and receiver |
| CN102340316A (en) * | 2011-09-07 | 2012-02-01 | 上海大学 | FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer |
| CN103944583A (en) * | 2014-04-28 | 2014-07-23 | 中国人民解放军国防科学技术大学 | Processing method and device for parallelizing high-speed serial signals in SerDes |
-
2016
- 2016-08-31 CN CN201610765794.XA patent/CN106411463B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1808925A (en) * | 2005-01-21 | 2006-07-26 | 华为技术有限公司 | Method and system of primary/standby selection and zero-loss switching for asynchronous signals |
| CN101931482A (en) * | 2010-09-08 | 2010-12-29 | 武汉虹信通信技术有限责任公司 | Clock synchronization method and system of convergent type video optical transmitter and receiver |
| CN102340316A (en) * | 2011-09-07 | 2012-02-01 | 上海大学 | FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer |
| CN103944583A (en) * | 2014-04-28 | 2014-07-23 | 中国人民解放军国防科学技术大学 | Processing method and device for parallelizing high-speed serial signals in SerDes |
Non-Patent Citations (1)
| Title |
|---|
| A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization;Seungnam Choi等;《IEEE Transactions on Circuits and Systems I》;20160307;第276-287页 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106411463A (en) | 2017-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101950175B (en) | Implementation method of high-speed fieldbus based on industrial Ethernet | |
| CN103825696B (en) | A kind of device that high speed fibre real-time Communication for Power is realized based on FPGA | |
| CN106411740B (en) | Network port extended method based on ethernet controller | |
| CN101808027B (en) | Data receiving, storing and forwarding device suitable for various ports | |
| CN106411463B (en) | A kind of high-speed data transmission apparatus and method based on asynchronous clock | |
| CN102202058B (en) | Controller for protocol conversion between multipath UART bus and CAN bus | |
| JPH025665A (en) | Adaptor | |
| CN101951313A (en) | FPGA-based SFI4.1 device | |
| WO2002065686A1 (en) | Method and apparatus for deskewing multiple incoming signals | |
| CN104158822A (en) | Point-to-point transmission system of optical fiber links based on dual-channel binding and transmission method | |
| CN110471880A (en) | A kind of ARINC429 bus module and its data transmission method for supporting No. Label screening based on FPGA | |
| CN202190284U (en) | Protocol converter for CAN bus and SpaceWire bus | |
| CN101945031B (en) | Method for implementing mutual communication of slave stations of high-speed field bus | |
| CN112948295A (en) | FPGA and DDR high-speed data packet transmission system and method based on AXI4 bus | |
| CN101072064B (en) | Ethernet relay device and method | |
| CN205829667U (en) | A kind of communication gate of RTEX Yu DeviceNET | |
| CN102075397A (en) | Direct interfacing method for ARINC429 bus and high-speed intelligent unified bus | |
| CN108429707B (en) | Time trigger service repeater and method adapting to different transmission rates | |
| CN101374115A (en) | Rapid discriminating multiport control method based on PROFIBUS packet | |
| CN111130691B (en) | Satellite-borne asynchronous rate communication matching device | |
| CN103078667A (en) | Low voltage differential signaling (LVDS) high-speed data transmission method based on cat-5 | |
| WO2016000376A1 (en) | Signal processing method and signal processing apparatus based on pci-e interfaces | |
| US3943348A (en) | Apparatus for monitoring the operation of a data processing communication system | |
| CN101887635A (en) | High-resolution multi-channel seismic exploration data transmission system at shallow layer of deepwater | |
| CN108667706A (en) | The adjustable Ethernet serial server of serial ports quantity dynamic and its data transmission method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |