CN111261627B - 半导体结构 - Google Patents

半导体结构 Download PDF

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CN111261627B
CN111261627B CN201910106435.7A CN201910106435A CN111261627B CN 111261627 B CN111261627 B CN 111261627B CN 201910106435 A CN201910106435 A CN 201910106435A CN 111261627 B CN111261627 B CN 111261627B
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刘芳妏
吕增富
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Nanya Technology Corp
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Abstract

本发明公开了一种半导体结构，包含硅控整流器(silicon control rectifier,SCR)区域及NPN区域。硅控整流器区域包含第一p井区、第一n井区及第一p+区。第一n井区被第一p井区环绕。第一p+区配置于第一p井区中，并与第一n井区间隔开。NPN区域包含第二p井区、第一n+区、第二n+区及第二p+区。第一n+区与第二p井区及静电放电源耦合。第二n+区与第二p井区耦合，并与第一n+区间隔开。第二p+区配置于第二p井区中，并与第一p井区中的第一p+区等电位连接。本发明提供的半导体结构具有较低的开启电压(约5V至约15V)。因此，此半导体结构可以用于含有低电压元件的电路。

Description

半导体结构
技术领域
本发明是关于具有静电保护的半导体结构。
背景技术
集成电路已经发展到具有更小特征尺寸的先进技术。随着特征尺寸的缩小，静电放电(electrostatic discharge,ESD)造成损害的可能性随之增加。静电放电通常是瞬间高电压的放电。静电放电可能发生在电子电路中，例如集成电路。
近年来，硅控整流器(silicon control rectifier,SCR)广泛地被使用在静电放电保护电路中。然而，一般的硅控整流器的开启电压为约20V，此电压超过了低电压元件的崩溃电压。为了满足低电压元件的需求，需要降低硅控整流器的开启电压。
发明内容
本发明的目的在于提供一种具有较低开启电压的半导体结构。
根据本发明的一方面是提供一种半导体结构，包含硅控整流器(silicon controlrectifier,SCR)区域及NPN区域。硅控整流器区域形成于半导体基材中，包含第一p井区、第一n井区及第一p+区。第一n井区被第一p井区环绕。第一p+区配置于第一p井区中，并与第一n井区间隔开。NPN区域形成于半导体基材中，且邻近于硅控整流器区域。NPN区域包含第二p井区、第一n+区、第二n+区及第二p+区。第一n+区与第二p井区及静电放电源耦合。第二n+区与第二p井区耦合，并与第一n+区间隔开。第二p+区配置于第二p井区中，并与第一p井区中的第一p+区等电位连接。
根据本发明一个或多个实施方式，硅控整流器区域还包含第三p+区，配置于第一n井区中，并与静电放电源耦合。
根据本发明一个或多个实施方式，第三p+区与第一n+区等电位连接。
根据本发明一个或多个实施方式，NPN区域还包含第一环型布植区，直接耦合至第一n+区，其中第一环型布植区为p型掺杂。
根据本发明一个或多个实施方式，NPN区域还包含第二环型布植区，直接耦合至第二n+区，其中第二环型布植区为p型掺杂。
根据本发明一个或多个实施方式，半导体结构还包含第二n井区，配置于硅控整流器区域与NPN区域之间。
根据本发明一个或多个实施方式，半导体结构还包含金属线，等电位内连接第二p+区与第一p+区。
根据本发明一个或多个实施方式，硅控整流器区域还包含第三n+区，配置于第一p井区，且与接地节点耦合。
根据本发明一个或多个实施方式，硅控整流器区域及NPN区域配置成形成第一静电放电路径，第一静电放电路径自静电放电源经由NPN区域的第二p井区至第三n+区。
根据本发明一个或多个实施方式，硅控整流器区域及NPN区域配置成形成第二静电放电路径，第二静电放电路径自静电放电源经由硅控整流器区域的第一n井区至第三n+区。
本发明提供的半导体结构具有较低的开启电压(约5V至约15V)。因此，此半导体结构可以用于含有低电压元件的电路。
附图说明
为让本发明的上述和其他目的、特征、优点与实施方式能更明显易懂，结合附图详细说明如下：
图1绘示根据本发明的一实施例的半导体结构100的剖面图；
图2绘示对应图1的半导体结构100的等效电路图；
图3绘示根据本发明的一实施例的NPN区域320的剖面图；
图4绘示根据本发明的一实施例的NPN区域420的剖面图。
具体实施方式
现在将详细介绍本发明的实施例，其示例在附图中示出。在附图及说明书中，同样的标号用于指相同或相似的元件。
此外，“耦合至”或“与…耦合”或类似用词在本发明中无须进一步限定，其可以代表直接或间接电性连接。因此，当第一元件“耦合至”第二元件，其间的连接可以为直接的电性连接，且路径上仅有寄生元件，或是通过介于中间的元件间接电性连接，其中包含其他元件及连接。
根据本发明的多个实施例，半导体结构可以用于静电放电(electrostaticdischarge,ESD)的保护。与一般的硅控整流器(silicon control rectifier,SCR)元件相比，本发明提供的静电放电保护结构具有较低的开启电压。本发明的详细结构将在以下讨论。
图1绘示根据本发明的一实施例的半导体结构100的剖面图。半导体结构100包含硅控整流器区域110及NPN区域120。硅控整流器区域110及NPN区域120皆形成于半导体基材100a中。
硅控整流器区域110包含第一p井区111、第一n井区121及第一p+区131。第一p井区111环绕第一n井区121，而第一p+区131配置于第一p井区111中并与第一n井区121间隔开。此外，第一p+区131电性连接至第一p井区111。
在一些实施例中，硅控整流器区域110还包含第三p+区133，配置于第一n井区121中。第三p+区133电性耦合至静电放电源150。
在一些实施例中，硅控整流器区域110可以进一步包含第三n+区143，配置于第一p井区111中。第三n+区143耦合至接地节点170，其中接地节点170可以为导电结构，且可以认为是“零伏特”。
在一些实施例中，硅控整流器区域110还包含第四p+区134及第四n+区144，分别配置于第一p井区111及第一n井区121。第三n+区143、第四p+区134、第四n+区144及第三p+区133依序配置于硅控整流器区域110中。
NPN区域120形成于半导体基材100a中，且邻近于硅控整流器区域110。NPN区域120包含第二p井区112、第一n+区141、第二n+区142及第二p+区132。更进一步说明，第一n+区141、第二n+区142、第三n+区143及第四n+区144、第一p+区131、第二p+区132、第三p+区133及第四p+区134配置于半导体基材100a的上表面。
第一n+区141耦合至第二p井区112。在一些示例中，第一n+区141形成于第二p井区112中。此外，第一n+区141耦合至静电放电源150。举例来说，第一n+区141可以通过金属材料制成的导电迹线或导线连接至静电放电源150。在一些实施例中，第一n+区141可以实质上等电位连接至第三p+区133。举例来说，第一n+区141可以通过另一个金属材料制成的导电迹线或导线连接至第三p+区133。
第二n+区142与第一n+区141间隔开，并与第二p井区112耦合。详细而言，第二n+区142可以形成于第二p井区112中，并且靠近第一n+区141。在一些示例中，第二n+区142可以配置于第一p+区131与第一n+区141之间。
第二p+区132形成于第二p井区112中，并实质上等电位连接至形成于第一p井区111中的第一p+区131。在一些实施例中，半导体结构100可以还包含导电迹线160，导电迹线160等电位内连接第二p+区132与第一p+区131。导电迹线160可以形成于半导体基材100a之中或之上，且可以包含金属材料或由金属材料制成，例如铜、铝或其他合适的金属。导电迹线160可以自第二p+区132经过硅控整流器区域110及/或NPN区域120之外的合适区域而延伸至第一p+区131。因此，第二p+区132可以实质上等电位连接至第一p+区131。
在一些实施例中，半导体结构100还包含第二n井区180，配置于硅控整流器区域110与NPN区域120之间。第二n井区180将硅控整流器区域110的第一p井区111与NPN区域120的第二p井区112分隔开。值得注意的是，可以根据需求配置任意数量的n井区于硅控整流器区域110与NPN区域120之间。在一些实施例中，可以进一步形成第二n井区180于远离第一p井区111且邻近NPN区域120另一侧的区域。在一些实施例中，如图1所示，第二n井区180可以配置于NPN区域120的两侧。
在一些实施例中，半导体结构100可以包含深n井区(deep n-well region)181，深n井区181形成于第一p井区111之下。根据本发明的一些示例，第一p井区111与NPN区域120可以通过第二n井区180及深n井区181完全隔开。由于第一p井区111与NPN区域120隔开，硅控整流器区域110中任意区域的电位并不会受到NPN区域120的影响。
在某些实施例中，半导体结构100可以包含深n井区182，配置于第二p井区112之下。深n井区182及第二n井区180环绕NPN区域120，使得NPN区域120中任意区域的电位并不会受到硅控整流器区域110的影响。
图2绘示对应图1的半导体结构100的等效电路图。请参考图1及图2，绘示于图2的硅控整流器电路210及NPN晶体管220分别对应图1的硅控整流器区域110及NPN区域120。NPN晶体管220包含集电极221、发射极223及基极222。详细而言，图2中NPN晶体管220的集电极221、发射极223及基极222分别对应图1中第一n+区141、第二n+区142及第二p井区112。
图2的硅控整流器电路210可以包含或由NPN晶体管240及PNP晶体管250构成。硅控整流器电路210的NPN晶体管240包含集电极241、基极242及发射极243。硅控整流器电路210的PNP晶体管250包含集电极251、基极252及发射极253。集电极241、基极242及发射极243分别对应第一n井区121、第一p井区111及第三n+区143。另一方面，集电极251、基极252及发射极253分别对应第一p井区111、第一n井区121及第三p+区133。因此，NPN晶体管240的基极242耦合至PNP晶体管250的集电极251，而NPN晶体管240的集电极241耦合至PNP晶体管250的基极252。
此外，图2的节点215对应图1的第一p+区131。而且，图2的节点225对应图1的第二n+区132。图2的连接230对应图1的导电迹线160。节点215(例如第一p+区131)通过连接230(例如导电迹线160)实质上等电位连接至节点225(例如第二n+区132)。
请参考图1，当静电放电发生时，静电放电的电流/电压自静电放电源150传送至第一n+区141。第一n+区141因而吸引第二p井区112的电子，使得电子聚集于第一n+区141的附近。因此，与第二n+区142相比，第二p井区112产生较高的电位。
请参考图2，一旦基极222的电位VB高于发射极223的电位VE，可以驱动NPN晶体管220。在一些示例中，当电位VB高于电位VE约0.7V时，可以驱动NPN晶体管220。特别的是，当静电放电大于约5V，即可以驱动NPN晶体管220。
基极222通过节点225及节点215等电位耦合至基极242。基极222的电位与基极242实质上相同。换句话说，NPN晶体管220的基极222的较高的电位可以驱动硅控整流器电路210的NPN晶体管240。一旦NPN晶体管240被驱动，则PNP晶体管250亦随之驱动。因此，通过NPN区域的辅助，本发明的半导体结构整体的开启电压可以降低至约5V至约15V，例如8V至11V。
在一般没有NPN晶体管连接的硅控整流器元件中，硅控整流器元件的开启电压是由n井与p井之间的接面的突崩击穿电压(avalanche breakdown voltage)所决定。一般硅控整流器元件的开启电压通常大于约20V，而无法用于保护低电压元件避免静电放电的损害。与一般的硅控整流器元件相比，本发明的半导体结构具有相对较低的开启电压，因此可以用于保护低电压元件。
在一些实施例中，硅控整流器区域110及NPN区域120配置成形成第一静电放电路径(例如绘示于图2的路径261)，第一静电放电路径261自静电放电源150经NPN区域120的第二p井区112至第三n+区143。如图2所示，第一静电放电路径261经由NPN晶体管220至接地节点170。当静电放电发生时，NPN晶体管220会开启，并将电流接地排除。
在某些实施例中，硅控整流器区域110及NPN区域120配置成形成第二静电放电路径(例如绘示于图2的路径262)，第二静电放电路径262自静电放电源150经硅控整流器区域110的第一n井区121至第三n+区143。类似于第一静电放电路径261，第二静电放电路径262经由硅控整流器电路210至接地节点170。换句话说，本发明的半导体结构具有两条静电放电路径。因此，本发明的半导体结构将静电放电接地排除的效果更佳。
现在将讨论NPN区域的一些实施例的变形。在各种绘示的实施例中，相同的标号用于标记相同的元件。根据本发明的另一实施例，图3绘示的NPN区域320可以替换图1中的NPN区域120。与图1中的NPN区域120不同，NPN区域320还包含环型布植区(halo implantregion or pocket implant region)191，形成于靠近第二n+区142处。详细而言，环型布植区191与第二n+区142接触。环型布植区191的导电类型(conductivity type)与第二n+区142不同。举例来说，第二n+区142为N型掺杂，而环型布植区191为P型掺杂。由于导电类型不同，所以环型布植区191可以增加第二n+区142的电阻。第二n+区142的电阻增加使得NPN区域320的开启电压增加。因而使得半导体结构的整体开启电压亦增加。在环型布植区191形成于靠近第二n+区142的实施例中，半导体结构的整体开启电压可以增加至约10V至约15V，例如11V、12V、13V或14V。
图4绘示根据本发明又一实施例的半导体结构的NPN区域420。NPN区域420还包含环型布植区192，形成于靠近第一n+区141处，并且与第一n+区141接触。如上所述，环型布植区192可以增加第一n+区141的电阻。第一n+区141的电阻增加可以使NPN区域420开启电压降低，因而使半导体结构的整体开启电压降低。半导体结构的整体开启电压可以降低至约5V至约10V，例如6V、7V、8V或9V。
此外，由于环型布植区191及环型布植区192的掺杂浓度小于第二p井区112，因此环型布植区191及环型布植区192亦可以被称为“p-区”。
本发明提供的半导体结构具有较低的开启电压(约5V至约15V)。因此，此半导体结构可以用于含有低电压元件的电路。再者，本发明亦提供具有配置于NPN区中的环型布植区的半导体结构。通过此环型布植区，半导体结构的开启电压可以根据需求而微调。
虽然本发明已以实施方式详细公开如上，然其他实施方式亦是可行的。因此权利要求的精神及范围不应受到上述的实施方式所限制。
任何本领域的技术人员，在不脱离本发明的精神与范围内，当可作各种更动与润饰。鉴于前述内容，本发明包含落入本发明的权利要求内的修改和变化。

Claims (10)

1.一种半导体结构，其特征在于，包含：
硅控整流器区域，形成于半导体基材中，所述硅控整流器区域包含：
第一p井区；
第一n井区，被所述第一p井区环绕；及
第一p+区，配置于所述第一p井区中，并与所述第一n井区间隔开；以及
NPN区域，形成于所述半导体基材中，且邻近于所述硅控整流器区域，所述NPN区域包含：
第二p井区；
第一n+区，与所述第二p井区及静电放电源耦合；
第二n+区，与所述第二p井区耦合，并与所述第一n+区间隔开；及
第二p+区，配置于所述第二p井区中，并与所述第一p井区中的所述第一p+区等电位连接。
2.如权利要求1所述的半导体结构，其特征在于，所述硅控整流器区域还包含第三p+区，配置于所述第一n井区中，并与所述静电放电源耦合。
3.如权利要求2所述的半导体结构，其特征在于，所述第三p+区与所述第一n+区等电位连接。
4.如权利要求1所述的半导体结构，其特征在于，所述NPN区域还包含第一环型布植区，直接耦合至所述第一n+区，其中所述第一环型布植区为p型掺杂。
5.如权利要求1所述的半导体结构，其特征在于，所述NPN区域还包含第二环型布植区，直接耦合至所述第二n+区，其中所述第二环型布植区为p型掺杂。
6.如权利要求1所述的半导体结构，其特征在于，还包含第二n井区，配置于所述硅控整流器区域与所述NPN区域之间。
7.如权利要求1所述的半导体结构，其特征在于，还包含金属线，等电位内连接所述第二p+区与所述第一p+区。
8.如权利要求1所述的半导体结构，其特征在于，所述硅控整流器区域还包含第三n+区，配置于所述第一p井区，且与接地节点耦合。
9.如权利要求8所述的半导体结构，其特征在于，所述硅控整流器区域及所述NPN区域配置成形成第一静电放电路径，所述第一静电放电路径自所述静电放电源经由所述NPN区域的所述第二p井区至所述第三n+区。
10.如权利要求8所述的半导体结构，其特征在于，所述硅控整流器区域及所述NPN区域配置成形成第二静电放电路径，所述第二静电放电路径自所述静电放电源经由所述硅控整流器区域的所述第一n井区至所述第三n+区。
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