CN111243968B - Method for placing chips in groove - Google Patents
Method for placing chips in groove Download PDFInfo
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- CN111243968B CN111243968B CN202010129509.1A CN202010129509A CN111243968B CN 111243968 B CN111243968 B CN 111243968B CN 202010129509 A CN202010129509 A CN 202010129509A CN 111243968 B CN111243968 B CN 111243968B
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- 239000000084 colloidal system Substances 0.000 claims abstract description 83
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000000227 grinding Methods 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims abstract description 9
- 238000003825 pressing Methods 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 238000002360 preparation method Methods 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 30
- 235000012431 wafers Nutrition 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 239000003822 epoxy resin Substances 0.000 claims description 12
- 229920000647 polyepoxide Polymers 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 8
- 229910010272 inorganic material Inorganic materials 0.000 claims description 8
- 239000011147 inorganic material Substances 0.000 claims description 8
- 239000011368 organic material Substances 0.000 claims description 8
- 239000004814 polyurethane Substances 0.000 claims description 8
- 229920002635 polyurethane Polymers 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- 229910052809 inorganic oxide Inorganic materials 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 239000000843 powder Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229920001187 thermosetting polymer Polymers 0.000 claims description 4
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 239000000835 fiber Substances 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 claims 1
- 239000003292 glue Substances 0.000 description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 239000010453 quartz Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 238000011049 filling Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000003384 imaging method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/54—Providing fillings in containers, e.g. gas fillings
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Micromachines (AREA)
- Dicing (AREA)
Abstract
The invention discloses a method for placing a chip in a groove, which comprises the following steps: a, at fan-out embedding support plate surface preparation recess, fixed colloid is filled in the recess, specifically is: manufacturing a groove on the surface of the fan-out type embedded carrier plate by utilizing photoetching and etching processes, wherein the side length range of the groove is 1um to 10000um, and the depth is 10um to 1000 um; pouring the colloid into the groove through a dispensing or coating process; then removing the residual colloid on the surface of the groove by an etching or grinding process, and only leaving the colloid in the groove; b, embedding the cut chip into the groove of the carrier plate, and heating to soften the colloid; c, applying pressure on the surface of the chip by using another cover plate, manufacturing salient points on the surface of the cover plate, enabling the salient points to correspond to the position of the chip, and simultaneously curing the colloid; and D, taking down the cover plate after the colloid is solidified, and grinding the protruding colloid by a CMP process to obtain the final embedded structure.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a method for placing chips in a groove.
Background
The millimeter wave radio frequency technology is rapidly developed in the semiconductor industry, is widely applied to the fields of high-speed data communication, automobile radars, airborne missile tracking systems, space spectrum detection and imaging and the like, is expected to reach 11 billion dollars in market in 2018, and becomes a new industry. The new application puts new requirements on the electrical performance, compact structure and System reliability of the product, and for a wireless transmitting and receiving System, the wireless transmitting and receiving System cannot be integrated on the same Chip (SOC) at present, so that different chips including a radio frequency unit, a filter, a power amplifier and the like need to be integrated into an independent System to realize the functions of transmitting and receiving signals.
The most widely researched silicon cavity embedded fan-out structure can effectively solve the integration problem of a radio frequency micro-system module, but for a chip process embedded into a cavity, a colloid for pasting a chip is required to be placed in the cavity in advance, if the amount of the coated colloid in the cavity is less, the bottom of the chip cannot be completely covered by the colloid, and the height of the chip cannot be controlled; if the amount of glue applied in the cavity is large, the glue is extruded out to easily pollute the surface of the chip after the chip is pressed in.
Disclosure of Invention
The invention aims to provide a method for placing chips in a groove.
In order to solve the technical problems, the invention adopts the following technical scheme:
one aspect of the embodiments of the present invention provides a method for placing a chip in a groove, including the following steps:
a, at fan-out embedding support plate surface preparation recess, fixed colloid is filled in the recess, specifically is: manufacturing a groove on the surface of the fan-out type embedded carrier plate by utilizing photoetching and etching processes, wherein the side length range of the groove is 1um to 10000um, and the depth is 10um to 1000 um; pouring the colloid into the groove through a dispensing or coating process; then removing the residual colloid on the surface of the groove by an etching or grinding process, and only leaving the colloid in the groove;
b, embedding the cut chip into the groove of the carrier plate, and heating to soften the colloid;
c, applying pressure on the surface of the chip by using another cover plate, manufacturing salient points on the surface of the cover plate, enabling the salient points to correspond to the position of the chip, and simultaneously curing the colloid;
and D, taking down the cover plate after the colloid is solidified, and grinding the protruding colloid by a CMP process to obtain the final embedded structure.
Preferably, the step B specifically includes: and embedding the cut chip into the groove of the fan-out type embedding carrier plate through an FC (fiber channel) process, and heating the bottom of the fan-out type embedding carrier plate to soften the colloid.
Preferably, the step C specifically includes: and covering one side of the fan-out embedded carrier plate, which is exposed out of the chip, with another cover plate for lamination, wherein the other cover plate is a silicon wafer comprising 4, 6, 8 and 12 inch wafers or SOI (silicon on insulator) wafers, and the thickness range is 200um to 2000 um.
Preferably, the step C specifically includes: at the moment, the chip is fixed on the salient point of the cover plate in a sticking mode, and then the chip is embedded into the groove while the whole cover plate covers the base with the groove.
Another aspect of the embodiments of the present invention provides a method for placing a chip in a groove, including the following steps:
a, manufacturing a groove on the surface of a fan-out embedded carrier plate, and filling a fixing colloid in the groove;
b, embedding the cut chip into the groove of the carrier plate, and heating to soften the colloid;
c, applying pressure on the surface of the chip by using another cover plate, manufacturing salient points on the surface of the cover plate, enabling the salient points to correspond to the position of the chip, and simultaneously curing the colloid;
and D, taking down the cover plate after the colloid is solidified, leaving the convex points on the surface of the chip for protection, grinding the protruding colloid by a CMP process, and removing residual convex point materials to obtain the final embedded structure.
Preferably, the step a specifically includes:
manufacturing a groove on the surface of the fan-out type embedded carrier plate by utilizing photoetching and etching processes, wherein the side length range of the groove is 1um to 10000um, and the depth is 10um to 1000 um;
the fan-out embedded carrier plate comprises 4, 6, 8 and 12 inch wafers or SOI (silicon on insulator) sheets, and the thickness range is 200um to 2000 um;
pouring the colloid into the groove through a dispensing or coating process; the colloid can be made of photoresist, epoxy resin or thermosetting adhesive, or glass powder or inorganic material, and then the residual colloid on the surface of the groove is removed by etching or grinding process, and only the colloid in the groove is left.
Preferably, the step C specifically includes:
covering one surface of the carrier plate, which is exposed out of the chip, with another cover plate for lamination, wherein the cover plate is a silicon wafer comprising 4, 6, 8, 12 inch wafers or SOI (silicon on insulator) wafers, and the thickness range is 200um to 2000 um;
the cover plate is provided with salient points, firstly, a layer of material is manufactured on the surface of the cover plate through a deposition process, and the material is an inorganic oxide containing silicon oxide or silicon nitride or an organic material containing epoxy resin and polyurethane;
then, carrying out graphical processing on the surface facing the deposition material through photoetching and etching processes, so that the position contacting the chip is covered by the layer of material; the thickness of the layer material ranges from 100nm to 100 um;
the salient points protect the surface of the chip, the colloid overflowing when the chip is pressed down cannot pollute the surface of the chip, meanwhile, the area in the middle of the salient points can contain the overflowing colloid, and then the colloid is waited for solidification.
The invention has the following beneficial effects: through designing a kind of apron, set up the arch of take the altitude on the apron, place excessive glue in the cavity like this, press the chip to get into the cavity through the arch, the colloid in the cavity is extruded the protruding outside region of apron, has both guaranteed that the chip bottom has the glue of same thickness, has avoided the chip surface to be polluted by the colloid again.
Drawings
FIG. 1 is a first schematic structural diagram illustrating a chip-in-recess placement method according to an embodiment of the present invention;
FIG. 2 is a second schematic structural diagram illustrating a chip-in-recess placement method according to an embodiment of the present invention;
FIG. 3 is a third schematic structural view illustrating a chip-in-recess placement method according to an embodiment of the present invention;
FIG. 4 is a schematic structural view of the cover plate of embodiment 1 of the present invention taken out;
fig. 5 is a schematic diagram of a final embedded structure obtained in embodiment 1 of the present invention;
fig. 6 is a schematic structural view of embodiment 2 of the present invention with the cover plate removed;
fig. 7 is a schematic diagram of a final embedded structure obtained in embodiment 2 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Detailed description of the preferred embodiment 1
The method for placing the chip in the groove provided by the embodiment of the invention comprises the following steps:
a, manufacturing a groove on the surface of a fan-out embedded carrier plate, and filling a fixing colloid in the groove;
as shown in fig. 1, a groove is formed on the surface of the fan-out embedded carrier 102 by photolithography and etching processes, wherein the side length of the groove ranges from 1um to 10000um, the depth ranges from 10um to 1000um,
the fan-out embedded carrier 102 may be a Silicon wafer, including a 4, 6, 8, 12 inch wafer or an SOI (Silicon-On-Insulator) wafer, with a thickness ranging from 200um to 2000 um. The material can also be other materials, including inorganic materials such as glass, quartz, silicon carbide, alumina and the like, and can also be organic materials such as epoxy resin, polyurethane and the like, and the main function of the material is to provide a supporting function.
Pouring the colloid 104 into the groove through a dispensing or coating process; the colloid can be made of photoresist, epoxy resin, thermosetting adhesive, glass powder, inorganic material and the like, and then the residual colloid on the surface of the groove is removed through an etching or grinding process, and only the colloid in the groove is left;
b, embedding the cut chip 105 into the groove of the carrier plate, and heating to soften the colloid;
as shown in fig. 2, the cut chips 105 are embedded into the grooves of the fan-out embedded carrier 102 by FC process, and the glue is softened by heating at the bottom of the fan-out embedded carrier 102;
c, applying pressure on the surface of the chip by using another cover plate 101, manufacturing a salient point 103 on the surface of the cover plate, and curing the colloid at the same time when the salient point 103 corresponds to the position of the chip 105;
as shown in fig. 1, another cover plate 101 covers one side of the fan-out embedded carrier plate 102 exposed from the chip for lamination, where the other cover plate 101 may be a silicon wafer including a 4, 6, 8, 12 inch wafer or an SOI wafer with a thickness ranging from 200um to 2000um, or other materials including inorganic materials such as glass, quartz, silicon carbide, alumina, etc., or organic materials such as epoxy resin, polyurethane, etc., and its main function is to provide a whole-surface lamination effect.
Here, the cover plate 101 has the bumps 103, and a layer of material is first manufactured on the surface of the cover plate through a deposition process, wherein the material can be inorganic oxide such as silicon oxide or silicon nitride, and can also be organic material such as epoxy resin and polyurethane;
then, carrying out graphical processing on the surface facing the deposition material through photoetching and etching processes, so that the position contacting the chip is covered by the layer of material;
the thickness of the layer material ranges from 100nm to 100 um;
the salient points protect the surface of the chip, the surface of the chip cannot be polluted by overflowing colloid when the chip is pressed down, meanwhile, the middle areas of the salient points can contain the overflowing colloid, and then the colloid is waited to be solidified;
alternatively, as shown in fig. 2, the chip 105 is not first embedded into the chip, but is first fixed on the bumps 103 of the cover plate 101 by means of adhesion, and then the entire cover plate 101 covers the base with the groove, and the chip 105 is embedded into the groove, and the resulting structure is shown in fig. 3.
D, taking down the cover plate after the colloid is solidified, and grinding the protruding colloid by a CMP process to obtain a final embedded structure;
as shown in fig. 4, the cover plate is removed after the glue is cured, and the wafer is cleaned;
as shown in fig. 5, the protruding colloids are planarized by a CMP process to obtain the final embedded structure.
Detailed description of the preferred embodiment 2
Another embodiment of the present invention provides a method for placing a chip in a groove, including:
a, manufacturing a groove on the surface of a fan-out embedded carrier plate, and filling a fixing colloid in the groove;
referring to fig. 1, a groove is manufactured on the surface of the fan-out embedded carrier plate 102 by using photolithography and etching processes, wherein the side length of the groove ranges from 1um to 10000um, and the depth ranges from 10um to 1000 um;
the silicon wafer in the step comprises a 4, 6, 8 and 12-inch wafer or an SOI wafer, the thickness range is 200um to 2000um, other materials can be used, including inorganic materials such as glass, quartz, silicon carbide and alumina, organic materials such as epoxy resin and polyurethane can be used, and the main function of the silicon wafer is to provide a supporting function.
Pouring the colloid into the groove through a dispensing or coating process; the colloid can be made of photoresist, epoxy resin, thermosetting adhesive, glass powder, inorganic material and the like, and then residual colloid on the surface of the groove is removed through an etching or grinding process, and only the colloid in the groove is left;
b, embedding the cut chip into the groove of the carrier plate, and heating to soften the colloid;
referring to fig. 1, the cut chip is embedded into the groove of the carrier by FC process, and the bottom of the carrier is heated to soften the colloid;
c, applying pressure on the surface of the chip by using another cover plate, manufacturing salient points on the surface of the cover plate, enabling the salient points to correspond to the position of the chip, and simultaneously curing the colloid;
referring to fig. 1, another cover plate 101 covers the carrier plate 102 to perform a pressing process on the side where the chip 105 is exposed, where the cover plate 101 may be a silicon wafer or an SOI wafer with a thickness ranging from 200um to 2000um, or other materials, including inorganic materials such as glass, quartz, silicon carbide, and alumina, or organic materials such as epoxy resin and polyurethane, and its main function is to provide a whole-surface pressing effect.
The cover plate is provided with the salient points 103, firstly, a layer of material is manufactured on the surface of the cover plate through a deposition process, and the material can be inorganic oxides such as silicon oxide or silicon nitride and the like, and also can be organic materials such as epoxy resin, polyurethane and the like; then, carrying out graphical processing on the surface facing the deposition material through photoetching and etching processes, so that the position contacting the chip is covered by the layer of material; the thickness of the layer material ranges from 100nm to 100 um;
the salient points 103 protect the surface of the chip, the surface of the chip cannot be polluted by overflowing colloid when the chip is pressed down, meanwhile, the middle areas of the salient points can contain the overflowing colloid, and then the colloid is waited to be solidified;
d, taking down the cover plate after the colloid is solidified, leaving the convex points on the surface of the chip for protection, grinding the protruding colloid through a CMP process, and removing residual convex point materials to obtain a final embedded structure;
as shown in fig. 6, the cover plate is taken down after the colloid is solidified, and the convex points on the cover plate are left on the surface of the chip for protection;
as shown in fig. 7, the protruding colloid is polished by a CMP process, and then the bump material is removed by dry etching or wet cleaning, so as to obtain the final embedded structure.
According to the method for placing the chip in the groove, the cover plate is designed, the protrusion with a certain height is arranged on the cover plate, excessive glue is placed in the cavity, the chip is pressed into the cavity through the protrusion, glue in the cavity is extruded to the area outside the protrusion of the cover plate, the glue with the same thickness at the bottom of the chip is guaranteed, and the surface of the chip is prevented from being polluted by the glue.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (3)
1. A method for placing an in-groove chip is characterized by comprising the following steps:
a, at fan-out embedding support plate surface preparation recess, fixed colloid is filled in the recess, specifically is: manufacturing a groove on the surface of the fan-out type embedded carrier plate by utilizing photoetching and etching processes, wherein the side length range of the groove is 1um to 10000um, and the depth is 10um to 1000 um; pouring the colloid into the groove through a dispensing or coating process; then removing the residual colloid on the surface of the groove by an etching or grinding process, and only leaving the colloid in the groove;
b, the chip that the cutting is good is embedded into the support plate recess, and the heating makes the colloid soften, specifically includes: embedding the cut chip into a groove of the fan-out type embedded carrier plate through an FC (fiber channel) process, and heating the bottom of the fan-out type embedded carrier plate to soften the colloid;
c, exert pressure on the chip surface with another apron, apron surface preparation bump, the bump corresponds the chip position, is the colloid solidification simultaneously, specifically includes: covering one side of the fan-out embedded carrier plate exposed out of the chip with another cover plate for pressing, wherein the other cover plate is a silicon wafer comprising 4, 6, 8, 12 inch wafers or SOI (silicon on insulator) wafers, and the thickness range is 200um to 2000 um;
and D, taking down the cover plate after the colloid is solidified, and grinding the protruding colloid by a CMP process to obtain the final embedded structure.
2. The method for placing a chip in a groove according to claim 1, wherein the step C specifically comprises: at the moment, the chip is fixed on the salient point of the cover plate in a sticking mode, and then the chip is embedded into the groove while the whole cover plate covers the base with the groove.
3. A method for placing an in-groove chip is characterized by comprising the following steps:
a, at fan-out embedding support plate surface preparation recess, fixed colloid is filled in the recess, specifically includes:
manufacturing a groove on the surface of the fan-out type embedded carrier plate by utilizing photoetching and etching processes, wherein the side length range of the groove is 1um to 10000um, and the depth is 10um to 1000 um;
the fan-out embedded carrier plate comprises 4, 6, 8 and 12 inch wafers or SOI (silicon on insulator) sheets, and the thickness range is 200um to 2000 um;
pouring the colloid into the groove through a dispensing or coating process; the colloid is made of photoresist, epoxy resin or thermosetting adhesive or glass powder or inorganic material, and then residual colloid on the surface of the groove is removed through an etching or grinding process, and only the colloid in the groove is left;
b, embedding the cut chip into the groove of the carrier plate, and heating to soften the colloid;
c, exert pressure on the chip surface with another apron, apron surface preparation bump, the bump corresponds the chip position, is the colloid solidification simultaneously, specifically includes:
covering one surface of the carrier plate, which is exposed out of the chip, with another cover plate for pressing, wherein the cover plate is a silicon wafer comprising 4, 6, 8, 12 inch wafers or SOI (silicon on insulator) wafers, and the thickness range is 200um to 2000 um;
the cover plate is provided with salient points, firstly, a layer of material is manufactured on the surface of the cover plate through a deposition process, and the material is an inorganic oxide containing silicon oxide or silicon nitride or an organic material containing epoxy resin and polyurethane;
then, carrying out graphical processing on the surface facing the deposition material through photoetching and etching processes, so that the position contacting the chip is covered by the layer of material; the thickness of the layer material ranges from 100nm to 100 um;
the salient points protect the surface of the chip, the surface of the chip cannot be polluted by overflowing colloid when the chip is pressed down, meanwhile, the middle areas of the salient points can contain the overflowing colloid, and then the colloid is waited to be solidified;
and D, taking down the cover plate after the colloid is solidified, leaving the convex points on the surface of the chip for protection, grinding the protruding colloid by a CMP process, and removing residual convex point materials to obtain the final embedded structure.
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| CN202010129509.1A CN111243968B (en) | 2020-02-28 | 2020-02-28 | Method for placing chips in groove |
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| CN202010129509.1A CN111243968B (en) | 2020-02-28 | 2020-02-28 | Method for placing chips in groove |
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| CN104576424A (en) * | 2014-12-10 | 2015-04-29 | 华进半导体封装先导技术研发中心有限公司 | Method for realizing fan-out wafer encapsulation by preparing bumps on chip in advance |
| CN107275302B (en) * | 2017-07-21 | 2019-08-30 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package structure and its manufacturing method |
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| CN1466777A (en) * | 2000-09-25 | 2004-01-07 | Ҿ쳵���ʽ���� | Semiconductor element and method of manufacturing and multi-layer printed circuit board and mfg. method |
| CN1829416A (en) * | 2005-02-28 | 2006-09-06 | 三星电机株式会社 | Embedded chip printed circuit board and method of manufacturing the same |
| CN106180954A (en) * | 2016-08-08 | 2016-12-07 | 华东光电集成器件研究所 | A kind of multi-chip eutectic weldering device for exerting |
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