CN110021547A - A kind of big interim bonding method of salient point wafer in surface - Google Patents
A kind of big interim bonding method of salient point wafer in surface Download PDFInfo
- Publication number
- CN110021547A CN110021547A CN201811593467.6A CN201811593467A CN110021547A CN 110021547 A CN110021547 A CN 110021547A CN 201811593467 A CN201811593467 A CN 201811593467A CN 110021547 A CN110021547 A CN 110021547A
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- Prior art keywords
- support plate
- groove
- salient point
- bonding method
- interim bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68313—Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Micromachines (AREA)
Abstract
The invention discloses a kind of big interim bonding method of salient point wafer in surface, specific processing includes 101) making recessing step and 102) bonding steps；The present invention provides a kind of big interim bonding method of salient point wafer in surface for the applicability that can greatly increase interim bonding technology.
Description
Technical field
The present invention relates to technical field of semiconductors, are temporarily bonded more specifically, it is related to a kind of big salient point wafer in surface
Method.
Background technique
Under the historical background of rear Moore's Law, integrated level change is improved by way of traditional diminution transistor size
It obtains more difficult.Present electronic system just develops towards miniaturization, diversification, intelligentized direction, and ultimately forms and have
The multi-functional high integration low cost Integrated Electronic System in one of the fusions such as perception, communication, processing, transmission.Multifunctional comprehensive
The core technology of electronic system be it is integrated, from Planar integration to it is three-dimensionally integrated, from chip-scale to integrated level and complexity more
High system-level integrated development.Three-dimensionally integrated system in package, which is able to solve in same area, integrates asking for more transistors
Topic is following developing direction.
Do support plate or cover board by pinboard do the structure of system in package can be architecturally by chip by plane
Layout is changed to stacked layout, and the energy systems such as integrated passive devices or discrete component building, so that precision, density increase, property
It can greatly improve, represent the development trend of future radio frequency integrated circuit technique, there are great advantages characteristics in various aspects:
A) three-dimensional Manufacturing resource system in package completes whole interconnection an of system using a chip housing, makes total weldering
Point is greatly reduced, and the line distance of element is also shortened, so that electrical property be made to be improved.
B) three-dimensional Manufacturing resource system in package is superimposed two or more chips in same switching board chip, the side Z
To space also use, and packaging pin need not be increased, two chip stackings are all larger than in same shell with chip area ratio
100%, three chip stackings can increase to 250%.
But the production of pinboard generally requires interim bonding technology, that is, need with the technique that is temporarily bonded first one just
The support plate of Chang Houdu is combined with pinboard, is then supported with support plate and is carried out thinned and the back side RDL and bump to pinboard
Technique finally removes support plate the production for completing pinboard, and this method is for 300 microns to the switching between 50 micron thickness
It is very important for plate.
But interim bonding is that the combination of support plate and pinboard is realized by the effect of bonding glue, is bonded the thickness of glue
Often below 100 microns, in this way if switching plate surface has biggish protrusion or mounted ultra-thin chip with FC technique
If, it cannot be directly bonded with support plate, and some protrusions or surface mount chip cannot be touched with being glued.
Summary of the invention
The present invention overcomes the deficiencies in the prior art, a kind of table for the applicability that can greatly increase interim bonding technology is provided
The big interim bonding method of salient point wafer in face.
Technical scheme is as follows:
A kind of big interim bonding method of salient point wafer in surface, specific processing include the following steps:
101) it makes recessing step: groove being made by photoetching, etching technics in support plate upper surface, passes through rotation in slide glass upper surface
It applies, glue spraying or electroplating technique add one layer of bonding glue；
102) bonding steps: step 101) treated support plate, it is done with pinboard by way of heating and pressing and is faced
Shi Jianhe, heating temperature range is between 20 degree to 200 degree；Pinboard surface bulge or pasting chip are enclosed in the recessed of support plate
Inside slot.
Further, support plate size uses one of 4,6,8,12 cun, and support plate thickness range is 200um to 2000um,
Carrier plate material uses one of silicon wafer, glass, quartz, silicon carbide, aluminium oxide, epoxy resin, polyurethane.
Further, groove structure depth is in 10um to 1000um, and between 1um to 10cm, groove is cut the width of groove
Face figure is rectangular, round, oval or triangle.
Further, the thickness range of glue is bonded between 1um to 300um, enters bonding glue in groove by baking.
Advantage is the present invention compared with prior art: the present invention is the convex of pinboard by making groove on support plate surface
It rises or surface mount chip provides the region being received, the applicability of interim bonding technology can be greatly increased；For cannot be straight
The protrusion or pasting chip with being glued touching are connect, can be directly embedded in groove, groove provides guard space for these devices.
Detailed description of the invention
Fig. 1 is that the first of the invention forms the sectional view of groove；
Fig. 2 is the sectional view that bonding glue is generated in Fig. 1 of the invention；
Fig. 3 is the first overall structure sectional view of the invention；
Fig. 4 is the sectional view of second of formation groove and bonding dry film of the invention；
Fig. 5 is the sectional view in Fig. 4 of the invention after processing bonding dry film；
Fig. 6 is second of overall structure sectional view of the invention；
Fig. 7 is the third overall structure sectional view of the invention；
Fig. 8 is the 4th kind of overall structure sectional view of the invention.
It is identified in figure: support plate 101, pinboard 102, chip 103, groove 104, bonding glue 105, bonding dry film 106.
Specific embodiment
Embodiments of the present invention are described below in detail, in which the same or similar labels are throughly indicated identical or classes
As element or the element of similar functions.It is exemplary below with reference to the embodiment of attached drawing description, is only used for explaining
The present invention and cannot function as limitation of the present invention.
Those skilled in the art can understand that unless otherwise defined, all terms used herein (including skill
Art term and scientific and technical terminology) there is meaning identical with the general understanding of those of ordinary skill in fields of the present invention.Also
It should be understood that those terms such as defined in the general dictionary should be understood that have in the context of the prior art
The consistent meaning of meaning, and unless definition as here, will not be explained in an idealized or overly formal meaning.
The label about step mentioned in each embodiment, it is only for the convenience of description, without substantial
The connection of sequencing.Different step in each specific embodiment can carry out the combination of different sequencings, realize this hair
Bright goal of the invention.
The present invention is further described with reference to the accompanying drawings and detailed description.
Embodiment one:
As shown in Figure 1 to Figure 3, the big interim bonding method of salient point wafer in a kind of surface, specific processing include the following steps:
101) it makes 104 step of groove: groove 104,104 knot of groove being made by photoetching, etching technics in 101 upper surface of support plate
Structure depth in 10um to 1000um, the width of groove 104 between 1um to 10cm, 104 sectional view of groove be it is rectangular, round,
Ellipse or triangle.One layer of bonding glue 105 is added by spin coating, glue spraying or electroplating technique in slide glass upper surface, is bonded glue
105 thickness range enters bonding glue 105 in groove 104 between 1um to 300um, through baking, and with 101 knot of support plate
It closes closer.
101 size of support plate uses one of 4,6,8,12 cun, and 101 thickness range of support plate is 200um to 2000um, support plate
101 materials are also possible to other materials, including glass using silicon wafer is generally used, quartz, silicon carbide, the inorganic material such as aluminium oxide
Material, is also possible to epoxy resin, the organic materials such as polyurethane, major function is to provide supporting role.
102) bonding steps: step 101) treated support plate 101, make it with switching by way of heating and pressing
Plate 102 does interim bonding, and heating temperature range is between 20 degree to 200 degree；102 surface bulge of pinboard or pasting chip
103 are enclosed in inside the groove 104 of support plate 101.
Embodiment two:
As shown in Figures 4 to 6, it is basically the same as the first embodiment, difference is, on the groove 104 of 101 upper surface of support plate
Technique by pasting dry film adds one layer of interim bonding dry film 106, is bonded the thickness range of dry film 106 between 1um to 300um,
The bonding dry film 106 of 104 opening range of groove is removed by photoetching.
Embodiment three:
It as shown in Fig. 7 to Fig. 8, is basically the same as the first embodiment, difference is that the groove 104 in 101 upper surface of support plate is cut
Face uses triangle or ellipse, and bonding glue 105 patch and 101 upper surface of support plate, thickness completely is throughout all essentially the same.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, without departing from the inventive concept of the premise, can also make several improvements and modifications, these improvements and modifications also should be regarded as
In the scope of the present invention.
Claims (4)
1. a kind of big interim bonding method of salient point wafer in surface, which is characterized in that specific processing includes the following steps:
101) it makes recessing step: groove being made by photoetching, etching technics in support plate upper surface, passes through rotation in slide glass upper surface
It applies, glue spraying or electroplating technique add one layer of bonding glue；
102) bonding steps: step 101) treated support plate, it is done with pinboard by way of heating and pressing and is faced
Shi Jianhe, heating temperature range is between 20 degree to 200 degree；Pinboard surface bulge or pasting chip are enclosed in the recessed of support plate
Inside slot.
2. the big interim bonding method of salient point wafer in a kind of surface according to claim 1, it is characterised in that: support plate size is adopted
With one of 4,6,8,12 cun, support plate thickness range is 200um to 2000um, carrier plate material use silicon wafer, glass, quartz,
One of silicon carbide, aluminium oxide, epoxy resin, polyurethane.
3. the big interim bonding method of salient point wafer in a kind of surface according to claim 1, it is characterised in that: groove structure is deep
Degree is in 10um to 1000um, and for the width of groove between 1um to 10cm, groove section figure is rectangular, round, oval or three
It is angular.
4. the big interim bonding method of salient point wafer in a kind of surface according to claim 1, it is characterised in that: be bonded the thickness of glue
Range is spent between 1um to 300um, enters bonding glue in groove by baking.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811593467.6A CN110021547A (en) | 2018-12-25 | 2018-12-25 | A kind of big interim bonding method of salient point wafer in surface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811593467.6A CN110021547A (en) | 2018-12-25 | 2018-12-25 | A kind of big interim bonding method of salient point wafer in surface |
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| Publication Number | Publication Date |
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| CN110021547A true CN110021547A (en) | 2019-07-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811593467.6A Pending CN110021547A (en) | 2018-12-25 | 2018-12-25 | A kind of big interim bonding method of salient point wafer in surface |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111640677A (en) * | 2020-03-02 | 2020-09-08 | 浙江集迈科微电子有限公司 | Method for placing chips in groove |
| CN112509928A (en) * | 2020-11-30 | 2021-03-16 | 复旦大学 | Temporary bonding method |
| CN114121767A (en) * | 2021-11-19 | 2022-03-01 | 武汉新芯集成电路制造有限公司 | Wafer bonding structure and wafer bonding method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050221598A1 (en) * | 2004-03-31 | 2005-10-06 | Daoqiang Lu | Wafer support and release in wafer processing |
| CN103187350A (en) * | 2011-12-31 | 2013-07-03 | 刘胜 | Silicon wafer thinning fixture with through-hole electroplating copper salient points and thinning technique |
| CN105244308A (en) * | 2015-11-16 | 2016-01-13 | 华天科技（昆山）电子有限公司 | Method for holding thin wafer through temporary bonding of porous slide glass |
-
2018
- 2018-12-25 CN CN201811593467.6A patent/CN110021547A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050221598A1 (en) * | 2004-03-31 | 2005-10-06 | Daoqiang Lu | Wafer support and release in wafer processing |
| CN103187350A (en) * | 2011-12-31 | 2013-07-03 | 刘胜 | Silicon wafer thinning fixture with through-hole electroplating copper salient points and thinning technique |
| CN105244308A (en) * | 2015-11-16 | 2016-01-13 | 华天科技（昆山）电子有限公司 | Method for holding thin wafer through temporary bonding of porous slide glass |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111640677A (en) * | 2020-03-02 | 2020-09-08 | 浙江集迈科微电子有限公司 | Method for placing chips in groove |
| CN111640677B (en) * | 2020-03-02 | 2022-04-26 | 浙江集迈科微电子有限公司 | Method for placing chips in groove |
| CN112509928A (en) * | 2020-11-30 | 2021-03-16 | 复旦大学 | Temporary bonding method |
| CN114121767A (en) * | 2021-11-19 | 2022-03-01 | 武汉新芯集成电路制造有限公司 | Wafer bonding structure and wafer bonding method |
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Application publication date: 20190716 |