CN111226306A - 具有带抬升区的栅极的晶体管 - Google Patents

具有带抬升区的栅极的晶体管 Download PDF

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CN111226306A
CN111226306A CN201880068026.6A CN201880068026A CN111226306A CN 111226306 A CN111226306 A CN 111226306A CN 201880068026 A CN201880068026 A CN 201880068026A CN 111226306 A CN111226306 A CN 111226306A
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蔡军
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

在至少一个示例中，晶体管(100)包含半导体(102)、第一漂移层(112)、漏极区(116)、体区(128)、源极区(134)、浅沟槽隔离区(114)、电介质(119)及栅极(120)。所述第一漂移层(112)在所述半导体(102)中形成并且具有第一类型的多数载流子。所述漏极区(116)在所述第一漂移层(112)中形成并且具有所述第一类型的多数载流子。所述体区(128)在所述半导体(102)中形成并且具有第二类型的多数载流子。所述源极区(134)在所述体区(128)中形成并且具有所述第一类型的多数载流子。所述浅沟槽隔离区(114)在所述第一漂移层(112)中形成并且被设置在所述漏极区(116)与所述体区(128)之间。所述电介质(119)在所述半导体(102)上形成，并且所述栅极(120)在所述电介质(119)上方形成且具有抬升区(122)。

Description

具有带抬升区的栅极的晶体管
背景技术
横向扩散MOSFET(LDMOS)是在许多高电应用中(诸如在开关DC到DC转换器中)有用的晶体管。为降低在一些DC到DC转换器中电感器的大小，LDMOS以相对高的频率被接通和关断。
发明内容
在至少一个实施例中，晶体管包括半导体、第一漂移层、漏极区、体区、源极区、浅沟槽隔离区、电介质和栅极。第一漂移层在半导体中形成并且具有第一类型的多数载流子。漏极区在第一漂移层中形成并且具有第一类型的多数载流子。体区在半导体中形成并且具有第二类型的多数载流子。源极区在体区中形成并且具有第一类型的多数载流子。浅沟槽隔离区在第一漂移层中形成并且被设置在漏极区与体区之间。电介质在半导体上形成，以及栅极在电介质上方形成并且具有抬升区。
在至少一个实施例中，晶体管进一步包括在第一漂移层中形成的掺杂区，其中掺杂区具有第一类型的多数载流子。
在至少一个实施例中，电介质具有在栅极的抬升区下的抬升区。
在至少一个实施例中，掺杂区与浅沟槽隔离区共享圆形界面。
在至少一个实施例中，圆形界面降低在晶体管的操作期间的局部电场。
在至少一个实施例中，晶体管进一步包括在半导体中形成的第二漂移层，其中第二漂移层具有第一类型的多数载流子。
在至少一个实施例中，一种方法包括：在半导体中形成具有第一类型的多数载流子的第一漂移层；在第一漂移层中形成浅沟槽隔离区；在半导体上方生长衬垫氧化物层；在衬垫氧化物层上方沉积氮化物层；在氮化物层上方沉积光致抗蚀剂层；在光致抗蚀剂层中暴露开口图案；基于开口图案在光致抗蚀剂层中蚀刻开口以暴露到氮化物层的开口；蚀刻到氮化物层的开口以暴露到衬垫氧化物层的开口；去除光致抗蚀剂层；在到衬垫氧化物层的开口上生长氧化物；去除氮化物层；去除衬垫氧化物层，并且留下在衬垫氧化物层上生长的氧化物的至少一部分；生长栅极氧化物层；在栅极氧化物层上方形成栅极；在第一漂移层中形成具有第一类型的多数载流子的漏极区；在半导体中形成具有第二类型的多数载流子的体区；以及在体区中形成具有第一类型的多数载流子的源极区。
在至少一个实施例中，其中在到垫氧化物层的开口上生长氧化物时，氧化物被生长到至少200埃的厚度。
在至少一个实施例中，该方法进一步包括通过开口将掺杂剂注入到衬垫氧化物层以提供第一类型的多数载流子。
在至少一个实施例中，对于该方法，第一类型的多数载流子是电子，并且第二类型的多数载流子是空穴，其中通过开口将掺杂剂注入到衬垫氧化物层包含以从0°到9°的注入角度，采用25KeV到250KeV的范围中的能量注入剂量为6·1011cm-2到9·1012cm-2的磷或砷。
在至少一个实施例中，对于该方法，半导体包括硅。氧化物、衬垫氧化物层和栅极氧化物层各自包括二氧化硅。此外，在到氧化物衬垫层的开口上生长氧化物包含使半导体氧化。
在至少一个实施例中，该方法进一步包括在半导体中形成具有第一类型的多数载流子的第二漂移层。
在至少一个实施例中，在半导体中形成第一漂移层包括以从0°到9°的注入角度，采用25KeV到400KeV的能量在半导体中注入剂量为8·1011cm-2到2·1013cm-2的砷。此外，在半导体中形成第二漂移层包括以从0°到9°的注入角度，采用160KeV到1MeV的能量在半导体中注入剂量为1·1012cm-2到2·1013cm-2的磷。
在至少一个实施例中，在半导体中形成第一掩埋层包括以从0°到9°的注入角度，采用800KeV到2MeV的能量将剂量为1·1012cm-2到2·1013cm-2的硼注入到半导体中。
在至少一个实施例中，该方法进一步包括在半导体中形成具有第二类型的多数载流子的第二掩埋层。
在至少一个实施例中，第二晶体管包括半导体、第一漂移层、漏极区、体区、源极区、浅沟槽隔离区、电介质和掺杂区。第一漂移层在半导体中形成且具有第一类型的多数载流子。漏极区在第一漂移层中形成并且具有第一类型的多数载流子。体区在半导体中形成并且具有第二类型的多数载流子。源极区在体区中形成并且具有第一类型的多数载流子。浅沟槽隔离区在第一漂移层中形成并且被设置在漏极区与体区之间。电介质在半导体上形成，以及掺杂区在第一漂移层中形成并且具有第一类型的多数载流子。
在至少一个实施例中，对于上述第二晶体管，掺杂区与浅沟槽隔离区共享圆形界面。
在至少一个实施例中，对于上述第二晶体管，圆形界面降低了晶体管的操作期间的局部电场。
附图说明
图1示出了各种实例中的说明性LDMOS。
图2示出了各种示例中的说明性LDMOS的制造。
图3示出了各种示例中的说明性LDMOS的制造。
图4示出了各种示例中的说明性LDMOS的制造。
图5示出了各种示例中的说明性LDMOS的制造。
图6示出了各种示例中的说明性LDMOS的制造。
图7示出了各种示例中的说明性LDMOS的制造。
图8示出了实施例中制造说明性LDMOS的说明性过程步骤。
具体实施方式
LDMOS以相对高的频率被接通和关断，以降低在某些DC到DC转换器中使用的电感器的大小。然而，由于LDMOS的栅极到源极电容和栅极到漏极电容，高频率开关可导致能量损耗。此外，LDMOS可表现出热载流子退化，由此不利地影响LDMOS特性和可制造性。希望的是提供适合用于高频率开关的LDMOS，带有可接受品质因数RSPQ产品，其中RSP是特定的漏极到源极导通电阻，并且Q是栅极电荷。
在所描述的实施例中，诸如LDMOS的晶体管包括具有抬升区的栅极。抬升区被提议用来帮助降低在LDMOS的栅极与漂移层之间的电容。LDMOS可以包括在LDMOS的结型场效应晶体管(JFET)区中具有圆角的浅沟槽隔离(STI)区。圆角被提议用来帮助改进在STI区与JFET区之间的界面，并且帮助提供降低表面场(RESURF)，以及减轻热载流子退化。在一些实施例中，JFET区的掺杂可以通过JFET区中的自对准注入来进行微调。在所描述的实施例中，LDMOS包括与p型掩埋层相邻的深p型掩埋层，并且对于一些实施例，包括两个n型漂移层，其中p型和n型层具有用于RESURF和用于在高电压操作下提供完全耗尽区的分级掺杂分布。
图1示出了根据实施例的说明性LDMOS 100。说明性LDMOS 100在p型硅衬底102中形成，所述衬底102最初可以是轻掺杂p-到高掺杂p+。为便于说明，图1未示出LDMOS的所有典型元件，诸如作为集成电路器件的BEOL(后段)制造的一部分在硅衬底102中的有源极区之上形成的各种金属和电介质层。图1图示了说明性LDMOS 100的简化横截面，其中所图示的特征未按比例绘制。
在硅衬底102中形成的是n型掩埋层104、p型掩埋层106和p型掩埋层108。在一些实施例中，通过采用800KeV到2.5MeV的能量，将剂量为3·1012cm-2到8·1012cm-2的硼注入到硅衬底102中来形成p型掩埋层106。在一些实施例中，通过以从0°到9°的注入角度，采用800KeV到2MeV的能量，将剂量为1·1012cm-2到2·1013cm-2的硼注入到硅衬底102中来形成p型掩埋层108。
说明性LDMOS 100中的层之间的关系可以被描述为在p型掩埋层106上形成的p型掩埋层108和在n型掩埋层104上形成的p型掩埋层106，其中p型掩埋层108和p型掩埋层106彼此相邻，并且P型掩埋层106和N型掩埋层104彼此相邻。然而，要领会的是，这些层可以不具有在何处一个层停止和相邻层开始的精确限定的边界。
在硅衬底102中形成n型漂移层110和n型漂移层112。在一些实施例中，通过以从0°到9°的注入角度，采用160KeV到1MeV的能量注入剂量为1·1012cm-2到2·1013cm-2的磷来形成n型漂移层110。在一些实施例中，通过以从0°到9°的注入角度，采用25KeV到400KeV的能量，注入剂量为8·1011cm-2到2·1013cm-2的砷来形成n型掩埋层112。n型漂移层110和n型漂移层112可以被描述为彼此相邻，其中n型漂移层112在n型漂移层110上形成。n型漂移层110可以被描述为与p型掩埋层108相邻并且在其上形成。然而，这些层可以不具有在何处一个层停止和相邻层开始的精确限定的边界。
在一些实施例中，形成层104、106、108、110和112的顺序通过在图1中它们的有序图示来暗示，其中在p型掩埋层106之前在硅衬底102中形成n型掩埋层104，并且在形成p型掩埋层106之后形成层p型掩埋层108，之后是形成n型漂移层110，以及随后形成n型漂移层112。对于一些实施例，形成层104、106、108、110和112时，可以利用相同的掩模。
在n型漂移层110中和在n型漂移层112中形成STI区114。在与STI区114相邻的n型漂移层112中形成漏极区116。对于图1的实施例，漏极区116是高掺杂n型。对漏极区116形成触点118，以提供从漏极区116到未示出的其它通孔和金属层的电连接。STI区114是电介质并且可以包括SiO2(二氧化硅)。
栅极120在STI区114的一部分之上的栅极氧化物区119上方形成，并且包含抬升区122。栅极120可以包括多晶硅。因为STI区114具有抬升区124，所以出现了抬升区122，并且抬升区124是由于STI区114的边缘氧化物生长引起的。此生长还造成圆角126，如将在后面更详细所描述的。抬升区122和124被提议用来帮助降低说明性LDMOS 100的栅极到漏极电容，并且圆角126被提议用来提供RESURF。
抬升区122和124可以被描述为彼此接近。在图1的实施例中，此接近是由于在制造期间与STI区114相邻形成栅极120时栅极120与STI区114的表面覆形。
与n型漂移层110和112相邻形成p型体区128，其中对于一些实施例，栅极120可以提供p型体区128的自对准。对于一些实施例，可以在形成栅极120之前形成p型体区128。p型体区128可以被描述为与n型漂移层110和112相邻，使得STI区114被设置在漏极区116与p型体区128之间。可以在p型体区128中形成非重掺杂n型区130，之后是与栅极120相邻沉积间隔层132，之后是形成重掺杂n型区134，使得区130和134提供源极区。体触点136是p型体区128中的重掺杂p型区，以提供与p型体区128的欧姆接触。
在一些实施例中，为形成部分源极区(区130)，可以通过以从0°到9°的注入角度，采用25KeV到160KeV的能量，将剂量为3·1013cm-2到1·1015cm-2的砷注入p型体128的上部区。在一些实施例中，对于体触点136，还可以通过以从7°到35°的注入角度，采用60KeV到260KeV的能量，将剂量为1·1013cm-2到5·1014cm-2的硼注入p-型体128的上部区。在一些实施例中，可以通过以从0°到9°的注入角度，采用300KeV到1.6MeV的能量，将剂量为2·1012cm-2到6·1013cm-2的硼注入p-型体128的底部区，以便为RESURF将p型体128连接到p型掩埋层108。
在源极区(区134)和体触点136上形成触点138。通孔和其它金属层(未示出)被电连接到触点138以提供到p型体128和到源极区(区130和134)的电连接。
彼此靠近并且共享界面的p型体128和n型漂移层112的部分限定了JFET区。在一些实施例中，在形成栅极氧化物区119和栅极120之前，通过注入剂对JFET区中(具体地说与STI区114相邻的n型漂移层112中)的区139进行掺杂，以对JFET区中的电场进行微调。区139与STI区114的圆角126共享圆形界面。区139被称为JFET调整注入区139。
一些实施例可以具有一个p型掩埋层而不是两个p型掩埋层106和108，以及一个n型漂移层而不是两个n型漂移层110和112。然而，在层106、108、110和112具有平衡的掺杂分布的情况下，可在反向偏置下更好地(或完全地)耗尽说明性LDMOS 100，使得可以通过相对小的漂移层来实现较高电压电路。
说明性LDMOS 100是n沟道LDMOS，其中n型区的多数载流子是电子并且p型区的多数载流子是空穴。其它实施例可以互换n型区和p型区，使得可制造p沟道LDMOS。
形成STI区114时可以形成STI区140，其中STI区140帮助提供与其它器件(未示出)的隔离。可以在说明性LDMOS 100旁形成包括n型、p型垂直层和氧化物层的深沟槽以提供进一步的隔离，但是为便于说明，这些层未被示出。
图2图示了根据实施例的说明性LDMOS 100的制造，其中在形成层104、106、108、110和112之后形成STI区114和140。可以通过相同过程步骤来形成STI区114和140，其中其各自的沟槽被蚀刻并且衬有氧化物衬层(未示出)，在氧化物衬层上方沉积氧化物(SIO2)，并且执行CMP(化学机械抛光)。(图1示出了由于在后面的过程步骤中另外的氧化物生长，比如图2中所示的稍微更厚的STI区140)。在STI区114和140及n型漂移层112上方生长牺牲衬垫氧化物层202。
图3图示了根据实施例的说明性LDMOS 100的制造，其中在牺牲衬垫氧化物层202上方形成氮化物(Si3N4)层302和光致抗蚀剂层304。开口图案306被暴露在光致抗蚀剂层304中并且被蚀刻以暴露到氮化物层302的开口，之后是蚀刻到氮化物层302的开口以暴露到牺牲衬垫氧化物层202的开口。
图4图示了根据实施例的说明性LDMOS 100的制造，其中箭头402指示将掺杂剂注入到将成为JFET区的一部分并且将形成JFET调整注入区139的n型漂移层112的该部分的步骤。通过开口将掺杂剂注入到牺牲衬垫氧化物层202。在图4的实施例中，掺杂剂是n型施主。
图5图示了根据实施例的说明性LDMOS 100的制造，图示了从图4的掺杂步骤产生的JFET调整注入区139。对于一些实施例，为形成JFET调整注入区139，可以通过以从0°到9°的注入角度，采用在25KeV到250KeV的能量，注入剂量为6·1011cm-2到9·1012cm-2的磷或砷，以补偿界面状态和降低JFET区电阻。
掺杂说明性LDMOS 100的JFET区以提供JFET调整注入区139能够降低JFET区电阻并且允许调整JFET区中的电场。用以提供JFET区、n型漂移层110和112以及p型掩埋层106和108的掺杂分布的链注入允许对性能与栅极长度(即，与栅极120关联的栅极长度)、热载流子和漂移层电阻进行折衷。掺杂分布能够帮助屏蔽在到STI区114的侧壁(例如，图1中的圆角126)的p型体区128与到STI区114的底部下方的n型漂移层110的该部分的p型掩埋层108之间的电场。这能够帮助减轻所得小沟道的表面贯穿，使得说明性LDMOS 100可以实现带有低泄漏和降低的栅极到源极电容的相对小的栅极长度。
图6图示了根据实施例的说明性LDMOS 100的制造。去除光致抗蚀剂层304，之后进行在开口上到牺牲衬垫氧化物层202的热氧化物生长，从而产生抬升区124。在一些实施例中，在到牺牲衬垫氧化物层202的开口上生长的另外的氧化物可以具有大于200埃的厚度，诸如从360埃到1600埃，并且在760℃到990℃之间的温度下生长。牺牲衬垫氧化物层202在最先形成时是大约100埃厚，使得由于热生长引起的另外的氧化物实质上大于牺牲衬垫氧化物层202的初始厚度。附图未按比例绘制，瓶因此没有描绘氧化物生长相对于牺牲衬垫氧化物层202的比例。还存在STI区114到n型漂移层112中的生长，从而产生圆角126。
图7图示了根据实施例的说明性LDMOS 100的制造。在图6中描绘的氧化物的热生长之后，剥离氮化物层302，为体区沉积、图案化和蚀刻光致抗蚀剂层(未示出)，并且注入掺杂剂以形成体区128。去除光致抗蚀剂层，并且去除牺牲衬垫氧化物层202。因为由于热生长引起的氧化物厚度远大于牺牲衬垫氧化物层202的初始厚度，所以牺牲衬垫氧化物层202的去除仍然在抬升区124中留下了氧化物的相对大的厚度。在去除牺牲衬垫氧化物层202之后热生长高质量的栅极氧化物，产生了图7中所描绘的氧化物层119。
如图7中所示，在部分体区128、n型漂移层112和JFET调整注入区139及STI区114的一部分上方的氧化物层119上形成栅极120。通过在氧化物层119上沉积多晶硅，在多晶硅上沉积光致抗蚀剂层，图案化并蚀刻掉光致抗蚀剂层的暴露部分以暴露多晶硅的不需要部分，之后是去除不需要的多晶硅，可以形成栅极120。可以在多晶硅上形成硅化物以降低其薄层电阻。当沉积多晶硅以形成栅极120时，由于氧化物层119中的抬升区124，栅极120形成抬升区122。执行另外的过程步骤以制造源极区(区130和134)、体触点136和漏极区116。
图8描绘了在实施例中制造说明性LDMOS 100的说明性过程。在步骤802中，在半导体衬底中形成第一和第二p型掩埋层。在步骤804中，在第二n型第二漂移层之上形成第一n型漂移层。在步骤806中，在第一n型漂移层中形成STI区。在步骤808中，生长牺牲衬垫氧化物层，并且在牺牲衬垫氧化物层上方沉积氮化物层。
在步骤810中，沉积，光刻暴露、烘烤并且蚀刻光致抗蚀剂层以暴露到氮化物层的开口。在步骤812中，蚀刻到氮化物层的开口以暴露到牺牲衬垫氧化物层的开口。在步骤814中，通过经开口向牺牲衬垫氧化物层注入施主来掺杂第一n型漂移层中的区。此区将在形成p型体区128时是JFET区的一部分，并且已在前面被称为JFET调整注入区。
在去除光致抗蚀剂层之后，在步骤816中，热生长到牺牲衬垫氧化物层的开口。在步骤818中，去除氮化物层并且形成体区。在步骤820中，去除牺牲衬垫氧化物层(留下步骤816的大部分的氧化物生长)，并且生长高质量栅极氧化物。在步骤822中，栅极被沉积在氧化物上方，并且使用光致抗蚀剂层被图案化和蚀刻以形成栅极。在剩余步骤中，形成说明性LDMOS 100的其它基本组件。例如，在步骤824中，在第一n型漂移层中形成n型漏极区，并且在p型体区中形成n型源极区。在步骤826中，在p型体区中形成体触点。
图8概述了用以制造说明性LDMOS 100的一些基本步骤，但是一些步骤对于一些实施例是可选的。例如，一些实施例可以不具有JFET调整注入区139，并且一些实施例可以具有一个p型掩埋层或一个n型漂移层。此外，图8中所图示的步骤的顺序不一定意味着制造过程中步骤的具体顺序。
在权利要求的范围内，在所描述的实施例中的修改是可能的，并且其它实施例是可能的。

Claims (20)

1.一种晶体管，其包括：
半导体；
在所述半导体中形成的第一漂移层，所述第一漂移层具有第一类型的多数载流子；
在所述第一漂移层中形成的漏极区，所述漏极区具有所述第一类型的多数载流子；
在所述半导体中形成的体区，所述体区具有第二类型的多数载流子；
在所述体区中形成的源极区，所述源极区具有所述第一类型的多数载流子；
浅沟槽隔离区，其在所述第一漂移层中形成并且被设置在所述漏极区与所述体区之间；
在所述半导体上形成的电介质；以及
在所述电介质上方并且具有抬升区的栅极。
2.根据权利要求1所述的晶体管，其进一步包括：
在所述第一漂移层中形成的掺杂区，所述掺杂区具有所述第一类型的多数载流子。
3.根据权利要求1所述的晶体管，所述电介质具有在所述栅极的所述抬升区下的抬升区。
4.根据权利要求1所述的晶体管，所述掺杂区与所述浅沟槽隔离区共享圆形界面。
5.根据权利要求4所述的晶体管，其中所述圆形界面降低在所述晶体管的操作期间的局部电场。
6.根据权利要求1所述的晶体管，其进一步包括：
在所述半导体中形成的第二漂移层，所述第二漂移层具有所述第一类型的多数载流子。
7.一种方法，其包括：
在半导体中形成具有第一类型的多数载流子的第一漂移层；
在所述第一漂移层中形成浅沟槽隔离区；
在所述半导体上方生长衬垫氧化物层；
在所述衬垫氧化物层上方沉积氮化物层；
在所述氮化物层上方沉积光致抗蚀剂层；
在所述光致抗蚀剂层中暴露开口图案；
基于所述开口图案在所述光致抗蚀剂层中蚀刻开口，以暴露到所述氮化物层的开口；
蚀刻到所述氮化物层的所述开口，以暴露到所述衬垫氧化物层的开口；
去除所述光致抗蚀剂层；
在到所述衬垫氧化物层的所述开口上生长氧化物；
去除所述氮化物层；
去除所述衬垫氧化物层，留下在所述衬垫氧化物层上生长的所述氧化物的至少一部分；
生长栅极氧化物层；
在所述栅极氧化物层上形成栅极；
在所述第一漂移层中形成具有所述第一类型的多数载流子的漏极区；
在所述半导体中形成具有第二类型的多数载流子的体区；以及
在所述体区中形成具有所述第一类型的多数载流子的源极区。
8.根据权利要求7所述的方法，其中在到所述衬垫氧化物层的所述开口上生长所述氧化物包含生长所述氧化物到至少200埃的厚度。
9.根据权利要求7所述的方法，所述方法进一步包括：
通过所述开口将掺杂剂注入到所述衬垫氧化物层以提供所述第一类型的多数载流子。
10.根据权利要求9所述的方法，其中所述第一类型的所述多数载流子是电子，并且所述第二类型的所述多数载流子是空穴，其中通过所述开口将掺杂剂注入到所述衬垫氧化物层包含以从0°到9°的注入角度，采用25KeV到250KeV的范围中的能量注入剂量为6·1011cm-2到9·1012cm-2的磷或砷。
11.根据权利要求10所述的方法，其中在到所述衬垫氧化物层的所述开口上生长所述氧化物包含生长所述氧化物到至少200埃的厚度。
12.根据权利要求7所述的方法，其中所述半导体包括硅，并且所述氧化物、所述衬垫氧化物层和所述栅极氧化物层各自包括二氧化硅，其中在到所述衬垫氧化物层的所述开口上生长所述氧化物包括使所述半导体氧化。
13.根据权利要求7所述的方法，其进一步包括：
在所述半导体中形成具有所述第一类型的多数载流子的第二漂移层。
14.根据权利要求13所述的方法，其中
在所述半导体中形成所述第一漂移层包括以从0°到9°的注入角度，采用25KeV到400KeV的能量在所述半导体中注入剂量为8·1011cm-2到2·1013cm-2的砷；以及
在所述半导体中形成所述第二漂移层包括以从0°到9°的注入角度，采用160KeV到1MeV的能量在所述半导体中注入剂量为1·1012cm-2到2·1013cm-2的磷。
15.根据权利要求13所述的方法，其进一步包括：
在所述半导体中形成具有所述第二类型的多数载流子的第一掩埋层。
16.根据权利要求15所述的方法，其中
在所述半导体中形成所述第一漂移层包括以从0°到9°的注入角度，采用25KeV到400KeV的能量在所述半导体中注入剂量为8·1011cm-2到2·1013cm-2的砷；
在所述半导体中形成所述第二漂移层包括以从0°到9°的注入角度，采用160KeV到1MeV的能量在所述半导体中注入剂量为1·1012cm-2到2·1013cm-2的磷；以及
在所述半导体中形成所述第一掩埋层包括以从0°到9°的注入角度，采用800KeV到2MeV的能量将剂量为1·1012cm-2到2·1013cm-2的硼注入到所述半导体中。
17.根据权利要求15所述的方法，其进一步包括：
在所述半导体中形成具有所述第二类型的多数载流子的第二掩埋层。
18.一种晶体管，其包括：
半导体；
在所述半导体中形成的第一漂移层，所述第一漂移层具有第一类型的多数载流子；
在所述第一漂移层中形成的漏极区，所述漏极区具有所述第一类型的多数载流子；
在所述半导体中形成的体区，所述体区具有第二类型的多数载流子；
在所述体区中形成的源极区，所述源极区具有所述第一类型的多数载流子；
浅沟槽隔离区，其在所述第一漂移层中形成并且被设置在所述漏极区与所述体区之间；
在所述半导体上形成的电介质；以及
在所述第一漂移层中形成的掺杂区，所述掺杂区具有所述第一类型的多数载流子。
19.根据权利要求18所述的晶体管，所述掺杂区与所述浅沟槽隔离区共享圆形界面。
20.根据权利要求19所述的晶体管，其中所述圆形界面降低在所述晶体管的操作期间的局部电场。
CN201880068026.6A 2017-10-19 2018-10-18 具有带抬升区的栅极的晶体管 Pending CN111226306A (zh)

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018125518A (ja) * 2017-02-03 2018-08-09 ソニーセミコンダクタソリューションズ株式会社 トランジスタ、製造方法
KR102227666B1 (ko) * 2017-05-31 2021-03-12 주식회사 키 파운드리 고전압 반도체 소자
JP7195167B2 (ja) * 2019-02-08 2022-12-23 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040251492A1 (en) * 2003-06-13 2004-12-16 John Lin LDMOS transistors and methods for making the same
US20120299093A1 (en) * 2011-05-27 2012-11-29 Min-Hwan Kim Semiconductor device
US20140070315A1 (en) * 2008-10-29 2014-03-13 Tower Semiconductor Ltd. Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure
CN103996710A (zh) * 2013-02-18 2014-08-20 飞兆半导体公司 具有双斜坡场板的ldmos器件
US20140312417A1 (en) * 2013-04-17 2014-10-23 Infineon Technologies Dresden Gmbh Semiconductor Device and Method of Manufacturing a Semiconductor Device
CN104241384A (zh) * 2014-09-23 2014-12-24 矽力杰半导体技术(杭州)有限公司 横向双扩散金属氧化物半导体晶体管及其制造方法
US20150155379A1 (en) * 2013-12-03 2015-06-04 Vanguard International Semiconductor Corporation Semiconductor device and method for fabricating the same
US9214548B1 (en) * 2014-11-07 2015-12-15 SK Hynix Inc. High voltage integrated devices, methods of fabricating the same, electronic devices including the same, and electronic systems including the same
US20160190269A1 (en) * 2014-12-30 2016-06-30 International Business Machines Corporation Tapered gate oxide in ldmos devices

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531355B2 (en) * 1999-01-25 2003-03-11 Texas Instruments Incorporated LDMOS device with self-aligned RESURF region and method of fabrication
US20020063263A1 (en) * 2000-11-30 2002-05-30 Scott David B. Metal oxide semiconductor transistor with self-aligned channel implant
KR100948139B1 (ko) * 2003-04-09 2010-03-18 페어차일드코리아반도체 주식회사 높은 브레이크다운 전압 및 낮은 온 저항을 위한 다중전류 이동 경로를 갖는 수평형 이중-확산 모스 트랜지스터
WO2005084221A2 (en) * 2004-03-01 2005-09-15 International Rectifier Corporation Self aligned contact structure for trench device
KR100859486B1 (ko) * 2006-09-18 2008-09-24 동부일렉트로닉스 주식회사 고전압용 정전기 방전 보호 소자 및 그 제조 방법
DE102010014370B4 (de) * 2010-04-09 2021-12-02 X-Fab Semiconductor Foundries Ag LDMOS-Transistor und LDMOS - Bauteil
US8822291B2 (en) * 2012-01-17 2014-09-02 Globalfoundries Singapore Pte. Ltd. High voltage device
KR101883010B1 (ko) * 2012-08-06 2018-07-30 매그나칩 반도체 유한회사 반도체 소자 및 그 소자의 제조 방법
CN104377244A (zh) 2013-08-15 2015-02-25 无锡华润上华半导体有限公司 一种降低ldmos导通电阻的器件结构
JP6189771B2 (ja) * 2014-03-03 2017-08-30 ルネサスエレクトロニクス株式会社 半導体装置
JP6284421B2 (ja) * 2014-05-09 2018-02-28 ルネサスエレクトロニクス株式会社 半導体装置
US9660074B2 (en) * 2014-08-07 2017-05-23 Texas Instruments Incorporated Methods and apparatus for LDMOS devices with cascaded RESURF implants and double buffers
KR101699585B1 (ko) * 2014-09-24 2017-01-24 주식회사 동부하이텍 고전압 반도체 소자 및 그 제조 방법
US9443958B2 (en) * 2014-10-06 2016-09-13 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device and method of forming the same
KR102177431B1 (ko) * 2014-12-23 2020-11-11 주식회사 키 파운드리 반도체 소자
JP6509665B2 (ja) * 2015-07-23 2019-05-08 ルネサスエレクトロニクス株式会社 半導体装置
US9905428B2 (en) * 2015-11-02 2018-02-27 Texas Instruments Incorporated Split-gate lateral extended drain MOS transistor structure and process
US9461046B1 (en) * 2015-12-18 2016-10-04 Texas Instruments Incorporated LDMOS device with graded body doping
US9583612B1 (en) * 2016-01-21 2017-02-28 Texas Instruments Incorporated Drift region implant self-aligned to field relief oxide with sidewall dielectric
US9905688B2 (en) * 2016-01-28 2018-02-27 Texas Instruments Incorporated SOI power LDMOS device
RU2639579C2 (ru) 2016-03-31 2017-12-21 Акционерное общество "Научно-производственное предприятие "Пульсар" Способ изготовления мощных кремниевых свч ldmos транзисторов с модернизированным затворным узлом элементарных ячеек
US10256340B2 (en) * 2016-04-28 2019-04-09 Vanguard International Semiconductor Corporation High-voltage semiconductor device and method for manufacturing the same
CN107492495A (zh) * 2016-06-12 2017-12-19 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
TWI604619B (zh) * 2016-09-02 2017-11-01 新唐科技股份有限公司 二極體、接面場效電晶體以及半導體元件
JP6710627B2 (ja) * 2016-12-20 2020-06-17 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6726092B2 (ja) * 2016-12-28 2020-07-22 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040251492A1 (en) * 2003-06-13 2004-12-16 John Lin LDMOS transistors and methods for making the same
US20140070315A1 (en) * 2008-10-29 2014-03-13 Tower Semiconductor Ltd. Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure
US20120299093A1 (en) * 2011-05-27 2012-11-29 Min-Hwan Kim Semiconductor device
CN103996710A (zh) * 2013-02-18 2014-08-20 飞兆半导体公司 具有双斜坡场板的ldmos器件
US20140312417A1 (en) * 2013-04-17 2014-10-23 Infineon Technologies Dresden Gmbh Semiconductor Device and Method of Manufacturing a Semiconductor Device
US20150155379A1 (en) * 2013-12-03 2015-06-04 Vanguard International Semiconductor Corporation Semiconductor device and method for fabricating the same
CN104241384A (zh) * 2014-09-23 2014-12-24 矽力杰半导体技术(杭州)有限公司 横向双扩散金属氧化物半导体晶体管及其制造方法
US9214548B1 (en) * 2014-11-07 2015-12-15 SK Hynix Inc. High voltage integrated devices, methods of fabricating the same, electronic devices including the same, and electronic systems including the same
US20160190269A1 (en) * 2014-12-30 2016-06-30 International Business Machines Corporation Tapered gate oxide in ldmos devices

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