CN111224734B

CN111224734B - Synchronization system for large-scale acquisition array

Info

Publication number: CN111224734B
Application number: CN202010297523.2A
Authority: CN
Inventors: 王志欣; 张吉林; 陈开国; 王维; 陈世朴; 费鑫; 叶云涛; 石璞
Original assignee: Ksw Technologies Co ltd
Current assignee: Ksw Technologies Co ltd
Priority date: 2020-04-16
Filing date: 2020-04-16
Publication date: 2020-07-17
Anticipated expiration: 2040-04-16
Also published as: CN111224734A

Abstract

The invention discloses a synchronization system of large-scale collection arrays, which forms a collection array supporting N M L, wherein N, M and L can be adjusted according to specific conditions, namely, the number and the type of each collection device, daughter card and collector can be flexibly expanded, clock signals and synchronization signals are distributed layer by layer to form a tree structure, and the distribution process only involves PCB wiring, chip internal wiring and signal frequency division, thereby forming a tree structure with fixed homologies and phase relations.

Description

Synchronization system for large-scale acquisition array

Technical Field

The invention relates to the technical field of communication, in particular to a synchronization system for a large-scale acquisition array.

Background

In the application of airplane test flight measurement and control, due to the reasons of more test points, scattered test points and the like, a plurality of devices are often adopted to complete on-site acquisition and monitoring; meanwhile, due to special requirements of application, for example, a vibration noise monitoring system of large-scale aircraft mechanical equipment, the scattered measuring points must be synchronously acquired, and the whole state of the equipment can be completely and accurately analyzed. The synchronous acquisition here requires not only that all test channels start to acquire at the same time, but also that all channels share a clock signal. In the traditional multi-device synchronization, two digital signals, namely a trigger signal and a reference clock, need to be shared between devices, and then the two digital signals are respectively collected and processed to realize the synchronization. Because two independent signal links are needed to be used for transmission between the devices, the problem of phase delay error between signals exists, and synchronization precision between the devices is affected.

With the continuous development of communication technology, the size and the requirements of the acquisition array are higher and higher. How to efficiently and stably realize the synchronization of the large-scale acquisition array becomes a crucial problem. The traditional method needs a large amount of structural analysis, static time sequence analysis and constraint of an acquisition system and a fussy debugging process, and is low in efficiency and reliability.

Based on the synchronous system, a large-scale acquisition array synchronous system is developed, the basic working principle of the system is given, and the real-time transmission of test flight test data of the testing machine is realized through the onboard modification.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provide a synchronization system of a large-scale acquisition array.

The purpose of the invention is realized by the following technical scheme:

a synchronization system of a large-scale acquisition array comprises a synchronization signal distribution device, a plurality of acquisition devices, a plurality of acquisition device daughter cards and a plurality of collectors;

the synchronous signal distribution equipment distributes N paths of clock signals and N paths of synchronous signals to the acquisition equipment through a clock and synchronous signal distribution module arranged in the synchronous signal distribution equipment;

the acquisition equipment distributes M paths of clock signals and M paths of synchronous signals to an acquisition equipment daughter card through a synchronous signal distribution module arranged in the acquisition equipment daughter card;

the acquisition equipment daughter card distributes L paths of clock signals and L paths of synchronous signals to the acquisition device through a synchronous signal distribution module arranged in the acquisition equipment daughter card;

the acquisition equipment daughter card is internally provided with a synchronous signal automatic alignment module, the synchronous signal automatic alignment module is realized by adopting an FPGA (field programmable gate array), and the synchronous signal automatic alignment module comprises an acquisition data processing module, a first synchronous control module and a second synchronous control module; the synchronous signal automatic alignment module has two working modes, specifically as follows:

the first working mode is as follows: the clock signal and the synchronous signal are sequentially transmitted to the collector after passing through the collected data processing module and the first synchronous control module; that is, the first synchronization control module continuously changes the delay amount of the synchronization signal, acquires the feedback provided by the collector, performs comprehensive analysis on all the feedback provided by the collector, selects an optimal delay amount (the delay amount is a TAP value), and sends the synchronization signal to the collector in this state to synchronize the collector;

the first synchronous control module completes adjustment of synchronous signals based on ODE L AY of an FPGA device, the adjustment process is controlled by embedded software FPGA _ PS _ SDK integrated in the FPGA, synchronous signal distribution equipment continuously sends periodic pulse signals at the initial power-on stage, the SDK calls a function get _ syncTap () module to obtain an optimal TAP value in the period, when the collector adopts an AD9684 chip, the function get _ syncTap () module continuously triggers AD9684 to carry out synchronous operation in a register writing mode, and a status register of each operation is read back, and the method comprises the following specific steps:

first, the function get _ syncTap () module automatically determines the TAP value of the ODE L AY;

secondly, judging each TAP value for N times, wherein the judgment times N can be adapted to configuration;

thirdly, when the function get _ syncTap () module judges the TAP value each time, the function get _ syncTap () module allocates a weight value for the TAP value, the weight value means the availability, the larger the weight value is, the higher the availability is, and an optimal TAP value is returned according to the availability; wherein the content of the first and second substances,

according to TAP value historical data read by the function get _ syncTap () module and the characteristics of TAP values, a weight value comparison table corresponding to the TAP value historical data is made, so that all TAP values read by the function get _ syncTap () module can find corresponding weight values in the weight value comparison table; then, the function get _ syncTap () module judges whether the TAP value is the optimal TAP value according to the weight value corresponding to the TAP;

in the second working mode, a clock signal and a synchronous signal are sequentially transmitted to the collector after passing through the collected data processing module and the second synchronous control module, namely, the second synchronous control module finishes the adjustment of the synchronous signal based on the IDE L AY of the FPGA device, the synchronous signal distribution equipment continuously transmits periodic pulse signals at the initial power-on stage, and the optimal TAP value is obtained through the ex _ trig _ TAP module and the ex _ trig _ chk module of the FPGA device in the period;

the ex _ trig _ TAP module periodically controls and changes the TAP value of the IDE L AY, the ex _ trig _ chk module continuously detects the test result of the current TAP, and the ex _ trig _ TAP module records the test result of the current TAP value, so that the result is only PASS and FAI L possible;

the ex _ trig _ TAP module automatically analyzes the test results of the 32 TAPs and outputs an optimal TAP value;

the determination process of the ex _ trig _ chk module is as follows:

step 1, resetting two decision counters;

step 2, waiting for N clock signals;

step 3, judging whether the counters are fixed during the waiting period, if so, judging PASS this time and recording the judgment result, and if not, judging FA LL this time and recording the judgment result;

step 4, whether the TAP number of times is modified reaches 32 times or not, if not, the step 1 is returned, if yes, at least Z continuous PASS are determined as an effective segment, the number X of the effective segments is obtained, and the length Y of each effective segment, a starting point and an ending point are obtained;

step 5, judging whether the length of the longest effective segment is larger than a configuration value, if so, taking an intermediate value according to the starting position and the ending position of the effective segment and quitting the process, and if not, reporting a hardware error and quitting the process;

the synchronization signal automatic alignment module is further used for synchronization signal alignment check, and the step flow of the synchronization signal alignment check is as follows:

s1: setting an error threshold range between the optimal TAP value of the common working mode and the optimal TAP value of the inspection working mode, wherein the error threshold range can be adaptively set;

s2: setting a check waiting time period, starting synchronous signal alignment check every time the check waiting time period passes, namely entering the step S3, wherein the check waiting time period can be set adaptively;

s3: and obtaining the optimal TAP value of the common working mode and the optimal TAP value of the inspection working mode, obtaining an optimal TAP difference value between the common working mode and the inspection working mode, comparing and judging the optimal TAP difference value and the error threshold range, judging that the synchronous signal alignment inspection result is qualified if the optimal TAP difference value is in the error threshold range, otherwise, judging that the synchronous signal alignment inspection result is unqualified, and feeding back the inspection result to the acquisition equipment.

The specific content that the error threshold range in step S1 can be set adaptively is:

acquiring historical data of all TAP values in a common working mode, and acquiring historical data of all TAP values in a checking working mode;

calculating the difference value between each TAP value in the common working mode and each TAP value in the inspection working mode, and recording the corresponding difference value;

and listing the recorded corresponding difference values into a difference value recording table, wherein all the difference values in the difference value recording table form the error threshold value range.

Furthermore, a first collected data preprocessing module and a first signal processing module are configured inside the collecting device;

the first signal processing module respectively stores the obtained multiple paths of first quantized digital signals and processes the multiple paths of first quantized digital signals to further obtain first sampling data corresponding to the first quantized digital signals, and distributes the sampling analog signals corresponding to the first sampling data to the acquisition equipment daughter card, M paths of clock signals and M paths of synchronous signals;

the output of the acquisition equipment adopts a first display module, and the first display module is connected with the first signal processing module and used for reading and displaying first sampling data in the first display module;

the first signal processing module circularly reads the multiple paths of first quantized digital signals input by the first acquisition data preprocessing module by adopting a serial digital processing method, and performs first quantized digital signal processing to obtain first sampling data corresponding to the first quantized digital signals.

Furthermore, a second collected data preprocessing module and a second signal processing module are configured inside the collecting equipment daughter card;

the M paths of clock signals and the M paths of synchronous signals are sent to a second acquired data preprocessing module through a second power distribution module, the second acquired data preprocessing module takes the M paths of clock signals and the M paths of synchronous signals as sampling standards of the second acquired data preprocessing module, converts sampling analog signals corresponding to the first sampling data input by the first signal processing module into digital signals, performs frequency reduction, sampling reduction and data bit width adjustment processing on the digital signals to obtain second quantized digital signals, outputs the second quantized digital signals to a second signal processing module, respectively stores the obtained multiple paths of second quantized digital signals, processes the multiple paths of second quantized digital signals to further obtain second sampling data corresponding to the second quantized digital signals, and distributes the sampling analog signals, L paths of clock signals and L paths of synchronous signals corresponding to the second sampling data to the collector;

the output of the acquisition equipment daughter card adopts a second display module, and the second display module is connected with the second signal processing module and used for reading and displaying second sampling data in the second display module;

and the second signal processing module circularly reads the multiple paths of second quantized digital signals input by the second acquired data preprocessing module by adopting a serial digital processing method, and processes the second quantized digital signals to obtain second sampling data corresponding to the second quantized digital signals.

Furthermore, a second synchronous signal detection module, a second synchronous signal alignment judgment module, a second threshold synchronous signal storage module and a second synchronous signal abnormity alarm module are configured in the acquisition equipment daughter card; wherein the content of the first and second substances,

the second synchronous signal detection module is used for collecting and detecting M paths of synchronous signals received by the acquisition equipment daughter card and sending the M paths of synchronous signals to the second synchronous signal alignment judgment module when the result of the synchronization signal alignment inspection fed back to the acquisition equipment by the acquisition equipment daughter card is unqualified;

the second threshold synchronization signal storage module is used for storing a second threshold synchronization signal and calling the second threshold synchronization signal alignment judgment module;

the second synchronous signal alignment judgment module is used for dividing the received M paths of synchronous signals into M paths of independent synchronous signals, respectively aligning and judging the M paths of independent synchronous signals with a second threshold synchronous signal, if the M paths of independent synchronous signals are consistent with the second threshold synchronous signal, the second synchronous signal alignment judgment module feeds back to the second signal processing module to enable the second signal processing module to normally act, otherwise, the second synchronous signal alignment judgment module feeds back to the second signal processing module to enable the second signal processing module to stop distributing sampling analog signals, L paths of clock signals and L paths of synchronous signals corresponding to the second sampling data to the collector, and sends a driving control signal to the second synchronous signal abnormity alarm module;

the second synchronous signal abnormity alarm module is used for alarming abnormity when receiving the corresponding drive control signal;

if the M paths of independent synchronous signals are all inconsistent with a second threshold synchronous signal, the second synchronous signal alignment judgment module acquires a deviation value between the M paths of independent synchronous signals and the second threshold synchronous signal;

the second synchronization signal alignment judgment module compares the deviation value with a preset deviation threshold range, wherein the deviation threshold range comprises a first deviation threshold range and a second deviation threshold range;

if the deviation value falls within the range of the first deviation threshold value, the second synchronous signal alignment judgment module controls the second synchronous signal abnormity alarm module to send out a corresponding abnormity alarm, namely, maintenance personnel need to debug the synchronous signal automatic alignment module in the acquisition equipment daughter card;

and if the deviation value falls within the second deviation threshold range, the second synchronous signal alignment judgment module controls the second synchronous signal abnormity alarm module to send out a corresponding abnormity alarm, namely, the maintainer does not debug the synchronous signal automatic alignment module in the acquisition equipment daughter card temporarily and drives the first synchronous signal detection module in the acquisition equipment to act.

Furthermore, a first synchronous signal detection module, a first synchronous signal alignment judgment module, a first threshold synchronous signal storage module and a first synchronous signal abnormity alarm module are arranged in the acquisition equipment; wherein the content of the first and second substances,

the first synchronous signal detection module is used for acquiring and detecting N paths of synchronous signals received by the acquisition equipment and sending the N paths of synchronous signals to the first synchronous signal alignment judgment module when the second synchronous signal alignment judgment module drives the first synchronous signal detection module;

the first threshold value synchronous signal storage module is used for storing a first threshold value synchronous signal and calling the first threshold value synchronous signal alignment judgment module;

the first synchronous signal alignment judgment module is used for dividing the received N paths of synchronous signals into N paths of independent synchronous signals, respectively aligning and judging the N paths of independent synchronous signals with a first threshold synchronous signal, if the N paths of independent synchronous signals are consistent with the first threshold synchronous signal, the first synchronous signal alignment judgment module feeds back to the first signal processing module to enable the first signal processing module to normally act, otherwise, the first synchronous signal alignment judgment module feeds back to the first signal processing module to enable the first signal processing module to stop distributing sampling analog signals, M paths of clock signals and M paths of synchronous signals corresponding to the first sampling data to the acquisition equipment daughter card; and sending a driving control signal to the first synchronous signal abnormity alarm module;

and the first synchronous signal abnormity alarm module is used for alarming abnormity when receiving the corresponding drive control signal.

Furthermore, a first synchronous signal alignment secondary judgment module is also configured in the acquisition equipment;

when the first synchronization signal alignment judgment module judges that the N paths of independent synchronization signals are consistent with a first threshold synchronization signal, the first synchronization signal alignment judgment module feeds back to the first signal processing module to enable the first signal processing module to normally act;

the first synchronous signal alignment judgment module also sends a corresponding driving control signal to the first synchronous signal alignment secondary judgment module;

when the first synchronous signal alignment secondary judgment module receives the corresponding driving control signal, N paths of synchronous signals are directly obtained from the first synchronous signal detection module and are separated into N paths of independent synchronous signals, then the first threshold synchronization signal is called directly from the first threshold synchronization signal storage module, further, the N paths of independent synchronous signals are respectively aligned with the first threshold synchronous signal, if the N paths of independent synchronous signals are consistent with the first threshold synchronous signal, the first synchronous signal alignment secondary judgment module stops acting, otherwise, the first synchronous signal alignment secondary judgment module feeds back to the first signal processing module, so that the first signal processing module stops distributing the sampling analog signal, the M paths of clock signals and the M paths of synchronous signals corresponding to the first sampling data to the acquisition equipment daughter card; and sending a driving control signal to the first synchronous signal abnormity alarm module;

the alignment judgment algorithm in the first synchronization signal alignment secondary judgment module is different from that of the first synchronization signal alignment judgment module, but the input and the output of the two modules are correspondingly universal.

Furthermore, a second synchronous signal alignment secondary judgment module is also configured inside the acquisition equipment daughter card;

when the second synchronization signal alignment judgment module judges that the M paths of independent synchronization signals are consistent with a second threshold synchronization signal, the second synchronization signal alignment judgment module feeds back to the second signal processing module to enable the second signal processing module to normally act;

the second synchronous signal alignment judgment module also sends a corresponding driving control signal to the second synchronous signal alignment secondary judgment module;

when the second synchronous signal alignment secondary judgment module receives the corresponding drive control signal, M paths of synchronous signals are directly obtained from the second synchronous signal detection module, the M paths of synchronous signals are divided into M paths of independent synchronous signals, then a second threshold synchronous signal is directly called from the second threshold synchronous signal storage module, the M paths of independent synchronous signals are respectively aligned and judged with the second threshold synchronous signal, if the M paths of independent synchronous signals are consistent with the second threshold synchronous signal, the second synchronous signal alignment secondary judgment module stops acting, otherwise, the second synchronous signal alignment secondary judgment module feeds back to the second signal processing module, so that the second signal processing module stops distributing sampling analog signals, L paths of clock signals and L paths of synchronous signals corresponding to the second sampling data to the collector, and sends the drive control signal to a second synchronous signal abnormity alarm module;

the alignment judgment algorithm in the second synchronization signal alignment secondary judgment module is different from that of the second synchronization signal alignment judgment module, but the input and the output of the second synchronization signal alignment secondary judgment module are correspondingly universal.

The invention has the advantages that 1, an innovation point of the scheme is that the synchronous signal distribution equipment distributes N paths of clock signals and N paths of synchronous signals to the acquisition equipment through the clock and synchronous signal distribution module arranged in the synchronous signal distribution equipment, the acquisition equipment distributes M paths of clock signals and M paths of synchronous signals to the acquisition equipment daughter card through the synchronous signal distribution module arranged in the acquisition equipment daughter card, and the acquisition equipment daughter card distributes L paths of clock signals and L paths of synchronous signals to the collectors through the synchronous signal distribution module arranged in the acquisition equipment daughter card, so that an N x L collector array is formed, N, M and L can be adjusted according to specific conditions, namely the number and the type of each acquisition equipment, daughter card and collector can be flexibly expanded, the clock signals and the synchronous signals are distributed layer by layer to form a tree structure, only PCB (printed circuit board), chip internal and signal frequency division wiring are involved in the distribution process, so that a tree structure with fixed homologous and phase relations is formed, the structure is simple to implement, relative or absolute delay relations among the signals are not needed to be analyzed, the array configuration is large, the expandability is strong, and the configuration scale of the array can be changed.

2. The invention has the innovation points that a synchronous signal automatic alignment module is arranged in a collecting equipment sub-card and is realized by adopting an FPGA (field programmable gate array), the synchronous signal automatic alignment module comprises a collected data processing module, a first synchronous control module and a second synchronous control module, the synchronous signal automatic alignment module has two working modes, one mode is that a clock signal and a synchronous signal are sequentially sent to a collector after passing through the collected data processing module and the first synchronous control module, namely, the first synchronous control module continuously changes the delay of the synchronous signal and obtains the feedback provided by the collector, the first synchronous control module comprehensively analyzes all the feedback provided by the collector and selects an optimal delay, and sends the synchronous signal to the collector under the state to synchronize the collector, the second synchronous control module sends a TAP (TAP) to the collector after sequentially passing through the collected data processing module and the second synchronous control module, namely, the second synchronous control module finishes the adjustment of the synchronous signal based on IDE L AY of the FPGA device, and the power-on synchronous signal distribution equipment sends periodic pulse signals at the initial stage and obtains the optimal trig _ TAP _ alignment value of the FPGA device through a trig _ TAP _ block or a TAP _ chex _ synchronization module.

3. One inventive innovation point of the scheme is as follows: the acquisition equipment and the acquisition equipment daughter card designed by the invention have the advantages of less required external components, high integration, less introduced noise and convenience for field installation and debugging; the working quantity of the AD channels of the first collected data preprocessing module can be flexibly adjusted, the performance of each channel is consistent, and the use requirements under different sampling environments can be met.

4. One inventive innovation point of the scheme is as follows: under the big environment of this scheme, to the collection equipment stage, there is the problem that can't judge and learn whether this stage synchronizing signal aligns, if the collection equipment stage has the condition that synchronizing signal does not align, then later stage to collection equipment daughter card stage and collector stage will be further enlargied. Therefore, to overcome this problem.

In the above scheme, for the acquisition equipment stage, the synchronization signals are correspondingly aligned and judged, the transmission of signals and data from the acquisition equipment stage to the acquisition equipment daughter card stage can be automatically blocked according to the judgment result, the condition that the synchronization signals are not aligned is automatically prevented from being further increased, and technical maintenance personnel can be timely informed through corresponding abnormal alarm prompt.

5. One inventive innovation point of the scheme is as follows: under the big environment of this scheme, to the collection equipment daughter card stage, there is the problem that can't judge and learn whether this stage synchronizing signal aligns, if the collection equipment daughter card stage has the condition that synchronizing signal does not align, then later stage will be further enlargied to the collector stage. Therefore, to overcome this problem. In the above scheme, for the acquisition device daughter card stage, the synchronization signal is subjected to corresponding alignment judgment, and the transmission of the signal and data from the acquisition device daughter card stage to the acquisition device stage can be automatically blocked according to the judgment result, so that the condition that the synchronization signal is not aligned is automatically prevented from being further increased, and a technical maintainer can be timely informed through a corresponding abnormal alarm prompt.

6. One inventive innovation point of the scheme is as follows: in the large environment of the scheme, a crucial process is provided for the alignment judgment process of the first synchronization signal alignment judgment module, and if the module fails, the optimization design of the scheme is unambiguous, so that the verification of the alignment judgment result of the module is very necessary. In the above scheme, for the first synchronization signal alignment secondary judgment module and the first synchronization signal alignment judgment module, the same input is adopted, that is, the N-path synchronization signal and the first threshold synchronization signal are different in the alignment judgment algorithms adopted by the two modules, but the two algorithms have the same function; therefore, when the two inputs are the same, the outputs should be the same under normal conditions. Therefore, when the first synchronization signal alignment secondary judgment module receives the corresponding driving control signal, N paths of synchronization signals are directly obtained from the first synchronization signal detection module, the N paths of synchronization signals are divided into N paths of independent synchronization signals, then the first threshold synchronization signal is directly called from the first threshold synchronization signal storage module, and then the N paths of independent synchronization signals are respectively aligned and judged with the first threshold synchronization signal, if the N paths of independent synchronization signals are all consistent with the first threshold synchronization signal, the first synchronization signal alignment secondary judgment module stops acting, otherwise, the first synchronization signal alignment secondary judgment module feeds back to the first signal processing module, so that the first signal processing module stops distributing the sampling analog signal corresponding to the first sampling data to the acquisition device daughter card, M paths of clock signals and M paths of synchronous signals; the fault is shown in the first synchronous signal alignment secondary judgment module and the first synchronous signal alignment judgment module, and a driving control signal is sent to the first synchronous signal abnormity alarm module to prompt technical maintenance personnel to carry out fault debugging in time; therefore, the situation that the alignment judgment result of the first synchronization signal alignment judgment module is wrong, the acquisition equipment daughter card continues to acquire data, and then the synchronization signals are not aligned is further increased is avoided.

7. The invention has the innovation point that under the large environment of the scheme, a critical process is also provided for the alignment judgment process of the second synchronization signal alignment judgment module, if the module fails, the optimization design of the scheme is unambiguous, and therefore verification of the alignment judgment result of the module is very necessary, in the scheme, the alignment judgment algorithms adopted by the second synchronization signal alignment secondary judgment module and the second synchronization signal alignment judgment module are the same, namely M-path synchronization signals and second threshold synchronization signals, and the two algorithms have the same function, so when the two inputs are the same, the outputs of the two algorithms are the same under normal conditions, therefore, when the second synchronization signal alignment secondary judgment module receives corresponding driving control signals, the M-path synchronization signals are directly obtained from the second synchronization signal detection module, are separated into M-path individual synchronization signals, and then the second synchronization signal alignment signals are directly called from the second threshold synchronization signal storage module, and further the M-path synchronization signals are collected from the second synchronization signal alignment judgment module, and the second synchronization signal acquisition module is used for prompting the second synchronization signal acquisition and sampling of the M-path synchronization signals, otherwise, the second synchronization signal acquisition module is used for prompting the second synchronization signal acquisition module to acquire the M-path synchronization signals and for the second synchronization signals, and for prompting the second synchronization signal acquisition of the second synchronization signal acquisition module to obtain the second synchronization signals, and further prompting the second synchronization signal acquisition module to acquire the second synchronization signal, and to obtain the second synchronization signal, and to prompt the synchronization signal acquisition of the second synchronization signal acquisition module, and to prompt the second synchronization signal acquisition module, and to obtain the synchronization signal of the synchronization signal acquisition module, and to prompt the synchronization signal acquisition module, otherwise, and to prompt the synchronization signal acquisition module to obtain synchronization signal acquisition module, and to prompt the synchronization signal acquisition module to obtain the synchronization signal acquisition module, and to.

Drawings

Fig. 1 is a block diagram of a synchronous acquisition device architecture according to an embodiment of the present invention.

Fig. 2 is a diagram of clock and synchronization signal distribution of a synchronous acquisition device according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of operation signals of a first synchronization control module according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of the operation of the function get _ syncTap () module according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of an automatic judgment flow of the function get _ syncTap () module according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of a second synchronization control module according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of a determination process of the ex _ trig _ chk module according to an embodiment of the present invention.

Fig. 8 is a schematic diagram of the working signals of the decision counter according to the embodiment of the present invention.

Fig. 9 is a schematic diagram of an example of an application device according to an embodiment of the present invention.

Fig. 10 is a schematic internal block diagram of a capture daughter card of an application device example according to the embodiment of the present invention.

Detailed Description

The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.

Example (b):

the first working mode is as follows: the clock signal and the synchronous signal are sequentially transmitted to the collector after passing through the collected data processing module and the first synchronous control module; namely, the first synchronization control module continuously changes the delay amount of the synchronization signal, acquires the feedback provided by the collector, performs comprehensive analysis on all the feedback provided by the collector, selects an optimal delay amount, and sends the synchronization signal to the collector in the state to synchronize the collector;

the determination process of the ex _ trig _ chk module is as follows:

step 1, resetting two decision counters;

step 2, waiting for N clock signals;

On the above basis, preferably, the synchronization signal automatic alignment module further has the following operation modes, specifically:

the first method comprises the following steps: the clock signal and the synchronous signal are sequentially transmitted to the collector after passing through the collected data processing module and the first synchronous control module;

and the second method comprises the following steps: the clock signal and the synchronous signal are sequentially transmitted to the collector after passing through the data acquisition processing module and the second synchronous control module;

and the third is that: the clock signal and the synchronous signal are sequentially transmitted to the collector after passing through the collected data processing module, the first synchronous control module and the second synchronous control module;

and fourthly: the clock signal and the synchronous signal are sequentially transmitted to the collector after passing through the collected data processing module, the second synchronous control module and the first synchronous control module; the working principle of the first synchronous control module is the same as that in the first working mode, and the working principle of the second synchronous control module is the same as that in the second working mode; the above working modes all belong to the protection scope of the scheme.

In the scheme, as shown in fig. 1, a synchronous signal distribution device outputs N paths of clocks and N paths of synchronous signals to acquisition devices for synchronization among the acquisition devices, so that an acquisition array supporting N x M x L can be formed, and simultaneously, the number and types of each acquisition device, daughter card and acquisition device can be flexibly expanded, the specific distribution details of the clocks and the synchronous signals related to the method are introduced below, as shown in fig. 2, the clock signals and the synchronous signals are distributed layer by layer to form a tree structure, the distribution process only relates to PCB wiring, chip internal wiring and signal frequency division, so that a tree structure with fixed homologous and phase relationships is formed, the structure is simple to realize, the relative or absolute delay relationship among the signals is not required to be analyzed, the difficulty and the workload are large if the analysis is carried out, an automatic synchronous signal alignment module adopts an FPGA to realize, the local synchronous signals and external synchronous signals of the daughter card are both properly processed by the two modules, the synchronous signal alignment module adopts an FPGA to realize automatic alignment mode, and the synchronous signal alignment module is divided into two main working modes:

firstly, as shown in fig. 3, a synchronization signal is sent to a collector through a synchronization control module 1, the module continuously changes the delay amount of the synchronization signal and observes that the collector provides feedback, comprehensively analyzes all feedback provided by the collector, selects an optimal delay amount, and sends out the synchronization signal to synchronize the collector in the state, a D L Y1 module in the figure, namely the synchronization control module 1, completes the adjustment of the synchronization signal based on the ODE L AY of the FPGA device, the adjustment process is controlled by an embedded software FPGA _ PS _ SDK integrated in the FPGA, the synchronization signal distribution equipment continuously sends a periodic pulse signal at the initial power-on stage, and the SDK calls a function get _ syncTap () module to obtain an optimal TAP value during the period, taking an AD9684 chip as an example:

as shown in fig. 4 and 5, the function get _ syncTap () module continuously triggers the AD9684 to perform synchronization operation by writing a register, and reads back the status register of each operation.

The function get _ syncTap () module will automatically determine 32 TAPs of ODE L AY and return an optimal TAP value.

The function get _ syncTap () module may make N decisions for each TAP value in order to guarantee the reliability of the decision. The judgment times N can be matched, and are configured to be 256 times at present.

The function get _ syncTap () module has the capability of automatically determining the TAP value. In fig. 4, 6 feedback results provided by the AD9684 chip, and the function get _ syncTap () module assigns a weight value to each state. The meaning of the weight value is availability, the higher the value the higher the availability.

Secondly, as shown in fig. 6, the synchronization signal is processed by the synchronization control module 2, the adjustment of the synchronization signal is completed by adjusting the IDE L AY inside the FPGA, the adjustment process is realized by the FPGA, the synchronization signal distribution device continuously transmits a periodic pulse signal at the initial power-on stage, and the optimal tap value is obtained by the FPGA module ex _ trig _ tap/ex _ trig _ chk during the period.

The ex _ trig _ TAP module periodically controls the change of the TAP value of the IDE L AY, and the ex _ trig _ chk module continuously detects the test result of the current TAP, meanwhile, the ex _ trig _ TAP records the test result of the current TAP, and only two possibilities are PASS and FAI L.

The ex _ trig _ TAP module automatically analyzes the test results of the 32 TAPs and outputs an optimal TAP value.

The determination process of the ex _ trig _ chk module is shown in fig. 7, wherein the right process can also be controlled by using embedded software FPGA _ PS _ SDK integrated in the FPGA to facilitate expansion and upgrade.

As regards the decision counter, this counter is implemented within the ex _ trig _ chk module. As shown in fig. 8.

In order to explain the practical application and effect of the present invention in more detail, the present embodiment will be explained with reference to practical specific application devices. As shown in fig. 9, the number of collectors supported in the system is 4 × 12 × 2=96, where each collector supports 2 channels, thus supporting simultaneous acquisition of a total of 192 channels.

Fig. 10 is an internal block diagram of the acquisition daughter card. The externally supplied clock is distributed by the AD9510 to the AD9684 and to the FPGA. The AD9510 uses a clock distribution mode and bypasses internal dividers.

A clock and synchronous signal distribution module on the acquisition equipment is realized by using an FPGA on a backboard and is distributed to each acquisition daughter card. The synchronous signal provided by the back plate is used for synchronizing the operation in the FPGA, and is converted into a SYNC signal by the FPGA and then sent to the AD 9684. The calibration stage of the externally provided synchronous signal at the initial stage of power-on is a single pulse signal, the pulse width is N clock cycles, and the pulse cycle is 256 clock cycles; and the second pulse is used for unifying the internal operation of the FPGA in the acquisition stage. The SYNC pin of AD9684 is used to synchronize the internal clock and the phase of the digital end slave clock DCO.

The 192 channel data in the case realize the acquisition synchronization function, and the repeated test results are consistent after each power-on.

In the scheme, the acquisition equipment and the acquisition equipment daughter card designed by the scheme have the advantages of less required external components, high integration, less introduced noise and convenience for field installation and debugging; the working quantity of the AD channels of the first collected data preprocessing module can be flexibly adjusted, the performance of each channel is consistent, and the use requirements under different sampling environments can be met.

Under the big environment of this scheme, to the collection equipment daughter card stage, there is the problem of learning whether this stage synchronizing signal aligns, but unclear the offset value between this stage synchronizing signal and the threshold value synchronizing signal, this offset value is unclear can lead to technical maintenance personnel to be unaware of debugging the collection equipment daughter card, still debugs collection equipment, unclear preferred scheme then can lead to the wasting of resources problem, if: after the synchronization signal of the acquisition equipment daughter card is debugged, the problem of deviation cannot be solved, and the synchronization signal of the acquisition equipment still needs to be debugged. Therefore, to overcome this problem.

Under the big environment of this scheme, to the collection equipment stage, there is the problem that can't judge and learn whether this stage synchronizing signal aligns, if the collection equipment daughter card stage has the condition that synchronizing signal does not align, then later stage will be further enlargied to the collector stage. Therefore, to overcome this problem.

In the large environment of the scheme, a crucial process is provided for the alignment judgment process of the first synchronization signal alignment judgment module, and if the module fails, the optimization design of the scheme is unambiguous, so that the verification of the alignment judgment result of the module is very necessary.

In the above scheme, for the first synchronization signal alignment secondary judgment module and the first synchronization signal alignment judgment module, the same input is adopted, that is, the N-path synchronization signal and the first threshold synchronization signal are different in the alignment judgment algorithms adopted by the two modules, but the two algorithms have the same function; therefore, when the two inputs are the same, the outputs should be the same under normal conditions. Therefore, when the first synchronization signal alignment secondary judgment module receives the corresponding driving control signal, N paths of synchronization signals are directly obtained from the first synchronization signal detection module, the N paths of synchronization signals are divided into N paths of independent synchronization signals, then the first threshold synchronization signal is directly called from the first threshold synchronization signal storage module, and then the N paths of independent synchronization signals are respectively aligned and judged with the first threshold synchronization signal, if the N paths of independent synchronization signals are all consistent with the first threshold synchronization signal, the first synchronization signal alignment secondary judgment module stops acting, otherwise, the first synchronization signal alignment secondary judgment module feeds back to the first signal processing module, so that the first signal processing module stops distributing the sampling analog signal corresponding to the first sampling data to the acquisition device daughter card, M paths of clock signals and M paths of synchronous signals; the fault is shown in the first synchronous signal alignment secondary judgment module and the first synchronous signal alignment judgment module, and a driving control signal is sent to the first synchronous signal abnormity alarm module to prompt technical maintenance personnel to carry out fault debugging in time; therefore, the situation that the alignment judgment result of the first synchronization signal alignment judgment module is wrong, the acquisition equipment daughter card continues to acquire data, and then the synchronization signals are not aligned is further increased is avoided.

In the large environment of the scheme, the alignment judgment process of the second synchronization signal alignment judgment module also has a crucial process, and if the module fails, the optimization design of the scheme is unambiguous, so that the verification of the alignment judgment result of the module is very necessary.

In the scheme, the same input is adopted for a second synchronous signal alignment secondary judgment module and a second synchronous signal alignment judgment module, namely M-path synchronous signals and second threshold synchronous signals, the alignment judgment algorithms adopted by the second synchronous signal alignment secondary judgment module and the second synchronous signal alignment judgment module are different, but the functions of the two algorithms are the same, so that the output of the second synchronous signal alignment secondary judgment module and the output of the second synchronous signal alignment secondary judgment module are the same under the normal condition when the input of the second synchronous signal alignment secondary judgment module and the input of the second threshold synchronous signals are the same, the M-path synchronous signals are directly acquired from the second synchronous signal detection module and are divided into M-path independent synchronous signals, then the second threshold synchronous signals are directly called from the second threshold synchronous signal storage module, the M-path independent synchronous signals are respectively aligned and judged with the second threshold synchronous signals, if the M-path independent synchronous signals are all consistent with the second threshold synchronous signals, the second synchronous signal alignment secondary judgment module stops acting, otherwise, the second synchronous signal alignment secondary judgment module feeds back to the second signal processing module, the second synchronous signal alignment secondary judgment module, the second synchronous signal processing module stops the acquisition module and sends a fault acquisition and a fault detection result of the second synchronous signal alignment secondary judgment module, and a failure judgment module 358584, and further prompts a fault acquisition failure judgment module to a failure synchronization signal acquisition failure detection module.

The foregoing is merely a preferred embodiment of the invention, it being understood that the embodiments described are part of the invention, and not all of it. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The invention is not intended to be limited to the forms disclosed herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A synchronization system of a large-scale acquisition array is characterized by comprising a synchronization signal distribution device, a plurality of acquisition devices, a plurality of acquisition device daughter cards and a plurality of collectors;

the first working mode is as follows: the clock signal and the synchronous signal are sequentially transmitted to the collector after passing through the collected data processing module and the first synchronous control module; namely, the first synchronization control module continuously changes the delay amount of the synchronization signal, acquires the feedback provided by the collector, performs comprehensive analysis on all the feedback provided by the collector and selects an optimal delay amount, and sends the synchronization signal to the collector to synchronize the collector after the optimal delay amount is obtained;

the first synchronous control module completes adjustment of synchronous signals based on ODE L AY of an FPGA device, the adjustment process is controlled by embedded software FPGA _ PS _ SDK integrated in the FPGA, synchronous signal distribution equipment continuously sends periodic pulse signals at the initial power-on stage, the SDK calls a function get _ syncTap () module to obtain an optimal TAP value, the TAP value is delay, when the collector adopts an AD9684 chip, the function get _ syncTap () module continuously triggers AD9684 to carry out synchronous operation in a register writing mode, and reads back a state register of each operation, and the method comprises the following specific steps:

the determination process of the ex _ trig _ chk module is as follows:

step 1, resetting two decision counters of an ex _ trig _ chk module;

step 2, waiting for N clock signals;

2. The synchronization system of the large-scale collection array according to claim 1, wherein the collection device is internally configured with a first collection data preprocessing module and a first signal processing module;

the method comprises the steps that N paths of clock signals and N paths of synchronous signals are sent to a first collected data preprocessing module through a first power distribution module of the collecting device, the first collected data preprocessing module takes the N paths of clock signals and the N paths of synchronous signals as sampling standards of the first collected data preprocessing module, sampling analog signals input from outside are converted into digital signals, the digital signals are subjected to frequency reduction, sampling reduction and data bit width adjustment to obtain first quantized digital signals, the first quantized digital signals are output to a first signal processing module, the first signal processing module stores the obtained multiple paths of first quantized digital signals respectively and processes the multiple paths of first quantized digital signals to obtain first sampled data corresponding to the first quantized digital signals, and the first signal processing module distributes the sampling analog signals corresponding to the first sampled data to a collecting device sub-card, M paths of clock signals and M paths of synchronous signals;

3. The synchronization system of a large-scale acquisition array according to claim 2, wherein a second acquisition data preprocessing module and a second signal processing module are configured inside the acquisition device daughter card;

the M paths of clock signals and the M paths of synchronous signals are sent to a second collected data preprocessing module through a second power distribution module of the collecting equipment daughter card, the second collected data preprocessing module takes the M paths of clock signals and the M paths of synchronous signals as sampling standards of the second collected data preprocessing module, sampling analog signals corresponding to the first sampled data input by the first signal processing module are converted into digital signals, the digital signals are subjected to frequency reduction, sampling reduction and data bit width adjustment processing to obtain second quantized digital signals, the second quantized digital signals are output to a second signal processing module, the second signal processing module respectively stores the obtained multiple paths of second quantized digital signals, processes the multiple paths of second quantized digital signals to further obtain second sampled data corresponding to the second quantized digital signals, and the second signal processing module distributes the sampling analog signals, L paths of clock signals and L paths of synchronous signals corresponding to the second sampled data to the collector;

4. The synchronization system of a large-scale acquisition array according to claim 3, wherein a second synchronization signal detection module, a second synchronization signal alignment judgment module, a second threshold synchronization signal storage module and a second synchronization signal abnormality alarm module are configured inside the acquisition device daughter card; wherein the content of the first and second substances,

5. The synchronization system of the large-scale collection array according to claim 4, wherein a first synchronization signal detection module, a first synchronization signal alignment judgment module, a first threshold synchronization signal storage module and a first synchronization signal abnormality alarm module are configured inside the collection device; wherein the content of the first and second substances,

6. The synchronization system of the large-scale collection array according to claim 5, wherein a first synchronization signal alignment secondary judgment module is further configured inside the collection device;

7. The synchronization system of a large-scale acquisition array according to claim 6, wherein a second synchronization signal alignment secondary judgment module is further configured inside the acquisition device daughter card;

8. The synchronization system for large scale collection array of claim 1, wherein the error threshold range in step S1 is adaptively set as follows: