CN111213244A - 具有厚度沿晶体管宽度变化的半导体层的高电子迁移率晶体管 - Google Patents
具有厚度沿晶体管宽度变化的半导体层的高电子迁移率晶体管 Download PDFInfo
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Abstract
一种高电子迁移率晶体管(HEMT)包括半导体结构，该半导体结构包括形成异质结的覆盖层(101)和沟道层(102)，使得在覆盖层和沟道层的界面处形成二维电子气。HEMT还包括一组电极，该组电极包括沉积在覆盖层上的源极(110)、漏极(120)和栅极(130)。栅极沿着HEMT的长度布置在源极和漏极之间。覆盖层的至少在栅极下方的厚度沿着HEMT的宽度变化。
Description
技术领域
本发明总体涉及用于高频应用的诸如高电子迁移率晶体管的半导体器件。
背景技术
诸如硅(Si)和砷化镓(GaAs)之类的材料已经广泛应用于半导体器件中。然而,更熟悉的，这些半导体材料无法很好地适于更高功率和/或高频应用，这是因为它们的带隙相对小(例如，室温下Si为1.12eV并且GaAs为1.42eV)和/或击穿电压相对小。鉴于Si和GaAs带来的困难，对高功率、高温和/或高频应用和器件的兴趣已转向宽带隙半导体材料，诸如碳化硅(室温下αSiC为2.996eV)和III族氮化物(例如，室温下GaN为3.36eV)。与砷化镓和硅相比，这些材料通常具有更高的电场击穿强度和更高的电子饱和速度。
对高功率和/或高频应用特别感兴趣的器件是高电子迁移率晶体管(HEMT)，在一些情况下，它也被称为调制掺杂场效应晶体管(MODFET)。这些器件在许多情况下可以提供操作优势，这是因为在具有不同带隙能量的两种半导体材料的异质结处形成了二维电子气(2DEG)，并且带隙越小的材料具有越高的电子亲和力。2DEG是未掺杂(“非故意掺杂”)的、带隙更小的材料中的累积层，并且可以包含非常高的薄层电子浓度(例如超过1013cm-2)。另外，起源于较宽带隙半导体的电子转移到2DEG，从而由于减少了电离杂质散射而使得电子迁移率高。
高载流子浓度和高载流子迁移率的这种结合可以增加HEMT的跨导，并且可以针对高频应用提供优于金属半导体场效应晶体管(MESFET)的强大性能优势。
在氮化镓/氮化铝镓(GaN/AlGaN)材料系统中制造的高电子迁移率晶体管由于包括上述高击穿场、宽带隙、大导带偏移和/或高饱和电子漂移速度的材料特性的组合而具有产生大量RF功率的潜力。
RF晶体管的性能指标之一是线性度。具有高线性度的晶体管在使用低噪声放大器(LNA)或功率放大器(PA)时消耗更低的功率。当前，通过采用诸如导数叠加之类的各种线性化技术，在电路级解决了功率放大器中的线性度问题，然而，使用这些技术很昂贵。因此，需要设计一种具有高线性度和高功率密度的晶体管。
发明内容
技术问题
一些实施方式基于以下认识：晶体管的线性度取决于跨导相对于栅极电压的增加。跨导的逐渐增加产生高线性度，而跨导的快速增加导致低线性度。跨导的渐进性由形成晶体管的材料的结构和特性决定，并且难以控制。
例如，可以使用不同的材料来形成晶体管的栅极，但是适合于调制载流子沟道的导电率的金属的特性导致相对低的线性度。附加地或另选地，可以通过减小晶体管的栅极的宽度来增加线性度。然而，这样的减小也降低了载流子密度，这是不希望的。
一些实施方式基于以下认识：诸如二维电子气(2-DEG)密度之类的载流子沟道的密度取决于高电子迁移率晶体管(HEMT)的覆盖层的厚度。如本文中所使用的，覆盖层是与另一半导体层(在本文中称为沟道层)组合形成异质结的顶层。因此，通过改变覆盖层的厚度，2-DEG的密度还可以沿着器件的宽度改变。
具体地，HEMT的阈值电压是覆盖层的厚度和2-DEG密度的函数。因此，覆盖层的厚度变化导致阈值电压变化。例如，覆盖层的阶梯状轮廓创建具有多个虚设沟道的HEMT，每个虚设沟道在源极和漏极之间具有不同的阈值电压。
技术方案
因此，一个实施方式公开了一种高电子迁移率晶体管(HEMT)，该HEMT包括：半导体结构，其包括形成异质结的覆盖层和沟道层，使得在覆盖层和沟道层的界面处形成二维电子气；以及一组电极，其包括沉积在覆盖层上的源极、漏极和栅极，其中，栅极沿着HEMT的长度布置在源极和漏极之间，其中，覆盖层的至少在栅极下方的厚度沿着HEMT的宽度变化。
在一些实现中，覆盖层的在栅极下方的截面具有包括至少两个趋势和至少两个竖直部的阶梯状形状。覆盖层可以在其整个长度上具有相同的轮廓，或者可以在栅极外部具有恒定的覆盖层厚度。
另一实施方式公开了一种用于制造高电子迁移率晶体管(HEMT)的方法。该方法包括提供基板和具有至少一个载流子沟道的半导体结构；蚀刻半导体结构以限定HEMT的有源区；通过金属沉积、剥离、和快速热退火中的一种或组合来形成源极和漏极；通过重复光刻和蚀刻形成具有变化的厚度的覆盖层；以及形成栅极。
附图说明
[图1A]
图1A例示了根据一个实施方式的半导体器件的三维示意图。
[图1B]
图1B示出了根据一些实施方式的高电子迁移率晶体管(HEMT)的顶视图。
[图1C]
图1C示出了根据一个实施方式的沿着HEMT的宽度在沟道的中间的截面图。
[图1D]
图1D示出了根据一些实施方式的HEMT中的虚设沟道的示意图。
[图2A]
图2A示出了例示根据一些实施方式的覆盖层的厚度沿着器件的宽度的改变如何改善半导体器件的线性度的曲线图。
[图2B]
图2B示出了例示根据一些实施方式的覆盖层的厚度沿着器件的宽度的改变如何改善半导体器件的线性度的曲线图。
[图3]
图3示出了根据一些实施方式的具有平坦覆盖层的HEMT的gm对Vgs的曲线和具有可变厚度的覆盖层的HEMT的gm对Vgs的曲线。
[图4]
图4示出了根据一些实施方式的晶体管的gm3对Vgs特性的曲线图。
[图5]
图5示出了根据一个实施方式的HEMT的源极、栅极和漏极的相对布局。
[图6]
图6示出了根据一个实施方式的HEMT的截面图。
[图7]
图7示出了根据另一实施方式的HEMT的截面图。
[图8]
图8示出了根据一个实施方式的范例HEMT的2-D截面图。
[图9]
图9示出了根据本发明的一些实施方式的用于制造半导体器件的方法的框图。
具体实施方式
图1A示出了根据一个实施方式的半导体器件的三维示意图。半导体器件包括覆盖层101，并且在覆盖层下方存在沟道层102，使得在覆盖层和沟道层的界面处形成二维电子气(2-DEG)。为此，图1A的器件是高电子迁移率晶体管(HEMT)。
在一些实现中，为了在有目的的制造过程和封装期间的机械支撑，这些覆盖层和沟道层借助于缓冲层104形成在基板105上。提供源极110和漏极120以承载和放大通过2-DEG沟道层的电信号。为了调节沟道的电导率，在覆盖层的顶部上提供栅极。
在各种实施方式中，覆盖层的至少在栅极下方的厚度沿着HEMT的宽度变化。例如，在一个实施方式中，覆盖层的在栅极下方的截面具有阶梯状形状107，该阶梯状形状具有至少两个趋势和至少两个竖直部。
图1B示出了根据一些实施方式的HEMT的顶视图。如该图所展现的，顶平面具有两个方向：一个方向140沿着器件的长度(即，从源极朝向漏极)，而另一个方向150沿着器件的宽度。厚度的变化(例如，覆盖层中的阶梯轮廓)是沿着器件的宽度方向形成的。
图1C示出了根据一个实施方式的沿着器件的宽度在沟道中间的、示范出栅极下方的覆盖层具有阶梯状形状的截面图。如图1C所示，覆盖层101的形状或轮廓包括多个趋势105和竖直部106。这里，出于示范目的，图中仅示出了9个趋势和8个竖直部。然而，原则上趋势和竖直部的数量越多，器件的线性度性能越好。在这里，不同趋势的宽度可以相同或不同。而且，不同竖直部的高度也可以不同。在该示例中，栅极的形状或栅极的厚度也可以变化，但是对晶体管的性能影响最小。
一些实施方式基于以下认识：诸如二维电子气(2-DEG)密度之类的载流子沟道的密度取决于高电子迁移率晶体管(HEMT)的覆盖层的厚度。如本文中所使用的，覆盖层是与另一半导体层(在本文中称为沟道层)组合形成异质结的顶层。因此，通过改变覆盖层的厚度，2-DEG的密度也可以沿着器件的宽度而改变。
HEMT的阈值电压是覆盖层的厚度和2-DEG密度二者的函数。因此，覆盖层的厚度变化导致阈值电压变化。具体地，阈值电压可以根据下式确定：
其中，VT是HEMT的阈值电压，
是肖特基势垒高度，ΔEC是覆盖层和沟道层之间的导带不连续性，Ns是2-DEG密度，tcap是覆盖层厚度，∈cap是覆盖层厚度的介电常数。因此，通过具有阶梯状覆盖层，我们希望创建具有多个虚设沟道的HEMT，每个虚设沟道在源极和漏极之间具有不同的阈值电压。
图1D示出了根据一些实施方式的在源极与漏极之间的半导体结构中如何形成虚设沟道Ch-1、Ch-2、……、Ch-N的示意图。在此，每个沟道具有其自己的阈值电压，即，Vth1、Vth2、……、VthN。按照使得一个这样的虚设沟道的gm3破坏性地干涉另一虚设沟道的gm3并相互抵消的方式来设计阈值电压。因此，具有N个这样的虚设沟道的复合器件能够对于非常宽范围的栅极电压提供接近于零的gm3。gm3的这种破坏性干涉现象在本文中称为“导数叠加”。
图2A和图2B示出了例示根据一些实施方式的覆盖层的厚度沿着器件的宽度的改变如何改善半导体器件的线性度的曲线图。由表达式
数学定义的gm3是任何晶体管线性度的标志。gm3的幅度越小，线性度越高。
图2A示出了晶体管的gm3对栅极电压的曲线图。在该曲线中要注意的是，任何gm3曲线将具有标记为201的一个正区域(阴影)和标记为202的一个负区域(无阴影)。从正区域到负区域的过渡发生在阈值电压附近。在该图中标记为203的区域是操作的理想区域，这是因为它的gm3值接近零。然而，问题在于该区域沿着Vgs轴的扩展非常小，几乎不可能在如此小的栅极电压范围内操作晶体管。
图2B示出了分别在图1D中示出的两个虚设沟道Ch-1和Ch-2的gm3对Vgs的曲线图210和220。这里，沟道的阈值电压(即，功函数)被设计为使得Ch-1的gm3曲线的负区域与Ch-2的gm3曲线的正区域交叠。因此，如果晶体管仅具有这两个虚设沟道，则它将具有如标记为230的曲线的gm3曲线。需要注意的是，gm3值为零或接近零的栅极电压区域已经增强。gm3的这种破坏性干涉称为“导数叠加”。
图3示出了根据一些实施方式的具有平坦覆盖层的HEMT的gm对Vgs曲线320和具有可变厚度的覆盖层的HEMT的gm对Vgs曲线310。一些实施方式基于以下认识：晶体管的线性度取决于跨导相对于栅极电压的升高。跨导的逐渐增加产生高线性度，而跨导的快速增加导致低线性度。如该图所示，与具有平坦覆盖层的HEMT相比，实施方式的跨导上升缓慢。
图4示出了根据一些实施方式的晶体管的gm3对Vgs特性410以及传统HEMT的gm3对Vgs特性420的曲线图。如前所述，gm3是器件线性度的指标，线性度越高是指gm3越低。理想的线性晶体管应具有非常接近零的gm3。从这个示例中，很明显，根据一些实施方式的晶体管的gm3小于传统HEMT的gm3。
图5示出了根据一个实施方式的HEMT的源极、栅极和漏极的相对布局。源极与栅极之间的距离LSD大于栅极与漏极之间的距离LGD。因为高LSD增加源电阻，这进而降低器件的线性度，所以LSD应该尽可能低。然而，LSD不能非常小，由于其增大寄生电容而导致降低了截止频率。因此，在一些实施方式中，LSD小于500nm。LGD取决于器件的击穿电压。越高的击穿电压需要越高的LGD。LGD还取决于将用于形成沟道的半导体的材料特性，宽带隙材料将在相对低的LGD下给予较高击穿电压。例如，如果器件的击穿电压是VBR，则GaN基器件
任何RF晶体管的击穿电压与最大RF输出功率直接相关，
因此，高击穿电压给予高输出功率。
图6示出了根据一个实施方式的HEMT的截面，其中介电层150夹置在栅极130和阶梯状覆盖层101之间。该氧化物层有助于减小栅极漏电流，从而提高器件的最大截止频率。区域150的材料包括但不限于SiNx、Al2O3、SiO2、HfO2和掺杂HfO2。
图7示出了根据一个实施方式的HEMT的截面，其中半导体层170夹置在栅极130和阶梯状覆盖层101之间。在一些其它实施方式中，层170是p型掺杂的。在这种情况下，半导体层170可以包括但不限于GaN、AlGaN、AlN、金刚石等。这样的布置提供了常关操作。
图8示出了根据一个实施方式的示范HEMT的2-D截面图，其中半导体结构包括在沟道层102和缓冲层103之间的后阻挡层180。后阻挡层的目的是对在沟道层和覆盖层的界面处形成的2-DEG提供量子限制。根据一个实施方式，后阻挡掺杂有p型掺杂剂。
图9示出了根据本发明一些实施方式的用于制造半导体器件的方法的框图。该方法包括在910提供基板，在920制作至少包括III-V沟道层的半导体结构，该III-V沟道层在半导体结构中形成载流子沟道。顶阻挡层的材料具有比III-V沟道层中的材料的带隙更高的带隙。根据一些实施方式，可以采用各种方法来生长和形成顶阻挡层或沟道层，所述方法包括但不限于化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、分子束外延(MBE)、金属有机气相外延(MOVPE)和等离子体增强化学气相沉积(PECVD)和微波等离子体沉积系统。
然后，该方法包括在930通过湿蚀刻或干蚀刻限定晶体管的有源区。
此外，该方法还包括在940使用电子束沉积、焦耳蒸发、化学气相沉积和溅射工艺中的一种或组合来形成电连接到载流子沟道的源极和漏极。然后，将样品在真空或N2环境中以>800℃的温度退火来形成欧姆接触。
然后，该方法包括在950通过在需要沉积栅极的覆盖层中重复光刻和干蚀刻来形成阶梯状。
进一步，该方法还包括在960形成用于栅极的金属板。可以使用光刻→金属沉积→剥离和金属沉积→光刻→蚀刻中的一种或组合，来进行该金属板的形成。这里，可以使用包括但不限于照相光刻、电子束光刻来执行光刻。可以使用电子束沉积、焦耳蒸发、化学气相沉积和溅射工艺中的一种或组合进行金属沉积。
Claims (19)
1.一种高电子迁移率晶体管HEMT，该HEMT包括：
半导体结构，该半导体结构包括形成异质结的覆盖层和沟道层，使得在覆盖层和所述沟道层的界面处形成二维电子气；以及
一组电极，所述一组电极包括沉积在所述覆盖层上的源极、漏极和栅极，其中，所述栅极沿着所述HEMT的长度布置在所述源极和所述漏极之间，其中，所述覆盖层的至少在所述栅极下方的厚度沿着所述HEMT的宽度而变化。
2.根据权利要求1所述的HEMT，其中，所述覆盖层的在所述栅极下方的截面具有包括至少两个趋势和至少两个竖直部的阶梯状形状。
3.根据权利要求1所述的HEMT，其中，所述覆盖层的在所述栅极外部的厚度是恒定的。
4.根据权利要求2所述的HEMT，该HEMT还包括：
介电层，该介电层被布置在所述栅极和所述覆盖层之间。
5.根据权利要求2所述的HEMT，其中，所述趋势具有相同的宽度。
6.根据权利要求2所述的HEMT，其中，所述趋势具有不同的宽度。
7.根据权利要求2所述的HEMT，其中，所述竖直部具有相同的高度。
8.根据权利要求2所述的HEMT，其中，所述竖直部具有不同的高度。
9.根据权利要求1所述的HEMT，其中，所述源极与所述栅极之间的距离大于所述栅极与所述漏极之间的距离。
10.根据权利要求1所述的HEMT，其中，所述沟道层的材料包括氮化镓GaN、氮化铟镓InGaN、砷化镓GaAs和砷化铟镓InGaAs中的一种或组合，并且其中，所述覆盖层的材料包括氮化铝镓AlGaN、氮化铟镓InGaN、氮化铝AlN、砷化铝镓AlGaAs、砷化铝AlAs和砷化铟铝镓InAlGaAs中的一种或组合。
11.根据权利要求1所述的HEMT，其中，半导体层夹置在所述栅极和所述覆盖层之间，并且其中，所夹置的半导体层掺杂有导电性与载流子沟道的导电性相反的杂质。
12.根据权利要求1所述HEMT，其中，所述半导体结构包括位于所述沟道层下方的后阻挡层。
13.根据权利要求12所述的HEMT，其中，所述后阻挡层是p掺杂的。
14.一种用于制造高电子迁移率晶体管HEMT的方法，该方法包括以下步骤：
提供基板和具有至少一个载流子沟道的半导体结构；
蚀刻所述半导体结构以限定所述HEMT的有源区；
通过金属沉积、剥离和快速热退火中的一种或组合来形成源极和漏极；
通过重复光刻和蚀刻来形成具有变化的厚度的覆盖层；以及
形成栅极。
15.根据权利要求1所述的HEMT，其中，所述覆盖层的在所述栅极下方的截面具有包括至少两个趋势和至少两个竖直部的阶梯状形状。
16.根据权利要求14所述的方法，其中，使用电子束物理气相沉积EBPVD、焦耳蒸发、化学气相沉积和溅射工艺中的一种或组合来形成所述电极。
17.根据权利要求14所述的方法，其中，使用化学气相沉积CVD、金属有机化学气相沉积MOCVD、分子束外延MBE、金属有机气相外延MOVPE、等离子体增强化学气相沉积PECVD和微波等离子体沉积中的一种或组合，来制作所述半导体结构的层。
18.根据权利要求14所述的方法，该方法还包括以下步骤：
在所述沟道层下方形成后阻挡层。
19.根据权利要求14所述的方法，该方法还包括以下步骤：
使用原子层沉积ALD、化学气相沉积CVD、金属有机化学气相沉积MOCVD、分子束外延MBE、金属有机气相外延MOVPE、等离子体增强化学气相沉积PECVD和微波等离子体沉积中的一种或组合，在所述栅极下方形成介电层。
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| CN112736129A (zh) * | 2020-12-31 | 2021-04-30 | 厦门市三安集成电路有限公司 | 一种氮化物hemt射频器件及其制作方法 |
| CN112736127A (zh) * | 2020-12-31 | 2021-04-30 | 厦门市三安集成电路有限公司 | 一种氮化镓基hemt射频器件及其制作方法 |
| CN113555430A (zh) * | 2021-07-07 | 2021-10-26 | 西安电子科技大学 | 一种通过渐变栅实现多阈值调制技术的hemt器件及制备方法 |
| WO2024082655A1 (zh) * | 2022-10-18 | 2024-04-25 | 中兴通讯股份有限公司 | 高电子迁移率晶体管器件及其制造方法 |
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| US20210399121A1 (en) * | 2020-06-18 | 2021-12-23 | The Regents Of The University Of California | Novel approach to controlling linearity in n-polar gan mishemts |
| US20230420541A1 (en) * | 2020-11-16 | 2023-12-28 | National Research Council Of Canada | Multi-threshold voltage galium nitride high electron mobility transistor |
| CN113113483B (zh) * | 2021-03-15 | 2022-10-21 | 厦门市三安集成电路有限公司 | 一种hemt射频器件及其制作方法 |
| CN113113313A (zh) * | 2021-03-15 | 2021-07-13 | 厦门市三安集成电路有限公司 | 一种hemt器件及其制作方法 |
| KR102547803B1 (ko) * | 2021-05-18 | 2023-06-26 | 삼성전자주식회사 | 고 전자 이동도 트랜지스터 |
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| US10418474B2 (en) | 2019-09-17 |
| JP6956814B2 (ja) | 2021-11-02 |
| EP3491671A1 (en) | 2019-06-05 |
| WO2019077784A1 (en) | 2019-04-25 |
| JP2020524417A (ja) | 2020-08-13 |
| US20190115462A1 (en) | 2019-04-18 |
| EP3491671B1 (en) | 2020-08-19 |
| CN111213244B (zh) | 2024-03-08 |
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