CN111192923A - 包括源极/漏极区的半导体器件 - Google Patents

包括源极/漏极区的半导体器件 Download PDF

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CN111192923A
CN111192923A CN201910489544.1A CN201910489544A CN111192923A CN 111192923 A CN111192923 A CN 111192923A CN 201910489544 A CN201910489544 A CN 201910489544A CN 111192923 A CN111192923 A CN 111192923A
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source
active region
drain regions
layer
pair
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张星旭
李承勳
郑秀珍
曺荣大
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供了一种半导体器件，该半导体器件包括：有源区，限定在基底中；至少一个沟道层，在有源区上；栅电极，与有源区交叉，在有源区上，并围绕所述至少一个沟道层；以及成对的源极/漏极区，与栅电极的两侧相邻，在有源区上，并与所述至少一个沟道层接触，其中，成对的源极/漏极区包括选择性外延生长(SEG)层，以及成对的源极/漏极区中的每个在第一方向上的最大宽度是有源区在第一方向上的宽度的1.3倍或者更小。

Description

包括源极/漏极区的半导体器件
于2018年11月14日在韩国知识产权局(KIPO)提交并且名称为“包括源极/漏极区的半导体器件”的第10-2018-0139521号韩国专利申请通过引用全部包含于此。
技术领域
实施例涉及一种具有源极/漏极区的半导体器件。
背景技术
使用选择性外延生长(SEG,selective epitaxial growth)形成源极/漏极区的技术可以有助于提高晶体管的特性。
发明内容
可以通过提供一种半导体器件而实现实施例，该半导体器件包括：有源区，限定在基底中；至少一个沟道层，在有源区上；栅电极，与有源区交叉，在有源区上，并围绕所述至少一个沟道层；以及成对的源极/漏极区，与栅电极的两侧相邻，在有源区上，并与所述至少一个沟道层接触，其中，成对的源极/漏极区包括选择性外延生长(SEG)层，以及成对的源极/漏极区中的每个在第一方向上的最大宽度是有源区在第一方向上的宽度的1.3倍或者更小。
可以通过提供一种半导体器件而实现实施例，该半导体器件包括：有源区，限定在基底中；至少一个沟道层，在有源区上并具有P型杂质；栅电极，在有源区上与有源区交叉并围绕所述至少一个沟道层；以及成对的源极/漏极区，与栅电极的两侧相邻，在有源区上，并与所述至少一个沟道层接触，其中，成对的源极/漏极区包括具有N型杂质的选择性外延生长(SEG)层，以及成对的源极/漏极区中的每个在第一方向上的最大宽度是有源区在第一方向上的宽度的1.3倍或者更小。
可以通过提供一种半导体器件而实现实施例，该半导体器件包括：第一有源区和第二有源区，限定在基底中并且彼此分隔开；以及第一源极/漏极区和第二源极/漏极区，在第一有源区和第二有源区上并且彼此分隔开，其中，第一源极/漏极区和第二源极/漏极区包括选择性外延生长(SEG)层，以及第一源极/漏极区和第二源极/漏极区中的每个在第一方向上的最大宽度是第一有源区和第二有源区中对应的一个在第一方向上的宽度的1.3倍或者更小。
附图说明
通过参照附图详细描述示例性实施例，特征对于本领域技术人员将是明显的，其中：
图1示出了根据实施例的半导体器件的剖视图。
图2示出了根据实施例的半导体器件的布局图。
图3至图6示出了根据实施例的半导体器件的剖视图。
图7至图20示出了根据实施例的形成半导体器件的方法中的阶段的剖视图。
图21至图23示出了根据实施例的半导体器件的剖视图。
具体实施方式
图1示出了根据实施例的半导体器件的剖视图。图2示出了根据实施例的半导体器件的布局图。图1包括沿图2的线I-I'、线II-II'和线III-III'截取的剖视图。在实施方式中，半导体器件可以包括多桥沟道(MBC，multi-bridge channel)晶体管、纳米片晶体管或者栅极环绕式(GAA，gate-all-around)晶体管。
参照图1，根据实施例的半导体器件可以包括：基底21、有源区23、至少一个沟道层27、器件隔离层29、侧壁分隔件(spacer)38、多个内部分隔件43、成对的源极/漏极区45、层间绝缘层47、栅极介电层51、栅电极53和栅极覆盖图案55。所述至少一个沟道层27可以包括多个沟道层27。
参照图2，可以彼此平行地提供多个有源区23。可以彼此平行地提供多个栅电极53。多个栅电极53中的每个可与多个有源区23交叉。
再次参照图1和图2，器件隔离层29可以在基底21中。有源区23在基底21中可以通过器件隔离层29来限定。器件隔离层29的顶表面可以在低于有源区23的上端的水平上凹陷。多个沟道层27可以在垂直方向(例如，远离基底21)上依次堆叠在有源区23上。多个沟道层27可以与有源区23分隔开。多个沟道层27可以彼此分隔开。
栅电极53可以在有源区23上与有源区23交叉并且可围绕多个沟道层27。栅电极53可以在有源区23和多个沟道层27之间以及多个沟道层27之间，并且可以在多个沟道层27上与多个沟道层27交叉。栅电极53可以在器件隔离层29上延伸。栅电极53的底表面可以在低于有源区23的上端的水平上。栅电极53可以部分地覆盖有源区23的侧表面。在实施方式中，栅电极53的至少一部分可以在多个沟道层27的沟道层27之间或者有源区23和多个沟道层27之间。
栅极介电层51可以在栅电极53和多个沟道层27之间以及栅电极53和有源区23之间，并且可以在栅电极53和器件隔离层29之间延伸。栅极介电层51可以在栅电极53和多个内部分隔件43之间。栅极介电层51可以在侧壁分隔件38和栅电极53之间以及侧壁分隔件38和栅极覆盖图案55之间延伸。
成对的源极/漏极区45可以在有源区23上与栅电极53相邻或者在栅电极53的侧面(例如，两侧)。成对的源极/漏极区45可以与有源区23和多个沟道层27直接接触。成对的源极/漏极区45可以包括选择性外延生长(SEG)层。成对的源极/漏极区45可以包括例如磷化硅(SiP)、碳化硅(SiC)、硅(Si)或硅锗(SiGe)。成对的源极/漏极区45中的每个可以具有大于其横向宽度的垂直高度(例如，在远离基底21延伸的方向上)。成对的源极/漏极区45的上端可以在高于至少一个沟道层27的上端的水平上。例如，成对的源极/漏极区45的上端可以在高于多个沟道层27中最上沟道层27的上端的水平上。
成对的源极/漏极区45中的每个的横向宽度可以大于(例如，或者等于)有源区23的横向宽度。有源区23可以具有第一(例如，横向)宽度W1(在第一方向上)。成对的源极/漏极区45中的每个的最大宽度可以是第二(例如，横向)宽度W2(在第一方向上)。第二宽度W2可以是第一宽度W1的1.3倍或者更小(例如，但仍然大于或者等于第一宽度W1)。在实施方式中，第二宽度W2可以是第一宽度W1的1至1.3倍。成对的源极/漏极区45可以具有盒形形状、圆形形状或者圈形形状。当第二宽度W2大于或者等于第一宽度W1时，成对的源极/漏极区45和多个沟道层27之间的电阻可以减小。当第二宽度W2大于或者等于第一宽度W1时，可以提高半导体器件的电特性和可靠性。当第二宽度W2是第一宽度W1的1.3倍或者更小时，可以减小成对的源极/漏极区45的漏电流。当第二宽度W2是第一宽度W1的1.3倍或者更小时，可以提高半导体器件的集成密度。当第二宽度W2是第一宽度W1的1至1.3倍时，可以有助于最小化漏电流的半导体器件对增大集成密度可以是有利的，并且可以具有优异的电特性。
多个内部分隔件43可以在栅电极53和成对的源极/漏极区45之间。多个内部分隔件43可以在多个沟道层27的沟道层27之间。多个内部分隔件43可以在多个沟道层27的最下沟道层27和有源区23之间。
层间绝缘层47可以在器件隔离层29上以覆盖成对的源极/漏极区45。层间绝缘层47可以覆盖成对的源极/漏极区45的侧表面。栅极覆盖图案55可以覆盖栅电极53。
侧壁分隔件38可以在层间绝缘层47和栅电极53之间，以及层间绝缘层47和栅极覆盖图案55之间。侧壁分隔件38可以在多个沟道层27上。侧壁分隔件38可以与多个沟道层27的最上沟道层27的顶表面直接接触。侧壁分隔件38可以部分地保留在有源区23的侧表面上。层间绝缘层47、侧壁分隔件38和栅极覆盖图案55的上端可以基本上彼此共面。
在实施方式中，有源区23和多个沟道层27可以包括P型杂质。成对的源极/漏极区45可以包括N型杂质。成对的源极/漏极区45可以包括具有硅(Si)和磷(P)的SEG层。
在实施方式中，有源区23和多个沟道层27可以包括N型杂质。成对的源极/漏极区45可以包括P型杂质。成对的源极/漏极区45可以包括具有硅(Si)、锗(Ge)和硼(B)的SEG层。
图3至图6示出了根据实施例的半导体器件的剖视图。图3至图5示出了沿图2的线I-I'、线II-II'和线III-III'截取的剖视图。
参照图3，多个内部分隔件43可以抑制SEG层的过度横向生长。成对的源极/漏极区45的形状可以取决于多个内部分隔件43中的每个的高度和多个沟道层27中的每个的厚度。通过控制有源区23、多个沟道层27和多个内部分隔件43的尺寸以及有源区23、多个沟道层27和多个内部分隔件43之间的距离，成对的源极/漏极区45可以获得期望的尺寸和形状。成对的源极/漏极区45的侧表面可以具有多个粗糙或不平坦的部分。与成对的源极/漏极区45的与多个内部分隔件43相邻的部分相比或者相对于成对的源极/漏极区45的与多个内部分隔件43相邻的部分，成对的源极/漏极区45的与多个沟道层27相邻的部分可以在横向方向上突出。例如，在剖视图中，成对的源极/漏极区45可以具有波纹状边缘，其中成对的源极/漏极区45的突出部与多个沟道层27对齐(例如，相对于多个沟道层27处于同一高度)并且成对的源极/漏极区45的凹进部与多个内部分隔件43对齐。
参照图4，多个沟道层27的上角部和下角部可以被倒圆。有源区23的上角部可以被倒圆。多个源极/漏极区45中的每一个可以具有圈形形状。
参照图5，在向上的方向上(例如，在远离基底21的方向上)，多个沟道层27中的沟道层27的宽度可以变小。在向下的方向上，有源区23的宽度可以变大(例如，增大)。
参照图6，器件隔离层29可以在基底21中，并且可以限定彼此分隔开的第一有源区23A和第二有源区23B。器件隔离层29可以在基底21中位于第一有源区23A和第二有源区23B之间以及第一有源区23A和第二有源区23B外侧。第一有源区23A和第二有源区23B可以彼此平行。第一源极/漏极区45A和第二源极/漏极区45B可以在第一有源区23A和第二有源区23B上并且彼此分隔开。第一源极/漏极区45A和第二源极/漏极区45B可以包括SEG层。第一源极/漏极区45A和第二源极/漏极区45B中的每个的最大宽度可以是第一有源区23A和第二有源区23B中对应的(例如，作为基础的)一个的宽度的1.3倍或者更小。在实施方式中，第一源极/漏极区45A和第二源极/漏极区45B中的每个的最大宽度可以是第一有源区23A和第二有源区23B中对应的一个的宽度的1至1.3倍。第一源极/漏极区45A和第二源极/漏极区45B中的每个可以具有盒形形状或者圈形形状。在实施方式中，第一源极/漏极区45A和第二源极/漏极区45B可以包括SiP。层间绝缘层47可以在器件隔离层29上以覆盖第一源极/漏极区45A和第二源极/漏极区45B。
层间绝缘层47可以在第一源极/漏极区45A和第二源极/漏极区45B之间以及第一源极/漏极区45A和第二源极/漏极区45B外侧。第一源极/漏极区45A可以与第二源极/漏极区45B电绝缘。第一源极/漏极区45A和第二源极/漏极区45B之间的漏电流可以被最小化。
图7至图19示出了根据实施例的形成半导体器件的方法中的阶段的剖视图。
参照图7，可在基底21上交替地且重复性地形成多个牺牲层25和多个沟道层27。
基底21可以是半导体基底，例如，硅晶圆或者绝缘体上硅(SOI，silicon-on-insulator)晶圆。基底21可以包括具有P型杂质的P阱、具有N型杂质的N阱或者它们的组合，然而为了简洁起见，将省略其说明。P型杂质可以包括硼(B)，并且N型杂质可以包括磷(P)、砷(As)或者它们的组合。在实施方式中，基底21可以是具有P型杂质的单晶晶圆。
多个牺牲层25可以包括相对于多个沟道层27和基底21具有蚀刻选择性的材料。在实施方式中，多个牺牲层25中的每个可以包括利用SEG工艺形成的SiGe层，并且多个沟道层27中的每个可以包括利用SEG工艺形成的Si层。多个沟道层27中的每个可以包括P型杂质或者N型杂质。在实施方式中，多个沟道层27中的每个可以包括P型杂质。
参照图8，可以在多个沟道层27的最上沟道层上形成第一掩模图案33。第一掩模图案33可以包括第一缓冲层31和第一掩模层32。可以使用第一掩模图案33作为蚀刻掩模来部分地去除多个沟道层27、多个牺牲层25和基底21，从而形成多个沟槽28T。
可在基底21中在多个沟槽28T之间限定有源区23。多个牺牲层25和多个沟道层27可以在多个沟槽28T之间保留在有源区23上。
第一缓冲层31可以形成在多个沟道层27的最上沟道层和第一掩模层32之间。第一缓冲层31可以与多个沟道层27的最上沟道层直接接触。第一掩模层32可以形成在第一缓冲层31上。在实施方式中，第一缓冲层31可以包括氧化硅，并且第一掩模层32可以包括氮化硅。
多个沟槽28T的形成可以包括各向异性蚀刻工艺。多个沟槽28T的底部可以形成在低于基底21的顶表面的水平上。有源区23、多个牺牲层25和多个沟道层27的侧表面可以暴露在多个沟槽28T的侧壁。
参照图9，可以在多个沟槽28T的内部形成器件隔离层29。器件隔离层29可以包括诸如氧化硅、氮化硅、氮氧化硅或者它们的组合的绝缘材料。
参照图10，可以部分地蚀刻器件隔离层29，并可去除第一掩模图案33，以将多个牺牲层25和多个沟道层27暴露。也可以部分地暴露有源区23的侧表面。器件隔离层29的顶表面可以形成在低于有源区23的顶表面的水平上。
参照图11，可以形成第二缓冲层35、临时栅电极36、第二掩模图案37和侧壁分隔件38。
第二缓冲层35和临时栅电极36的形成可以包括多个薄膜形成工艺和多个图案化工艺。第二缓冲层35可以包括诸如氧化硅的氧化物。临时栅电极36可以包括多晶硅。临时栅电极36可以与多个牺牲层25和多个沟道层27交叉并且在器件隔离层29上延伸。临时栅电极36可以部分地覆盖多个沟道层27的顶表面和侧表面，部分地覆盖多个牺牲层25的侧表面，部分地覆盖有源区23的侧表面，并部分地覆盖器件隔离层29。第二缓冲层35可以形成在临时栅电极36和多个沟道层27之间，临时栅电极36和多个牺牲层25之间，临时栅电极36和有源区23之间，以及临时栅电极36和器件隔离层29之间。第二掩模图案37可以形成在临时栅电极36上。第二掩模图案37可以包括诸如氮化硅的氮化物。
侧壁分隔件38的形成可以包括薄膜形成工艺和各向异性蚀刻工艺。侧壁分隔件38可以包括诸如氮化硅的氮化物。侧壁分隔件38可以覆盖第二缓冲层35的侧表面和临时栅电极36的侧表面并且在第二掩模图案37的侧表面上延伸。侧壁分隔件38可以部分地覆盖有源区23的侧表面。
参照图12，可以使用第二掩模图案37和侧壁分隔件38作为蚀刻掩模来部分地去除多个沟道层27、多个牺牲层25和有源区23以形成凹陷区40R。凹陷区40R的底部可以在低于有源区23的上端的水平上。多个沟道层27的侧表面和多个牺牲层25的侧表面可以在凹陷区40R的内侧暴露。有源区23可以在凹陷区40R的底部暴露。
参照图13，可部分地蚀刻多个牺牲层25以形成多个侧凹(undercut)区25uc。多个侧凹区25uc的形成可以包括各向同性蚀刻工艺。
参照图14，可在多个侧凹区25uc中形成多个内部分隔件43。多个内部分隔件43的形成可以包括薄膜形成工艺和各向异性蚀刻工艺。多个内部分隔件43可以包括诸如氮化硅的氮化物。有源区23可以具有第一宽度W1。
参照图15，可在有源区23上形成成对的源极/漏极区45。成对的源极/漏极区45可以包括利用SEG工艺形成的SEG层。成对的源极/漏极区45可以包括与多个沟道层27不同的导电类型的杂质。成对的源极/漏极区45可以包括P型杂质或者N型杂质。成对的源极/漏极区45可以包括SiP、SiC、Si或者SiGe。
成对的源极/漏极区45中的每个可以形成为具有与参照图1至图6所描述的形状相似的各种形状。成对的源极/漏极区45中的每个可以具有盒形形状或者圈形形状。在实施方式中，在利用SEG工艺形成成对的源极/漏极区45的工艺过程中，在有源区23和多个沟道层27的表面上可以相对地促进SEG层的形成，而在多个内部分隔件43的表面上可以相对地抑制SEG层的形成。
在成对的源极/漏极区45的形成过程中，多个内部分隔件43可以抑制SEG层的过度横向生长。成对的源极/漏极区45的形状可以取决于多个内部分隔件43中的每个的高度和多个沟道层27中的每个的厚度。通过控制有源区23、多个沟道层27和多个内部分隔件43的尺寸以及有源区23、多个沟道层27和多个内部分隔件43之间的距离，成对的源极/漏极区45可以获得期望的尺寸和形状。成对的源极/漏极区45中的每个可以具有第二宽度W2。第二宽度W2可以是第一宽度W1的1.3倍或者更小。在实施例中，第二宽度W2可以大于第一宽度W1。第二宽度W2可以是第一宽度W1的1至1.3倍。
在实施方式中，多个内部分隔件43中的每个的高度可以是多个沟道层27中相邻的一个的厚度的0.8倍或者更大。在实施方式中，多个内部分隔件43中的每个的高度可以是多个沟道层27中相邻的一个的厚度的0.8至5倍。在实施方式中，多个内部分隔件43中的每个的高度可以与多个沟道层27中相邻的一个的厚度大约相等。
在实施方式中，有源区23和多个沟道层27可以包括P型杂质。成对的源极/漏极区45可以包括SiP层、包含N型杂质的SiC层或者包含N型杂质的Si层。例如，成对的源极/漏极区45中的每个可以包括利用SEG工艺形成的SiP层。
在实施方式中，有源区23和多个沟道层27可以包括N型杂质。成对的源极/漏极区45可以包括包含P型杂质的SiGe层或者包含P型杂质的Si层。例如，成对的源极/漏极区45中的每个可以包括利用SEG工艺形成的掺杂硼(B)的SiGe层。
根据实施例，可以抑制成对的源极/漏极区45的过度横向生长，并且成对的源极/漏极区45可以获得期望的形状。由于成对的源极/漏极区45的期望形状，所以可以将漏电流最小化，并且可以实现有利于增大集成密度并且具有优异的操作特性的半导体器件。
参照图16，可以形成层间绝缘层47以覆盖成对的源极/漏极区45、第二掩模图案37和侧壁分隔件38。层间绝缘层47可以包括氧化硅、氮化硅、氮氧化硅、碳氮氧化硅(SiOCN)、低k介电材料、高k介电材料或者它们的组合。层间绝缘层47可以包括复层，所述复层包括多个不同的层。
参照图17，可以部分地去除层间绝缘层47，并可以去除第二掩模图案37以暴露临时栅电极36。暴露临时栅电极36的工艺可以包括平坦化工艺。平坦化工艺可以包括化学机械抛光(CMP)工艺、回蚀工艺或者它们的组合。层间绝缘层47、侧壁分隔件38和临时栅电极36的顶表面可以被暴露并且基本上彼此共面。
参照图18，可以去除临时栅电极36以形成栅极沟槽36T。栅极沟槽36T的形成可以包括各向同性蚀刻工艺。
参照图19，可以去除第二缓冲层35，并且可以去除多个牺牲层25以形成多个间隙区25G。
再次参照图1，可以形成栅极介电层51、栅电极53和栅极覆盖图案55。栅极介电层51、栅电极53和栅极覆盖图案55的形成可以包括多个薄膜形成工艺和多个平坦化工艺。
栅电极53可以形成在栅极沟槽36T和多个间隙区25G内部。栅电极53可以在有源区23和多个沟道层27上与有源区23和多个沟道层27交叉。成对的源极/漏极区45可以保留为与栅电极53的两侧相邻。
栅电极53可以包括金属、金属氮化物、金属氧化物、金属硅化物、导电碳、多晶硅或者它们的组合。栅电极53可以包括钨(W)、氮化钨(WN)、钛(Ti)、氮化钛(TiN)、氮化钛硅(TiSiN)、钽(Ta)、氮化钽(TaN)、氮化钽硅(TaSiN)、锆(Zr)、氮化锆(ZrN)、铝(Al)、氮化铝(AlN)、钌(Ru)、氮化钌(RuN)、钼(Mo)、氮化钼(MoN)、氮化钼硅(MoSiN)、钴(Co)、氮化钴(CoN)、氮化钴硅(CoSiN)、镍(Ni)、硅(Si)或者它们的组合。栅电极53可以包括NMOS功函数金属或者PMOS功函数金属。栅电极53可以被称作替代金属栅极(RMG，replacement metalgate)。
栅极介电层51可以形成在栅电极53和有源区23之间以及栅电极53和多个沟道层27之间。栅极介电层51可以在栅电极53和侧壁分隔件38之间以及栅电极53和器件隔离层29之间延伸。在有源区23和多个沟道层27的表面上还可以形成界面介电层(例如，利用清洗工艺形成的氧化硅层)。栅极介电层51可以包括高k介电材料、氧化硅、氮化硅、氮氧化硅或者它们的组合。例如，栅极介电层51可以包括氧化铪(HfO)、氧化铪硅(HfSiO)、氧化铝(AlO)或者它们的组合。
多个沟道层27中的每个可以被栅电极53围绕。栅极介电层51可以在多个沟道层27和栅电极53之间。多个沟道层27中的每个可以被栅极介电层51围绕。
栅极覆盖图案55可以覆盖栅电极53。层间绝缘层47、侧壁分隔件38和栅极覆盖图案55的顶表面可以被暴露并且基本上彼此共面。栅极覆盖图案55可以包括诸如氮化硅的氮化物。
图20示出了根据实施例的形成半导体器件的方法中的阶段的剖视图。
参照图20，在利用SEG工艺形成成对的源极/漏极区45的工艺过程中，在有源区23和多个沟道层27的表面上可以相对地促进SEG层的形成，而在多个内部分隔件43的表面上可以相对地抑制SEG层的形成。在成对的源极/漏极区45的形成过程中，多个内部分隔件43可以抑制SEG层的过度横向生长。成对的源极/漏极区45的形状可以取决于多个内部分隔件43中的每个的高度和多个沟道层27中的每个的厚度。
通过控制有源区23、多个沟道层27和多个内部分隔件43的尺寸以及有源区23、多个沟道层27和多个内部分隔件43之间的距离，成对的源极/漏极区45可以获得期望的尺寸和形状。在实施方式中，多个内部分隔件43中的每个的高度可以是多个沟道层27中相邻的一个的厚度的0.8至5倍。成对的源极/漏极区45的侧表面可以包括多个粗糙部分。与成对的源极/漏极区45的与多个内部分隔件43相邻的部分相比，成对的源极/漏极区45的与多个沟道层27相邻的部分可以在横向方向上突出。
图21至图23示出根据实施例的半导体器件的剖视图。
参照图21，成对的源极/漏极区45中的每个可以包括第一SEG层L1、第二SEG层L2和第三SEG层L3。第一SEG层L1可以形成在有源区23上并且与至少一个沟道层27直接接触。第一SEG层L1可以包括第一重量百分比(wt％)的N型杂质或者第二重量百分比的P型杂质。第一SEG层L1可以包括与至少一个沟道层27和有源区23不同的导电类型的杂质。第二SEG层L2可以在第一SEG层L1上。第二SEG层L2可以包括第三重量百分比的N型杂质或者第四重量百分比的P型杂质。在实施方式中，第三重量百分比可以高于第一重量百分比，并且第四重量百分比可以高于第二重量百分比。第二SEG层L2可以包括与第一SEG层L1相同的导电类型的杂质。
第三SEG层L3可以在第二SEG层L2上。第三SEG层L3可以包括第五重量百分比的N型杂质或者第六重量百分比的P型杂质。第五重量百分比可以高于第三重量百分比，并且第六重量百分比可以高于第四重量百分比。在实施方式中，第五重量百分比可以低于第三重量百分比，并且第六重量百分比可以低于第四重量百分比。
参照图22，上绝缘层77可以在层间绝缘层47上以覆盖第一源极/漏极区45A和第二源极/漏极区45B。第一接触塞88A和第二接触塞88B可以穿过上绝缘层77和层间绝缘层47并且可以分别连接到第一源极/漏极区45A和第二源极/漏极区45B。接触分隔件81可以围绕第一接触塞88A和第二接触塞88B的侧表面。第一金属硅化物层83A和第二金属硅化物层83B可以在第一接触塞88A和第一源极/漏极区45A之间以及第二接触塞88B和第二源极/漏极区45B之间。第一接触塞88A和第二接触塞88B中的每个可以包括阻挡金属层84和塞导电层85。
上绝缘层77可以包括氧化硅、氮化硅、氮氧化硅、碳氮氧化硅(SiOCN)、低k介电材料、高k介电材料或者它们的组合。上绝缘层77可以是包括多个不同层的复层。接触分隔件81可以包括诸如氮化硅的氮化物。阻挡金属层84可以围绕塞导电层85的侧表面和底表面。阻挡金属层84可以包括Ti、TiN、Ta、TaN或者它们的组合。塞导电层85可以包括金属、金属氮化物、金属氧化物、金属硅化物、导电碳、多晶硅或者它们的组合。
参照图23，接触塞88可以穿过上绝缘层77和层间绝缘层47，并且可以连接到第一源极/漏极区45A和第二源极/漏极区45B。接触塞88可以包括阻挡金属层84和塞导电层85。接触分隔件81可以围绕接触塞88的侧表面。第一金属硅化物层83A和第二金属硅化物层83B可以在接触塞88与第一源极/漏极区45A和第二源极/漏极区45B之间。
通过总结和回顾，SEG层的横向生长会导致相邻的源极/漏极区之间的漏电流增加。
一个或者更多实施例可以提供一种用于提高晶体管的电特性，同时将漏电流最小化的新技术。
根据示例性实施例，可以在有源区上与栅电极的两侧相邻地提供成对的源极/漏极区。成对的源极/漏极区可以与至少一个沟道层接触。成对的源极/漏极区中的每个的最大宽度可以是有源区的宽度的1.3倍或者更小。成对的源极/漏极区中的每个的形状可以包括盒形形状或者圈形形状。可以实现可将漏电流最小化、可以有利于提高集成密度并且可以具有优异的操作特性的半导体器件。
一个或者更多实施例可以提供可以有助于将漏电流最小化并且可以具有优异的操作特性的半导体器件和形成该半导体器件的方法。
这里已经公开了示例性实施例，并且虽然采用了特定术语，但它们仅以一般性和描述性意义使用和解释，而不是为了限制的目的。在某些情况下，如截止到本申请提交之时的本领域普通技术人员将清楚的，结合具体实施例描述的特征、特性和/或元件可以单独使用，或者可与结合其他实施例描述的特征、特性和/或元件组合起来使用，除非另外特别说明。因此，本领域技术人员将理解的是，在不脱离本发明的由权利要求书阐述的精神和范围的情况下，可以做出形式上和细节上的各种改变。

Claims (20)

1.一种半导体器件，包括：
有源区，限定在基底中；
至少一个沟道层，在所述有源区上；
栅电极，与所述有源区交叉，在所述有源区上，并围绕所述至少一个沟道层；以及
成对的源极/漏极区，与所述栅电极的两侧相邻，在所述有源区上，并与所述至少一个沟道层接触，
其中：
所述成对的源极/漏极区包括选择性外延生长层，以及
所述成对的源极/漏极区中的每个在第一方向上的最大宽度是所述有源区在所述第一方向上的宽度的1.3倍或者更小。
2.如权利要求1所述的半导体器件，其中，所述成对的源极/漏极区中的每个具有盒形形状、圆形形状或者圈形形状。
3.如权利要求1所述的半导体器件，其中，所述成对的源极/漏极区包括磷化硅、碳化硅、硅或者硅锗。
4.如权利要求1所述的半导体器件，其中，所述成对的源极/漏极区的上端比所述至少一个沟道层的上端离所述基底更远。
5.如权利要求1所述的半导体器件，其中：
所述至少一个沟道层包括多个沟道层，并且
所述栅电极的至少一部分在多个所述沟道层中的沟道层之间或者所述有源区和所述多个沟道层之间。
6.如权利要求5所述的半导体器件，其中，所述多个沟道层中的所述沟道层彼此分隔开并且在垂直方向上依次堆叠在所述有源区上。
7.如权利要求5所述的半导体器件，所述半导体器件还包括所述栅电极和所述成对的源极/漏极区之间的多个内部分隔件，
其中，所述多个内部分隔件在所述多个沟道层中的所述沟道层之间以及所述多个沟道层中的最下沟道层和所述有源区之间。
8.如权利要求7所述的半导体器件，其中，所述多个内部分隔件包括氮化硅。
9.如权利要求7所述的半导体器件，其中：
所述成对的源极/漏极区的侧表面包括多个不平坦部分，以及
相对于所述成对的源极/漏极区的与所述所述多个内部分隔件相邻的部分，所述成对的源极/漏极区的与所述多个沟道层相邻的部分在横向方向上突出。
10.如权利要求1所述的半导体器件，所述半导体器件还包括：
器件隔离层，在所述基底中并限定所述有源区；
层间绝缘层，在所述器件隔离层上并覆盖所述成对的源极/漏极区；以及
侧壁分隔件，在所述层间绝缘层和所述栅电极之间并在所述至少一个沟道层上。
11.如权利要求10所述的半导体器件，所述半导体器件还包括栅极介电层，所述栅极介电层在所述栅电极和所述至少一个沟道层之间以及所述栅电极和所述有源区之间。
12.如权利要求11所述的半导体器件，其中，所述栅极介电层在所述侧壁分隔件和所述栅电极之间延伸。
13.如权利要求1所述的半导体器件，其中，所述成对的源极/漏极区中的每个包括：
第一选择性外延生长层，与所述至少一个沟道层接触并具有第一重量百分比的N型杂质或者第二重量百分比的P型杂质；
第二选择性外延生长层，在所述第一选择性外延生长层上，并具有第三重量百分比的N型杂质或者第四重量百分比的P型杂质，所述第三重量百分比高于所述第一重量百分比，并且所述第四重量百分比高于所述第二重量百分比；以及
第三选择性外延生长层，在所述第二选择性外延生长层上。
14.如权利要求1所述的半导体器件，所述半导体器件还包括：
上绝缘层，在所述成对的源极/漏极区上；以及
接触塞，贯穿所述上绝缘层而连接到所述成对的源极/漏极区中被选择的一个。
15.一种半导体器件，包括：
有源区，限定在基底中；
至少一个沟道层，在所述有源区上并具有P型杂质；
栅电极，在所述有源区上与所述有源区交叉并围绕所述至少一个沟道层；以及
成对的源极/漏极区，与所述栅电极的两侧相邻，在所述有源区上，并与所述至少一个沟道层接触，
其中：
所述成对的源极/漏极区包括具有N型杂质的选择性外延生长层，以及
所述成对的源极/漏极区中的每个在第一方向上的最大宽度是所述有源区在所述第一方向上的宽度的1.3倍或者更小。
16.如权利要求15所述的半导体器件，其中，所述成对的源极/漏极区包括硅和磷。
17.一种半导体器件，包括：
第一有源区和第二有源区，限定在基底中并且彼此分隔开；以及
第一源极/漏极区和第二源极/漏极区，在所述第一有源区和所述第二有源区上并且彼此分隔开，
其中：
所述第一源极/漏极区和所述第二源极/漏极区包括选择性外延生长层，以及
所述第一源极/漏极区和所述第二源极/漏极区中的每个在第一方向上的最大宽度是所述第一有源区和所述第二有源区中对应的一个在所述第一方向上的宽度的1.3倍或者更小。
18.如权利要求17所述的半导体器件，其中，所述第一有源区与所述第二有源区平行。
19.如权利要求17所述的半导体器件，所述半导体器件还包括在所述基底中并在所述第一有源区和所述第二有源区之间的器件隔离层。
20.如权利要求19所述的半导体器件，所述半导体器件还包括在所述器件隔离层上并在所述第一源极/漏极区和第二源极/漏极区之间的层间绝缘层。
CN201910489544.1A 2018-11-14 2019-06-06 包括源极/漏极区的半导体器件 Pending CN111192923A (zh)

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