CN111183513A - Method for manufacturing photoelectric semiconductor chip and bonding wafer used by same - Google Patents
Method for manufacturing photoelectric semiconductor chip and bonding wafer used by same Download PDFInfo
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- CN111183513A CN111183513A CN201980004714.0A CN201980004714A CN111183513A CN 111183513 A CN111183513 A CN 111183513A CN 201980004714 A CN201980004714 A CN 201980004714A CN 111183513 A CN111183513 A CN 111183513A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
Abstract
The invention provides a method for manufacturing photoelectric semiconductor chips and a bonding wafer used by the method. The method divides the traditional wafer into a mother wafer and a sub-wafer, and after the mother wafer and the sub-wafer are bonded by using a proper bonding technology, the traditional wafer can resist the high temperature of about 1000 ℃ of external delay and the warping change generated by stress; after the epitaxy the bond is released using a non-physically destructive method. The mother wafer can be recycled, the sub-wafer and the epitaxial layer are directly used for chip processing, thinning is not needed or is reduced a little, the problems of raw materials of large-size epitaxial wafers and chip processing cost are solved, and the epitaxial wafer with better wavelength uniformity is obtained.
Description
Technical Field
The invention relates to a manufacturing method of a photoelectric semiconductor chip, in particular to a bonded wafer suitable for epitaxy.
Background
Single crystal sapphire, silicon carbide, gallium arsenide crystal are typical epitaxial materials, have excellent photoelectric effect, and are widely used in LED, power devices. Sapphire, silicon carbide, gallium arsenide and other crystals all need to consume a large amount of electric energy during growth. And the larger the wafer size, the lower the yield of crystalline material, and the higher the cost of the semiconductor substrate wafer gradually transitioning from 4 inches to 6 inches or 8 inches.
The crystal is cut, ground, polished, cleaned and the like to form a wafer; after epitaxial growth, the thickness of the whole chip is required to be reduced in the chip manufacturing process so as to reduce the size of the chip. The thickness of the chip is usually only 1/3 of the wafer, that is, more than half of the crystal has to be ground by a thinning machine, and the waste of crystal material is great.
The thickness of the wafer is one of key factors influencing the uniformity of epitaxial wavelength, and the higher the thickness, the more the warping degree generated by the stress of the epitaxial layer can be reduced, so that the wavelength uniformity is improved; in order to reduce the chip size and waste of packaging materials, the chip thickness is becoming thinner and thinner, and therefore a thinner wafer substrate thickness is required. The thicker the wafer, the more costly it is to thin the wafer during the chip manufacturing process, which results in a large amount of waste of crystalline material.
Disclosure of Invention
The invention provides a method for solving the technical problems in the background technology, and discloses a method for manufacturing a photoelectric semiconductor chip. And selecting a proper bonding medium to grow a bonding medium film on the mother wafer, the daughter wafer or both, preferably growing a bonding medium on the surface of one of the mother wafer and the daughter wafer, and particularly preferably growing the bonding medium on the mother wafer as an intermediate layer. The intermediate layer comprises one of silicon dioxide, aluminum nitride and gallium nitride or any combination of the silicon dioxide, the aluminum nitride and the gallium nitride.
The bonding design is that the mother wafer and the son wafer are bonded under the vacuum high-temperature environment of 300 ℃ to 1000 ℃, and the bonding medium is positioned on the bonding surface. After the thin sub-wafer is processed by the semiconductor epitaxial process, the bonding medium can be separated after being damaged by a non-destructive bonding-breaking mode, and the sub-wafer separated from the mother wafer and the semiconductor epitaxial layer on the sub-wafer continue to be processed by the chip; the thicker mother wafer below can be subjected to high-temperature annealing after cleaning to release stress accumulated by epitaxial growth, and the annealed mother wafer can be recycled.
The thickness of the mother wafer and the sub-wafer can be designed according to the thickness of the final chip, and the thickness of the sub-wafer can be slightly less than or equal to the thickness of the substrate of the final chip. In order to improve the yield, the thickness of a thicker mother wafer is proposed; the thickness of the original wafer minus the thickness of the sub-wafer is the lowest thickness of the mother wafer. The surface of the mother wafer is a wafer with rough surfaces on both sides, and the stable rough surface can be manufactured by grinding high-hardness micro powder such as carborundum, boron carbide, silicon carbide and the like on both sides, and the Warping (WARP) generated by linear cutting is flattened; or rough surface made by yellow light, development, etching and other techniques. The surface of the sub-wafer to be epitaxially grown is defined as a front surface, the other surface opposite to the front surface is defined as a back surface, the back surface is oppositely bonded with the mother wafer, the front surface of the sub-wafer is a polished surface with an epitaxial grade, and the back surface and the mother wafer are both rough surfaces or polished surfaces. Before bonding, the growth surface of the bonding medium is cleaned and activated by using O3 and N2 in a plasma cleaning or chemical mode, and the activating treatment reagent comprises hydrogen peroxide, ammonia water or a mixture of the hydrogen peroxide and the ammonia water. The activation treatment may be a dry treatment, such as activation by plasma.
The bonding medium can be a silicon dioxide (SiO2), aluminum nitride (AlN) and other films, and an intermediate layer formed by the bonding medium needs to have a certain thickness to be uniformly bonded, for example, 3-5 μm is adopted to resist bending caused by high temperature of 1000 ℃ and epitaxial layer stress during epitaxial growth. The bonding condition needs to be carried out on high-temperature and vacuum bonding equipment. The non-destructive de-bonding method is an acid etching method, and the bonding medium is corroded and destroyed without damaging the wafer. The mother wafer is recycled, and the epitaxial stress is eliminated by cleaning, annealing and other processes, so that the mother wafer is relatively flat and is favorable for reuse.
Preferably, the thickness of the sub-wafer is 50-400 μm thicker than that of the final chip, a certain thinning adjusting space is reserved, after the sub-wafer is separated from the mother wafer, the side, away from the epitaxial layer, of the sub-wafer can be thinned, and the thickness of the mother wafer can be slightly thicker than the lowest mother wafer by 100-1000 μm to reserve a processing window. The thickness of the sub-wafer is 100-450 μm, and the thickness of the mother wafer is 300-1500 μm.
Preferably, the front surface of the sub-wafer is polished to have the roughness of 0.08-0.2 nm; the roughness of the back surface of the sub-wafer and the two surfaces of the mother wafer is 0.1 to 1.2 μm.
Preferably, the thickness of the middle layer formed by the bonding medium is 3-5 um.
Preferably, the bonding condition is 100-250 kg/cm under the vacuum environment at 300-400 DEG C2The pressure is applied to bond the mother wafer and the sub-wafer for 10-40 minutes.
Preferably, the debonding method is normal-temperature hydrofluoric acid (HF) etching of the silicon oxide bonding medium.
Preferably, the mother wafer is reused by cleaning with ultrasonic clean water, spin-drying, and annealing in a high-temperature annealing furnace at 1350-1400 ℃ to release residual stress in epitaxial production.
Preferably, in some cases, the mother wafer may include a first mother wafer and a second mother wafer, or be composed of more than two separable wafers.
The beneficial effects of the invention include:
the traditional wafer is divided into a mother wafer and a sub-wafer, and after the mother wafer and the sub-wafer are bonded by using a proper bonding technology, the high temperature of about 1000 ℃ of external delay time and the warping change generated by stress can be resisted; after the epitaxy the bond is released using a non-physically destructive method. The mother wafer can be recycled, the sub-wafer and the epitaxial layer are directly used for chip processing, thinning is not needed or is reduced a little, the problems of raw materials of large-size epitaxial wafers and chip processing cost are solved, and the epitaxial wafer with better wavelength uniformity is obtained.
In view of reducing the manufacturing cost of semiconductor devices and improving the efficiency of mass production, the research focusing on large-sized wafers requires better capability of resisting the process stress, and due to the recyclable characteristic of the mother wafer, the thickness of the mother wafer can be properly increased to maintain the stability of mass production, for example, the warpage problem during epitaxial growth is reduced, so that the uniformity of epitaxial growth is improved, the production cost cannot be obviously increased, and the significance in mass production of large-sized wafers is profound.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. Furthermore, the drawing figures are for a descriptive summary and are not drawn to scale.
FIG. 1 is a process flow for manufacturing a bonded wafer;
FIGS. 2-7 are schematic views of a process for fabricating an optoelectronic semiconductor product and corresponding bonded wafer photographs.
The following are marked in the figure: 100. A mother wafer; 110. a non-smooth surface; 200. a sub-wafer; 300. an intermediate layer; 310. an epitaxial layer.
Detailed Description
Several embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. The following description and illustrations of the embodiments do not limit the scope of the present invention in any way.
It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to fig. 1, the present invention provides a method for fabricating an optoelectronic semiconductor chip for fabricating a low-cost, high-performance, and environmentally friendly wafer, which is very cost-effective for large-sized sapphire, silicon carbide, or gallium arsenide wafers using the bonding method of the present invention. The method comprises the following steps: providing a mother wafer 100 and a sub-wafer 200 which are made of the same material or different materials, evaporating a dielectric layer on one surface of the mother wafer 100 and the sub-wafer 200, wherein the dielectric layer has a bonding characteristic, the dielectric layer is used as an intermediate layer 300, the dielectric layer is cleaned after being polished, the intermediate layer 300 is activated by ammonia water and hydrogen peroxide, the activation treatment aims to promote the surface of the intermediate layer 300 to form hydroxyl (-OH), the hydroxyl forms coulomb tension on Al or O of a wafer material, the intermediate layer is favorably connected with the mother wafer and the sub-wafer, the mother wafer 100 and the sub-wafer 200 are aligned in advance and are aligned with each other, a hot-press bonding process is carried out, a bonded wafer is obtained, and the bonded wafer is cleaned after.
Referring again to fig. 2-4, in detail, a mother wafer 100 and a daughter wafer 200 are provided, both of which are selected from materials including, but not limited to: sapphire, silicon carbide or gallium arsenide, and in order to perform the subsequent high-temperature bonding process, the wafer material can bear a high-temperature environment temperature not less than 1000 ℃. By providing the intermediate layer 300 between them, respectively, in the present embodimentThe SiO bonding dielectric material is deposited on the non-smooth surface 110 of the mother wafer 100 and the surface of the sub-wafer 200 opposite to the non-smooth surface 1002The intermediate layer 300 is manufactured (not shown in the intermediate layer figure), CMP (mechanical chemical polishing) is performed on the intermediate layer 300, since the SiO2 is manufactured in a vapor deposition mode, the flatness of the intermediate layer needs to be improved by polishing, and then after the two results are activated, the side with the intermediate layer 300 is oppositely bonded. In the embodiment, for example, the thickness of the mother wafer 100 is 300 μm to 500 μm, in order to prevent the wafer from being broken, the thickness of the mother wafer 100 tends to increase with the increase of the wafer area, so that in a large-sized wafer, for example, an eight-inch wafer, the thickness of the mother wafer 100 may reach 1500 μm, and the thickness of the sub-wafer 200 is 100 μm to 450 μm, the thickness of the sub-wafer 200 in the present invention concept may reach at least 100 μm, and it is clear that, with the improvement of the wafer manufacturing technology, the thinner sub-wafer 200 may be obtained by using the technical solution of the present invention.
In some embodiments, the better the cleanliness of the wafer surface, the better the quality of the grown bonding medium, and the better the bonding effect, the better the bonded wafer is cleaned after polishing. The smaller the Warpage (WARP), flatness (TTV), etc. of the wafer, the better the bonding effect, and even the thickness of the bonding medium can be reduced. Suitable bonding media need to be lattice matched to the wafer material, such as silicon dioxide (SiO)2) One or more of thin films of aluminum nitride (AlN), gallium nitride (GaN), and the like. A thin film may be grown on the mother wafer or both the mother wafer 100 and the daughter wafer 200 may be grown and bonded at a suitable temperature and pressure.
In the embodiment of the present invention, based on the above scheme, the surface roughness of the mother wafer 100 relative to the sub-wafer 200 may also affect the bonding effect. The rougher the surface of the wafer is, the denser the bonding medium is; however, the roughness is too large, but holes are easily formed, which affects the bonding effect, and in this embodiment, the roughness is controlled to be 0.1 to 1.2 μm.
In this embodiment, the mother wafer 100 and the sub-wafer 200 have to be the same size, and the diameter should be within ± 0.1mm, so as to facilitate the alignment of the mother wafer 100 and the sub-wafer 200 during bonding. The Sapphire wafer for LED needs to be Patterned (PSS) on the surface of the sub-wafer 200 by processes of exposure, development, etching, and the like to increase the light emitting effect in the light emitting semiconductor device. The bonding process of the wafer is recommended to avoid the damage of the bonding pressure on the patterns before the patterns are manufactured.
In other embodiments, unlike other physical damage methods, such as laser separation, which cuts a deep trench around the side of the wafer and then separates the wafer with a tool in a low temperature environment, the damage may generate a plurality of corner breakages, which reduces the recycling rate of the mother wafer 100. In the present embodiment, the bonding medium is debonded by acid etching, and for example, a sapphire wafer is used, the bonding medium silicon oxide is etched by hydrofluoric acid, and the silicon oxide can be easily separated after being soaked in hydrofluoric acid at normal temperature for 40 minutes without affecting the epitaxial layer and the wafer body of the semiconductor device.
Referring to fig. 5, the sub-wafer 200 is used for epitaxy, and a smooth surface is disposed on a side of the sub-wafer 200 away from the bonding surface, for producing an epitaxial layer 210, which includes an N-side layer, a P-side layer, and an active layer therebetween, for example, by MOCVD metal organic chemical vapor deposition of semiconductor material.
Referring to fig. 6 and 7, after the epitaxial layer 210 is fabricated, the intermediate layer 300 is released and the mother wafer 100 and the daughter wafer 200 are separated. The sub-wafer 200 continues a chip manufacturing process, for example, a chip pattern is manufactured on one side of the epitaxial layer 210 away from the sub-wafer 200 by using photoresist etching, a part of the P-side layer is removed until the N-side layer is exposed, then an insulating protection layer or a transparent conductive diffusion layer is manufactured on the surface of the P-side layer and/or the exposed N-side layer, and finally a chip electrode connected with the P-side layer and the exposed N-side layer is manufactured to form a light-emitting semiconductor chip structure.
Meanwhile, the separated mother wafer 100 can be recycled after high-temperature annealing for manufacturing the bonded wafer again. The sub-wafer 200 is thinned to accommodate chip processing requirements. The thinning thickness of the sub-wafer 200 can be greatly lower than that of the substrate in the prior art, for example, a 750-micron-thick wafer substrate is taken as an example, the invention can obtain a 100-micron chip substrate wafer only by removing about 200-micron wafer materials, and for comparison, 650 microns need to be removed in the prior art, and the removal amount is more than 3 times that of the invention. In industrial production, a grinding and removing mode is usually adopted to remove redundant substrate materials, the efficiency of the grinding process for removing the substrate materials is low, and grinding wheels are consumed, so that the processing time is long, and the loss of production spare parts such as grinding wheels is increased, therefore, compared with the prior art, the invention saves the production cost, shortens the thinning time, reduces the generated industrial waste, and plays a positive role in promoting the industrialization of large wafers with the size of six inches and more.
In some embodiments, the mother wafer 100 may be further designed to include a first mother wafer and a second mother wafer bonding assembly according to the actual thickness requirement, so that wafer-by-wafer removal can be realized to control the thickness control of the wafer substrate.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and improvements can be made without departing from the principle of the present invention, and these modifications and improvements should also be considered as the protection scope of the present invention.
Claims (21)
1. A method for producing an optoelectronic semiconductor chip, comprising the process steps:
step 1, providing a mother wafer and a sub-wafer, and bonding the mother wafer and the sub-wafer into a bonded wafer through an intermediate layer arranged between the mother wafer and the sub-wafer;
step 2, manufacturing an epitaxial layer on the surface of one side, close to the sub-wafer, of the bonded wafer;
and 3, unwinding the middle layer and separating the mother wafer and the sub-wafer.
2. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: the released sub-wafer and epitaxial layer continue to be processed into chips, and the mother wafer is recycled.
3. A method for fabricating optoelectronic semiconductor chips as recited in claim 2, wherein: and the untied mother wafer is recycled after high-temperature annealing.
4. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: and thinning the untwisted sub-wafer from the side far away from the epitaxial layer.
5. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: step 1, before bonding, an intermediate layer is respectively manufactured on the opposite surfaces of the mother wafer and the sub-wafer or only one of the opposite surfaces of the mother wafer and the sub-wafer.
6. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: the mother wafer and the sub-wafer comprise sapphire, silicon carbide or gallium arsenide.
7. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: the thickness of the sub-wafer is 100 μm to 450 μm.
8. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: the thickness of the mother wafer is 300-1500 μm.
9. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: the temperature of the high-temperature environment which can be borne by the mother wafer and/or the sub-wafer is not less than 1000 ℃.
10. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: the intermediate layer comprises one or any combination of silicon dioxide, aluminum nitride and gallium nitride.
11. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: the intermediate layer may be removed by an etching process.
12. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: the mother wafer at least comprises a first mother wafer and a second mother wafer.
13. A method for fabricating optoelectronic semiconductor chips as recited in claim 1, wherein: and performing activation treatment on the intermediate layer.
14. A method for fabricating optoelectronic semiconductor chips as recited in claim 13, wherein: the activating agent comprises hydrogen peroxide, ammonia water or a mixture of the hydrogen peroxide and the ammonia water.
15. A method for fabricating optoelectronic semiconductor chips as recited in claim 13, wherein: the activation treatment is a dry treatment, and is activated by plasma.
16. A bonded wafer as a growth substrate for manufacturing an optoelectronic semiconductor chip, characterized in that: the bonded wafer comprises a mother wafer, a sub-wafer and an intermediate layer between the mother wafer and the sub-wafer.
17. The bonded wafer of claim 16, wherein: the thickness of the sub-wafer is 100 μm to 450 μm.
18. The bonded wafer of claim 16, wherein: the mother wafer is 300-1500 μm.
19. The bonded wafer of claim 16, wherein: the thickness of the intermediate layer is 3 μm to 5 μm.
20. The bonded wafer of claim 16, wherein: and the surface of one side of the sub-wafer, which is far away from the mother wafer, is a smooth surface.
21. The bonded wafer of claim 16, wherein: the mother wafer at least comprises a first mother wafer and a second mother wafer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2019/083521 WO2020211089A1 (en) | 2019-04-19 | 2019-04-19 | Method for preparing optoelectronic semiconductor chip and bonding wafer used therein |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111183513A true CN111183513A (en) | 2020-05-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201980004714.0A Pending CN111183513A (en) | 2019-04-19 | 2019-04-19 | Method for manufacturing photoelectric semiconductor chip and bonding wafer used by same |
Country Status (4)
| Country | Link |
|---|---|
| KR (1) | KR20210120058A (en) |
| CN (1) | CN111183513A (en) |
| TW (1) | TWI734359B (en) |
| WO (1) | WO2020211089A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111952151A (en) * | 2020-07-28 | 2020-11-17 | 苏州赛万玉山智能科技有限公司 | Semiconductor composite wafer and method of manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102601702B1 (en) * | 2022-10-31 | 2023-11-13 | 웨이브로드 주식회사 | Method for manufacturing semiconductor light emitting devices using template for semiconductor growth |
| KR102649711B1 (en) * | 2022-12-02 | 2024-03-20 | 웨이브로드 주식회사 | Method for manufacturing ultra-thin type semiconductor die |
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| CN102486992A (en) * | 2010-12-01 | 2012-06-06 | 比亚迪股份有限公司 | Manufacturing method of semiconductor device |
| CN102184882A (en) * | 2011-04-07 | 2011-09-14 | 中国科学院微电子研究所 | Method for forming composite functional material structure |
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2019
- 2019-04-19 CN CN201980004714.0A patent/CN111183513A/en active Pending
- 2019-04-19 WO PCT/CN2019/083521 patent/WO2020211089A1/en active Application Filing
- 2019-04-19 KR KR1020217027188A patent/KR20210120058A/en not_active Application Discontinuation
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2020
- 2020-01-22 TW TW109102559A patent/TWI734359B/en active
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| TW200849337A (en) * | 2007-06-06 | 2008-12-16 | Soitec Silicon On Insulator | Process for fabricating a structure for epitaxy without an exclusion zone |
| KR20100033641A (en) * | 2008-09-22 | 2010-03-31 | 주식회사 동부하이텍 | Method for wafer recycling of semiconductor device |
| CN102956762A (en) * | 2011-08-26 | 2013-03-06 | 郑朝元 | Method and structure enabling III-V-group wafer to be reusable for epitaxial processes |
| CN103165625A (en) * | 2011-12-15 | 2013-06-19 | 电力集成公司 | Composite wafer for fabrication of semiconductor devices |
| US20130157440A1 (en) * | 2011-12-15 | 2013-06-20 | Power Integrations, Inc. | Composite wafer for fabrication of semiconductor devices |
| US9761493B2 (en) * | 2014-01-24 | 2017-09-12 | Rutgers, The State University Of New Jersey | Thin epitaxial silicon carbide wafer fabrication |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111952151A (en) * | 2020-07-28 | 2020-11-17 | 苏州赛万玉山智能科技有限公司 | Semiconductor composite wafer and method of manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202039945A (en) | 2020-11-01 |
| WO2020211089A1 (en) | 2020-10-22 |
| KR20210120058A (en) | 2021-10-06 |
| TWI734359B (en) | 2021-07-21 |
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