CN111182742A - Circuit board and manufacturing method thereof - Google Patents
Circuit board and manufacturing method thereof Download PDFInfo
- Publication number
- CN111182742A CN111182742A CN201811334125.2A CN201811334125A CN111182742A CN 111182742 A CN111182742 A CN 111182742A CN 201811334125 A CN201811334125 A CN 201811334125A CN 111182742 A CN111182742 A CN 111182742A
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- Prior art keywords
- layer
- circuit
- layers
- circuit board
- manufacturing
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
Abstract
The invention provides a circuit board manufacturing method, which comprises the following steps: providing a substrate, wherein the substrate comprises a base layer and two circuit layers respectively arranged on two sides of the base layer, and the base layer is made of a non-metallizable material; respectively attaching covering layers to the two circuit layers, wherein each covering layer comprises an adhesive layer and a bottom film, the bottom film is attached to the circuit layers through the adhesive layers, each covering layer does not cover the partial area of the circuit layer to form an exposed area, and the bottom film is made of a metallizable material; perforating a through hole on the covering layer; forming a metal seed layer on the surface of the bottom film and the wall of the through hole; forming a copper plating layer on the metal seed layer; and carrying out circuit manufacturing on the copper plating layer on the bottom film to form a circuit pattern. The invention also provides a circuit board. The invention simplifies the flow and the process of the circuit board manufacturing method and reduces the cost.
Description
Technical Field
The invention relates to a circuit board and a manufacturing method thereof.
Background
When the multilayer circuit board is manufactured, glue is firstly coated to connect the single-layer board and the substrate, then glue solidification such as fixing is carried out in a pressing mode, and then the multilayer board is conducted through processes such as laser and hole plating. It is also desirable to expose the outer circuit board by tearing the cover. The manufacturing method of the multilayer circuit board has the disadvantages of more complicated steps and longer time consumption. And when the amount of glue spillage is too great, there is also a risk that the lid cannot be torn open.
Disclosure of Invention
In view of the above, it is desirable to provide a circuit board with simple manufacturing process and a manufacturing method thereof.
A circuit board manufacturing method comprises the following steps:
providing a substrate, wherein the substrate comprises a base layer and two circuit layers respectively arranged on two sides of the base layer, and the base layer is made of a non-metallizable material;
respectively attaching covering layers to the two circuit layers, wherein each covering layer comprises an adhesive layer and a bottom film, the bottom film is attached to the circuit layers through the adhesive layers, each covering layer does not cover the partial area of the circuit layer to form an exposed area, and the bottom film is made of a metallizable material;
perforating a through hole on the covering layer;
forming a metal seed layer on the surface of the bottom film and the wall of the through hole;
forming copper plating layers on the metal seed layer and the circuit layer positioned in the exposed area, so that the thickness of the circuit layer positioned in the exposed area is larger than that of the circuit layer positioned in the unexposed area;
and carrying out circuit manufacturing on the copper plating layer on the bottom film to form a circuit pattern.
Preferably, the base film polyimide is ring-opened by a roughening activation treatment so that a metal seed layer can be formed in combination with other metals.
Preferably, after the step of forming the circuit pattern by performing circuit fabrication on the copper plating layer on the base film, the method further includes forming a solder mask layer on the circuit pattern.
Preferably, the substrate is formed by: providing a double-sided copper-clad substrate, wherein the double-sided copper-clad substrate comprises a base layer and two copper foil layers respectively attached to two sides of the base layer; forming at least one first via in the double-sided copper-clad substrate by a drilling technique; manufacturing the at least one first through hole into a conductive hole through an electroless copper plating process and an electroplating copper process; and selectively etching the two copper foil layers through an image transfer process and an etching process to respectively form two circuit layers.
Preferably, the circuit pattern is formed by laminating, exposing, developing, etching and stripping a film, wherein a dry film is laminated on the exposed area to protect the circuit of the exposed area during laminating the film.
Preferably, the metal seed layer is formed by a sputtering process or an electroless plating process, and the metal of the metal seed layer includes at least one of titanium, nickel, vanadium, copper, aluminum, an aluminum alloy, tungsten, chromium, silver, or gold.
The utility model provides a circuit board, includes the basic unit and locates respectively two circuit layers of basic unit both sides, each the basement membrane has been pasted respectively on the circuit layer, the basement membrane does not cover the subregion on circuit layer is in order to form and exposes the district, is located the thickness on the circuit layer that exposes the district is greater than the thickness that is located the circuit layer that the district is not exposed, the basement membrane is equipped with the perforating hole, be filled with conductive metal material in the perforating hole, the basement membrane deviates from one side on circuit layer is equipped with the circuit pattern, the basic unit is non-metallizable material, the basement membrane is metallizable material.
Preferably, a solder mask layer is further disposed outside the circuit pattern, the solder mask layer includes an opening, and the opening exposes the solder pad of the circuit pattern.
Preferably, the circuit pattern includes a metal seed layer and a copper plating layer, and the metal seed layer is adjacent to the base film.
Preferably, the base film is polyimide, which is in an open-loop structure and is connected to the metal seed layer.
Compared with the prior art, the manufacturing method of the circuit board utilizes the difference between the non-metallizable base layer and the metallizable base film, and the base layer is not influenced when copper is plated on the base film, so that partial region exposure of the circuit layer on the base layer can be realized under the condition that a tearing cover process is cancelled, and the operation flow is simplified. The exposed area is always in an exposed state, so that the cover cannot be torn open due to excessive glue overflow and the like. In addition, the copper plating of the through-hole can be formed simultaneously with the formation of the copper plating layer, without an additional hole plating process.
Drawings
FIG. 1 is a cross-sectional view of a double-sided copper-clad substrate according to an embodiment of the present invention
Fig. 2 is a cross-sectional view of a substrate according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view of the substrate of fig. 1 after attaching a cover layer.
Fig. 4 is a cross-sectional view of the cover layer of fig. 3 after punching a through hole.
Fig. 5 is a cross-sectional view of the base film of the cap layer shown in fig. 4 after forming a metal seed layer.
Fig. 6 is a cross-sectional view of the metal seed layer shown in fig. 5 after a copper plating layer is formed thereon.
Fig. 7 is a cross-sectional view of the copper plated layer of fig. 6 after laminating a dry film thereon.
Fig. 8 is a cross-sectional view of the dry film of fig. 7 after exposure.
Fig. 9 is a cross-sectional view of the copper plating layer of fig. 8 after patterning for wiring.
Fig. 10 is a cross-sectional view of a circuit board made in accordance with an embodiment of the present invention.
Description of the main elements
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Referring to fig. 1 to 10, a method for manufacturing a circuit board according to a preferred embodiment of the invention includes the following steps:
s101 referring to fig. 2, a substrate 10 is provided, where the substrate 10 includes a base layer 11 and two circuit layers 12 respectively disposed on two sides of the base layer 11, and the base layer 11 is made of a non-metallizable material.
Referring also to fig. 1, the substrate 10 is formed by: firstly, providing a double-sided copper-clad substrate 13 as shown in fig. 1, wherein the double-sided copper-clad substrate 13 comprises a base layer 11 and two copper foil layers 14 respectively attached to two sides of the base layer 11; next, at least one first through hole is formed in the double-sided copper-clad substrate 13 by a drilling technique, and then a copper layer is deposited in the at least one first through hole by an electroless copper plating process and an electrolytic copper plating process, thereby making the at least one first through hole into a conductive hole 101, and again, the two copper foil layers 14 are selectively etched by an image transfer process and an etching process to form two wiring layers 12, respectively.
In this embodiment, the base layer 11 is made of non-metallizable Polyimide (PI), i.e., a metal seed layer cannot be formed on the surface of the base layer 11 by a sputtering process or a chemical plating process. It is understood that in other embodiments, the material of the base layer 11 may be other non-metallizable materials.
S102 referring to fig. 3, respectively attaching cover layers 20 to the two circuit layers 12, where each of the cover layers 20 includes an adhesive layer 21 and a bottom film 22, the bottom film 22 is attached to the circuit layers 12 through the adhesive layer 21, an exposed area 121 is formed in a partial area of each of the cover layers 20 not covering the circuit layers 12, and the bottom film 22 is a metallizable bottom film;
in the embodiment, the primary film 22 is polyimide after roughening activation, and is opened by roughening activation treatment to form a metal seed layer capable of combining with other metals.
S103 referring to fig. 4, through holes 23 are punched in the cover layer 20.
The through hole 23 penetrates through the base film 22 and the adhesive layer 21 and extends to the wiring layer 12. In this embodiment, the through hole 23 is formed by laser ablation. In other embodiments, the through hole 23 may be formed by mechanical drilling. The number of the through holes 23 may be one or plural.
S104 referring to fig. 5, a metal seed layer 24 is formed on the surface of the base film 22 and the hole walls of the through holes 23.
The metal seed layer 24 may be formed by a sputtering process or an electroless plating process. The metal of the metal seed layer 24 includes at least one of titanium, nickel, vanadium, copper, aluminum, tungsten, chromium, silver, and gold.
Since the base layer 11 is made of non-metallizable material, the exposed region 121 will not form a metal seed layer. The capping layer 20 also forms a metal seed layer 24 on the sidewalls of the exposed region 121.
S105 referring to fig. 6, a copper plating layer 25 is formed on the metal seed layer 24 and the circuit layer 12 in the exposed region 121.
In this embodiment, a copper plating layer 25 is formed on the metal seed layer 24 on the surface of the base film 22 and the wiring layer 12 in the exposed region 121 by electroplating, and a conductive metal material 231 is formed on the surface of the metal seed layer 24 on the wall of the through hole 23. The conductive metal material 231 is integrally molded with the copper plating layer 25, and the through-hole 23 is completely filled with the conductive metal material 231. The circuit layer 12 in the exposed region 121 includes the copper foil layer 14 and the copper plating layer 25, and thus has a thickness greater than that of the rest of the circuit layer 12 in the unexposed region.
The capping layer 20 also forms a copper plating layer 25 on the sidewalls of the exposed region 121.
S106 referring to fig. 9, the copper plating layer 25 is subjected to a circuit process to form a circuit pattern 26.
Referring to fig. 7 and 8 together, fig. 7 and 8 are cross-sectional views of a copper-clad dry film laminate and exposure of the dry film, respectively. The circuit pattern 26 is formed by laminating, exposing, developing, etching, and removing a film. During lamination, the dry film 40 is pressed on the exposed region 121 to protect the circuit of the exposed region 121. The metal seed layer 24 and the copper plating layer 25 formed on the sidewall of the cover layer 20 located in the exposed region 121 are removed together during etching.
S107 referring to fig. 10, a solder mask 30 is formed on the circuit pattern 26.
The solder mask layer 30 is solder mask ink, and the solder mask layer 30 can be formed by coating or printing a layer of solder mask ink by a roller and curing the solder mask ink. The solder mask 30 includes an opening 31, and the opening 31 exposes the pad 261 of the circuit pattern 26. The solder mask 30 is used to protect the circuit pattern 26 and prevent the circuit pattern 26 from being oxidized, scratched, and the like.
Referring to fig. 10, a circuit board 100 according to a preferred embodiment of the invention includes a base layer 11 and two circuit layers 12 respectively disposed on two sides of the base layer 11. Each of the wiring layers 12 is attached with a carrier film 22. The bottom film 22 has a through hole 23 formed therethrough, and the through hole 23 is filled with a conductive metal material 231. The side of the carrier film 22 facing away from the wiring layer 12 is provided with a wiring pattern 26.
The carrier film 22 does not cover a partial area of the wiring layer 12 to form an exposed area 121. The base layer 11 is made of non-metallizable material, and the bottom film 22 is made of metallizable material.
The circuit pattern 26 is further provided with a solder mask layer 30. The solder mask 30 includes an opening 31, and the opening 31 exposes the pad 261 of the circuit pattern 26.
The line pattern 26 includes a metal seed layer 24 and a copper plating layer 25, and the metal seed layer 24 is adjacent to the base film 22.
The circuit layer 12 in the exposed region 121 includes a copper foil layer 14 and a copper plating layer 25, which have a thickness greater than that of the rest of the circuit layer 12 in the unexposed region.
Compared with the prior art, the manufacturing method of the circuit board of the invention utilizes the difference between the non-metallizable base layer 11 and the metallizable base film 22, and the base layer 11 is not affected when the base film 22 is plated with copper, so that the partial region exposure of the circuit layer 12 on the base layer 11 can be realized under the condition that the tearing cover process is cancelled, and the operation flow is simplified. The exposed area 121 is always exposed, so that the cover cannot be torn open due to excessive glue overflow. Further, the copper plating of the through-hole 23 can be formed simultaneously with the formation of the copper plated layer 25, without an additional hole plating process.
Although the present invention has been described with reference to the above preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A circuit board manufacturing method comprises the following steps:
providing a substrate, wherein the substrate comprises a base layer and two circuit layers respectively arranged on two sides of the base layer, and the base layer is made of a non-metallizable material;
respectively attaching covering layers to the two circuit layers, wherein each covering layer comprises an adhesive layer and a bottom film, the bottom film is attached to the circuit layers through the adhesive layers, the partial area of each covering layer, which does not cover the circuit layers, forms an exposed area, and the bottom film is made of metallizable materials;
perforating a through hole on the covering layer;
forming a metal seed layer on the surface of the bottom film and the wall of the through hole;
forming copper plating layers on the metal seed layer and the circuit layer positioned in the exposed area, so that the thickness of the circuit layer positioned in the exposed area is larger than that of the circuit layer positioned in the unexposed area;
and carrying out circuit manufacturing on the copper plating layer on the bottom film to form a circuit pattern.
2. The method of manufacturing a circuit board according to claim 1, wherein: the basement membrane is polyimide, and the basement membrane is opened by coarsening and activating treatment so as to be combined with other metals to form a metal seed layer.
3. The method of manufacturing a circuit board according to claim 1, wherein: and after the step of carrying out circuit manufacturing on the copper plating layer on the bottom film to form a circuit pattern, the method also comprises the step of forming a solder mask layer on the circuit pattern.
4. The method of manufacturing a circuit board according to claim 1, wherein: the substrate is formed by the steps of: providing a double-sided copper-clad substrate, wherein the double-sided copper-clad substrate comprises a base layer and two copper foil layers respectively attached to two sides of the base layer; forming at least one first via in the double-sided copper-clad substrate by a drilling technique; manufacturing the at least one first through hole into a conductive hole through an electroless copper plating process and an electroplating copper process; and selectively etching the two copper foil layers through an image transfer process and an etching process to respectively form two circuit layers.
5. The method of manufacturing a circuit board according to claim 1, wherein: the circuit pattern is formed by pressing a dry film, exposing, developing, etching and removing the dry film, wherein when the dry film is pressed, the dry film is pressed on the exposed area together to protect the circuit of the exposed area.
6. The method of manufacturing a circuit board according to claim 1, wherein: the metal seed layer is formed through a sputtering process or a chemical plating process, and the metal of the metal seed layer comprises at least one of titanium, nickel, vanadium, copper, aluminum alloy, tungsten, chromium, silver or gold.
7. The utility model provides a circuit board, includes the basic unit and locates respectively two circuit layers of basic unit both sides, its characterized in that: each the line layer is last to be pasted the basement membrane respectively, the basement membrane does not cover the subregion on line layer is in order to form and exposes the district, is located the thickness on the line layer that exposes the district is greater than the thickness that is located the line layer that does not expose the district, the basement membrane is equipped with the perforating hole, be filled with conductive metal material in the perforating hole, the basement membrane deviates from one side on line layer is equipped with the line pattern, the basic unit is non-metallizable material, the basement membrane is metallizable material.
8. The circuit board of claim 7, wherein: the circuit pattern is also provided with a solder mask layer outside, the solder mask layer comprises an opening, the circuit pattern comprises a welding pad, and the opening exposes the welding pad of the circuit pattern.
9. The circuit board of claim 7, wherein: the circuit pattern comprises a metal seed layer and a copper plating layer, wherein the metal seed layer is close to the base film.
10. The circuit board of claim 9, wherein: the base film is polyimide and is in an open-loop structure so as to be connected with the metal seed layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811334125.2A CN111182742B (en) | 2018-11-09 | 2018-11-09 | Circuit board and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811334125.2A CN111182742B (en) | 2018-11-09 | 2018-11-09 | Circuit board and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111182742A true CN111182742A (en) | 2020-05-19 |
| CN111182742B CN111182742B (en) | 2021-05-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811334125.2A Active CN111182742B (en) | 2018-11-09 | 2018-11-09 | Circuit board and manufacturing method thereof |
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| Country | Link |
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| CN (1) | CN111182742B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6094745A (en) * | 1983-10-28 | 1985-05-27 | Matsushita Electric Works Ltd | Printed circuit board |
| CN102686051A (en) * | 2012-06-07 | 2012-09-19 | 杭州华三通信技术有限公司 | Processing method of printed circuit board (PCB) and PCB |
| CN102711392A (en) * | 2012-06-25 | 2012-10-03 | 广州美维电子有限公司 | Manufacturing method of flexible-rigid circuit board |
-
2018
- 2018-11-09 CN CN201811334125.2A patent/CN111182742B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6094745A (en) * | 1983-10-28 | 1985-05-27 | Matsushita Electric Works Ltd | Printed circuit board |
| CN102686051A (en) * | 2012-06-07 | 2012-09-19 | 杭州华三通信技术有限公司 | Processing method of printed circuit board (PCB) and PCB |
| CN102711392A (en) * | 2012-06-25 | 2012-10-03 | 广州美维电子有限公司 | Manufacturing method of flexible-rigid circuit board |
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| Publication number | Publication date |
|---|---|
| CN111182742B (en) | 2021-05-28 |
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