CN111181506A - Broadband efficient J-type power amplifier with novel output matching method - Google Patents
Broadband efficient J-type power amplifier with novel output matching method Download PDFInfo
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- CN111181506A CN111181506A CN202010064004.1A CN202010064004A CN111181506A CN 111181506 A CN111181506 A CN 111181506A CN 202010064004 A CN202010064004 A CN 202010064004A CN 111181506 A CN111181506 A CN 111181506A
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- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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Abstract
The invention discloses a broadband high-efficiency J-class power amplifier with a novel output matching method, which comprises an input matching network control module, a grid bias control module, a stable network control module, a transistor, an output matching network control module and a drain bias control module, wherein the input matching network control module, the stable network control module, the transistor and the output matching network control module are sequentially connected, the grid bias control module is connected with the input matching network control module, the drain bias control module is connected with the output matching network control module, and a novel topological network structure is combined, so that the design process is simplified, and the J-class amplifier efficiency is improved.
Description
Technical Field
The invention relates to the technical field of electronic information, in particular to a broadband efficient J-type power amplifier with a novel output matching method.
Background
Due to the increasing number of wireless communication users and the requirement for more extensive and faster data services, wireless communication technologies are constantly being innovated and developed. From 1G to 2G, from 3G to 4G, and to a 5G wireless communication network system facing the market, the data transmission rate is required to be faster and the bandwidth is required to be wider, the wireless communication system is evolving towards a multi-operation mode and high-rate transmission direction, and the power amplifier is an important component in the wireless communication system, and the performance of the power amplifier has an important influence on the transmitting system part of the wireless communication. Broadband high efficiency power amplifiers are an urgent need in the current field of wireless communications. The J-type power amplifier is also called a continuous J-type power amplifier, and has the advantages that high efficiency can be maintained, and meanwhile, good bandwidth characteristics can be obtained, but the drain efficiency of the J-type power amplifier is 78.5%. The power added efficiency of the designed J-type power amplifier is mostly between 50% and 65%, so the efficiency of the J-type power amplifier is still relatively low, and the efficiency of the J-type power amplifier needs to be improved. For the design of a class-J power amplifier, the current design is mostly based on the optimal impedance value at the load traction position, and after a harmonic control network is designed, a fundamental wave broadband matching network is designed. The complexity of the design is increased and often the design is biased and difficult to achieve the desired result.
Disclosure of Invention
The invention aims to provide a broadband high-efficiency J-class power amplifier with a novel output matching method, which simplifies the design process and improves the efficiency of the J-class amplifier.
In order to achieve the above object, the present invention provides a broadband high-efficiency J-class power amplifier with a novel output matching method, which includes an input matching network control module, a gate bias control module, a stable network control module, a transistor, an output matching network control module, and a drain bias control module, wherein the input matching network control module, the stable network control module, the transistor, and the output matching network control module are sequentially connected, the gate bias control module is connected to the input matching network control module, and the drain bias control module is connected to the output matching network control module.
The input matching network control module comprises a microstrip line TL1, a microstrip line TL2 and a microstrip line TL3, wherein the microstrip line TL1 is sequentially connected with the microstrip line TL2 and the microstrip line TL 3.
The gate bias control module comprises a microstrip line TL4, a capacitor C4 and a capacitor C3, one end of the microstrip line TL4 is connected with the microstrip line TL3, the other end of the microstrip line TL4 is connected with one ends of the capacitor C4 and the capacitor C3, and the other ends of the capacitor C4 and the capacitor C3 are grounded.
The stabilizing network control module comprises a resistor R1 and a capacitor C2, wherein one end of the resistor R1 connected with the capacitor C2 in parallel is connected with the microstrip line TL3, and the other end of the resistor R1 connected with the transistor.
The output matching network control module comprises a microstrip line TL5, a microstrip line TL6, a microstrip line TL7, a microstrip line TL8, a microstrip line TL9 and a microstrip line TL10, the microstrip line TL5, the microstrip line TL6, the microstrip line TL7 and the microstrip line TL8 are sequentially connected, and the microstrip line TL9 is respectively connected with the microstrip line TL7 and the microstrip line TL 10.
The drain bias control module comprises a microstrip line TL11, a capacitor C5, a capacitor C6 and a capacitor C7, one end of the microstrip line TL11 is connected with the microstrip line TL7, the other end of the microstrip line TL11 is connected with one ends of the capacitor C5, the capacitor C6 and the capacitor C7, and the other ends of the capacitor C5, the capacitor C6 and the capacitor C7 are grounded.
The broadband efficient J-type power amplifier with the novel output matching method further comprises a capacitor C8, and the capacitor C8 is connected with the microstrip line TL 10.
The broadband efficient J-class power amplifier with the novel output matching method further comprises a dielectric substrate, the dielectric substrate is connected with the input matching network control module, the grid electrode bias control module, the stabilizing network control module, the transistor, the output matching network control module and the drain electrode bias control module, and the dielectric substrate is made of Rogers 4350.
The broadband efficient J-class power amplifier with the novel output matching method comprises an input matching network control module, a grid bias control module, a stabilizing network control module, a transistor, an output matching network control module and a drain bias control module, wherein the input matching network control module, the stabilizing network control module, the transistor and the output matching network control module are sequentially connected, the grid bias control module is connected with the input matching network control module, the drain bias control module is connected with the output matching network control module, and a novel topological network structure is combined, so that the design process is simplified, and the efficiency of the J-class amplifier is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic circuit structure diagram of a wideband high-efficiency class-J power amplifier with a novel output matching method provided by the present invention.
Fig. 2 is a simple topology of the class J power amplifier of the present invention.
Fig. 3 is a topology diagram of a control network introducing peripheral harmonics, which is provided by the present invention.
Fig. 4 is an equivalent model of the CGH40010F transistor provided by the present invention.
Fig. 5 is a diagram of the novel topology matching network provided by the present invention.
Fig. 6 is a graph of the relationship between the output capacitance and the drain-source voltage provided by the present invention.
Fig. 7 is a power amplifier frequency sweep characteristic diagram of a broadband efficient class-J power amplifier with a novel output matching method provided by the invention.
Fig. 8 is a comparison graph of power added efficiency of the conventional and improved class-J power amplifiers at 1.5-2.5 GHz.
The device comprises a 1-input matching network control module, a 2-grid bias control module, a 3-stable network control module, a 4-transistor, a 5-output matching network control module and a 6-drain bias control module.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention. Further, in the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Referring to fig. 1, the present invention provides a wideband high-efficiency J-class power amplifier with a novel output matching method, where the wideband high-efficiency J-class power amplifier with the novel output matching method includes an input matching network control module 1, a gate bias control module 2, a stabilization network control module 3, a transistor 4, an output matching network control module 5, and a drain bias control module 6, where the input matching network control module 1, the stabilization network control module 3, the transistor 4, and the output matching network control module 5 are sequentially connected, the gate bias control module 2 is connected to the input matching network control module 1, and the drain bias control module 6 is connected to the output matching network control module 5.
In this embodiment, the broadband high-efficiency class-J power amplifier with the novel output matching method includes an input matching network control module 1, a gate bias control module 2, a stabilization network control module 3, a transistor 4, an output matching network control module 5, and a drain bias control module 6, where the input matching network control module 1, the stabilization network control module 3, the transistor 4, and the output matching network control module 5 are connected in sequence, the gate bias control module 2 is connected with the input matching network control module 1, and the drain bias control module 6 is connected with the output matching network control module 5, and since the class-J power amplifier has special fundamental wave and second harmonic impedance requirements, a simple implementation structure is to provide a second harmonic impedance value through an output capacitor, mainly a drain-source capacitor, the structure of the class-J power amplifier is shown in fig. 2, but because the bandwidth of the parasitic capacitance is limited, the class-J power amplifier realized by adopting the simple topology design cannot realize the required second harmonic impedance in a wider frequency range, so that the class-J power amplifier with the structure is not very good in broadband performance, and therefore, an additional harmonic control network is necessarily introduced, as shown in fig. 3. Firstly, power is input through an input port, the power enters the input matching network control module 1 (or input matching network) after passing through a capacitor C1, the power sequentially passes through the transistor 4 and the output matching network control module 5 (or output matching network), harmonic control is performed by the grid bias control module 2 and the drain bias control module 6, for the transistor 4, a CREE GaN CGH40010F transistor 4 is used, an equivalent model thereof is shown in FIG. 4, and the transistor comprises a current source plane, a packaging plane, three capacitors and three lead inductors, wherein the capacitance values of the three capacitors are 1.22pF, 0.25pF and 0.25pF respectively, the lengths of the three lead inductors are 0.5nH, 0.1nH and 0.1nH respectively, and the resistance values are 0.1 omega respectively, the design process is simplified, and the J-class amplifier efficiency is improved.
Further, the input matching network control module 1 includes a microstrip line TL1, a microstrip line TL2, and a microstrip line TL3, where the microstrip line TL1 is connected to the microstrip line TL2 and the microstrip line TL3 in sequence.
In this embodiment, the input matching network control module 1 includes a microstrip line TL1, a microstrip line TL2, and a microstrip line TL3, where the microstrip line TL1 is sequentially connected to the microstrip line TL2 and the microstrip line TL3, where a parameter of the microstrip line TL1 is W-2.3 mm, L-5 mm, a parameter of the microstrip line TL2 is W-2 mm, and L-6.1 mm; the microstrip line TL3 has parameters W equal to 6mm and L equal to 1.5mm, and matching of input power is completed.
Further, the gate bias control module 2 includes a microstrip line TL4, a capacitor C4, and a capacitor C3, one end of the microstrip line TL4 is connected to the microstrip line TL3, the other end of the microstrip line TL4 is connected to one ends of the capacitor C4 and the capacitor C3, and the other ends of the capacitor C4 and the capacitor C3 are grounded.
In this embodiment, the gate bias control module 2 includes a microstrip line TL4, a capacitor C4, and a capacitor C3, one end of the microstrip line TL4 is connected to the microstrip line TL3, parameters of the microstrip line TL4 are W equal to 2mm and L equal to 18.5mm, capacitance values of the capacitor C4 and the capacitor C3 are 10pF and 24pF, respectively, and one ends of the capacitor C4 and the capacitor C3 are grounded, so as to improve safety of the class J power amplifier.
Further, the stabilizing network control module 3 includes a resistor R1 and a capacitor C2, one end of the resistor R1 and the capacitor C2 connected in parallel is connected to the microstrip line TL3, and the other end is connected to the transistor 4.
In this embodiment, the stabilizing network control module 3 includes a resistor R1 and a capacitor C2, one end of the resistor R1 and the capacitor C2 connected in parallel is connected to the microstrip line TL3, and the other end is connected to the transistor 4, wherein the parameter values of the resistor R1 and the capacitor C2 are 3 Ω and 3pF, respectively, so as to further improve the stability of the amplifier.
Further, the output matching network control module 5 includes a microstrip line TL5, a microstrip line TL6, a microstrip line TL7, a microstrip line TL8, a microstrip line TL9, and a microstrip line TL10, the microstrip line TL5, the microstrip line TL6, the microstrip line TL7, and the microstrip line TL8 are sequentially connected, and the microstrip line TL9 is respectively connected with the microstrip line TL7 and the microstrip line TL 10.
In this embodiment, the output matching network control module 5 includes a microstrip line TL5, a microstrip line TL6, a microstrip line TL7, a microstrip line TL8, a microstrip line TL9, and a microstrip line TL10, where a parameter of the microstrip line TL5 is W ═ 1.5mm, and L ═ 2.5 mm; the microstrip line TL6 has the parameters that W is 0.5mm and L is 1.6 mm; the microstrip line TL7 has the parameters that W is 0.5mm and L is 1.7 mm; the microstrip line TL8 has the parameters that W is 6mm and L is 9.5 mm; the microstrip line TL9 has the parameters of W being 0.8mm and L being 8 mm; the microstrip line TL10 has parameters W equal to 8.4mm and L equal to 3.1 mm. The microstrip line TL8 acts as an open stub to short-circuit the second harmonic to suppress the harmonic, so the electrical length of TL8 is about 45 ° at the center frequency, which is 90 ° for the second harmonic.
Further, the drain bias control module 6 includes a microstrip line TL11, a capacitor C5, a capacitor C6, and a capacitor C7, one end of the microstrip line TL11 is connected to the microstrip line TL7, the other end of the microstrip line TL11 is connected to one ends of the capacitor C5, the capacitor C6, and the capacitor C7, and the other ends of the capacitor C5, the capacitor C6, and the capacitor C7 are grounded.
In this embodiment, the drain bias control module 6 includes a microstrip line TL11, a capacitor C5, a capacitor C6, and a capacitor C7, where W is 6mm, and L is 16.4 mm; the capacitance values of the capacitor C5, the capacitor C6 and the capacitor C7 are 24pF, 12pF and 10pF respectively, the microstrip line TL11, the microstrip line TL7, the microstrip line TL8 and the microstrip line TL9 form a novel topological matching network, and as shown in fig. 5, the novel matching network can simultaneously realize good control on fundamental waves and second harmonics in a wide working frequency and can also play a good role in harmonic suppression. In the matching network, the microstrip line TL11 is connected as a short-circuit stub, and is drain dc offset, and its electrical length should be close to 90 ° at the center frequency to ensure that the output power does not leak; the microstrip line TL8 acts as an open stub to short-circuit the second harmonic to suppress the harmonics, so the electrical length of TL8 is about 45 ° at the center frequency, which is 90 ° for the second harmonic. In order to suppress the harmonic in a wide frequency band, it is effective to add an open-circuit or short-circuit microstrip line, and the microstrip lines at both ends respectively realize a short circuit to the second harmonic at positions above and below the off-center frequency. After the short circuit point, the second harmonic impedance value required by the J-type power amplifier can be realized through the action of the microstrip line TL 11.
Furthermore, the broadband efficient class-J power amplifier with the novel output matching method further comprises a capacitor C8, and the capacitor C8 is connected with the microstrip line TL 10.
In this embodiment, the wideband high-efficiency class-J power amplifier with the novel output matching method further includes a capacitor C8, the capacitor C8 is connected to the microstrip line TL10, the capacitor C8 serves as an output capacitor, and includes a capacitor between a drain-source capacitor and a gate-drain, and since the voltage between the gate and the drain has a small influence on the output capacitor, the nonlinear output capacitor is referred to as a drain-source capacitor in general. As can be seen from fig. 6, when the drain-source voltage is at a lower level (0< Vds <20V), the output capacitance exhibits a very strong nonlinear characteristic; when the drain-source voltage is kept at a high level (Vds >30V), the output capacitance exhibits a weak non-linear characteristic. The improvement of the power amplifier by in-depth analysis of the nonlinear characteristics of the output capacitor has proved to be an effective way to boost the power amplifier.
Further, the broadband efficient J-class power amplifier with the novel output matching method further comprises a dielectric substrate, the dielectric substrate is connected with the input matching network control module 1, the gate bias control module 2, the stabilizing network control module 3, the transistor 4, the output matching network control module 5 and the drain bias control module 6, and the dielectric substrate is made of Rogers 4350.
In this embodiment, the wideband high-efficiency class-J power amplifier with the novel output matching method further includes a dielectric substrate, the dielectric substrate is connected to the input matching network control module 1, the gate bias control module 2, the stabilizing network control module 3, the transistor 4, the output matching network control module 5, and the drain bias control module 6, and the dielectric substrate is made of Rogers 4350, which has good high-frequency characteristics and is suitable for designing a radio frequency circuit. The loss tangent value of Rogers 4350 is 0.004, the relative dielectric constant is 3.48 +/-0.05, the thickness is 0.508mm, and the thickness of the copper-clad layer is 34um, so that the efficiency of the J-type amplifier can be improved.
In order to check the effectiveness of the novel output matching method, a J-type power amplifier is designed based on a traditional design method, the manufactured traditional J-type power amplifier and an improved J-type power amplifier are compared and analyzed according to the indexes of output power and power added efficiency, as shown in fig. 7, the J-type power amplifier based on the improved design method is in a frequency band of 1.5-2.5GHz, the power gain is kept at about 12 +/-1 d B, the output power is 40.5-41.5 dBm, and the gain flatness is less than +/-1 d B. The power added efficiency is kept at the level of 61% -71.5%, and the efficiency is higher than that of a power amplifier designed by using a traditional method in the same frequency band, as shown in fig. 8. From the above data, it can be seen that the circuit design structure and efficiency improvement method proposed by the present design are feasible. By EM simulation of ADS2013 simulation software and combination of produced physical layouts, obtained experimental data prove that the novel matching method can improve the efficiency of the broadband power amplifier under the condition of ensuring the bandwidth of the power amplifier.
The design method is formed based on the improvement of the circuit structure and the utilization of the nonlinear characteristic of the output capacitor, the optimal impedance value is obtained without carrying out load traction, and only a novel matching network is needed to be adopted, and the equivalent model of the transistor is synthesized to carry out simulation design on the output matching circuit of the power amplifier, so that the aim of designing the high-efficiency broadband power amplifier is fulfilled. The design structure provided is simple in topological structure, easy to control and good in harmonic suppression capability and fundamental wave matching function.
The invention discloses a broadband efficient J-class power amplifier with a novel output matching method, which comprises an input matching network control module 1, a grid bias control module 2, a stabilizing network control module 3, a transistor 4, an output matching network control module 5 and a drain bias control module 6, wherein the input matching network control module 1, the stabilizing network control module 3, the transistor 4 and the output matching network control module 5 are sequentially connected, the grid bias control module 2 is connected with the input matching network control module 1, and the drain bias control module 6 is connected with the output matching network control module 5, and is combined with a novel topological network structure, so that the design process is simplified, and the J-class amplifier efficiency is improved.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. The broadband efficient J-class power amplifier with the novel output matching method is characterized by comprising an input matching network control module, a grid bias control module, a stabilizing network control module, a transistor, an output matching network control module and a drain bias control module, wherein the input matching network control module, the stabilizing network control module, the transistor and the output matching network control module are sequentially connected, the grid bias control module is connected with the input matching network control module, and the drain bias control module is connected with the output matching network control module.
2. The wideband high-efficiency class-J power amplifier with the novel output matching method according to claim 1, wherein the input matching network control module includes a microstrip line TL1, a microstrip line TL2 and a microstrip line TL3, and the microstrip line TL1 is connected to the microstrip line TL2 and the microstrip line TL3 in sequence.
3. The wideband high-efficiency class-J power amplifier with the novel output matching method according to claim 2, wherein the gate bias control module includes a microstrip line TL4, a capacitor C4 and a capacitor C3, one end of the microstrip line TL4 is connected to the microstrip line TL3, the other end of the microstrip line TL4 is connected to one ends of the capacitors C4 and C3, and the other ends of the capacitors C4 and C3 are grounded.
4. The wideband high-efficiency class-J power amplifier with the novel output matching method as claimed in claim 2, wherein the stabilizing network control module includes a resistor R1 and a capacitor C2, one end of the resistor R1 and the capacitor C2 connected in parallel is connected to the microstrip line TL3, and the other end is connected to the transistor.
5. The broadband high-efficiency class-J power amplifier with the novel output matching method according to claim 1, wherein the output matching network control module comprises a microstrip line TL5, a microstrip line TL6, a microstrip line TL7, a microstrip line TL8, a microstrip line TL9 and a microstrip line TL10, the microstrip line TL5, the microstrip line TL6, the microstrip line TL7 and the microstrip line TL8 are sequentially connected, and the microstrip line TL9 is respectively connected with the microstrip line TL7 and the microstrip line TL 10.
6. The broadband high-efficiency class-J power amplifier with the novel output matching method as claimed in claim 5, wherein the drain bias control module comprises a microstrip line TL11, a capacitor C5, a capacitor C6 and a capacitor C7, one end of the microstrip line TL11 is connected with the microstrip line TL7, the other end of the microstrip line TL11 is connected with one end of the capacitor C5, the capacitor C6 and one end of the capacitor C7, and the other ends of the capacitor C5, the capacitor C6 and the capacitor C7 are grounded.
7. The wideband high efficiency class J power amplifier with the novel output matching method as claimed in claim 5, further comprising a capacitor C8, wherein the capacitor C8 is connected to the microstrip line TL 10.
8. The wideband high efficiency class J power amplifier with the novel output matching method as claimed in claim 1, further comprising a dielectric substrate, the dielectric substrate is connected to the input matching network control module, the gate bias control module, the stabilization network control module, the transistor, the output matching network control module and the drain bias control module, and the material of the dielectric substrate is Rogers 4350.
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| CN112737531A (en) * | 2021-04-02 | 2021-04-30 | 成都理工大学 | J-type power amplifier |
| CN117240235A (en) * | 2023-11-16 | 2023-12-15 | 南京诺源医疗器械有限公司 | Power amplifying circuit and electronic system |
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Application publication date: 20200519 |